EECS 388: Embedded Systems

Lecture 8 – Instruction Processing and

Lidar
Fall 2024

Jacob Schoonover
Lecture notes based in part on slides created by Alex Fosdick,
Heechul Yun, Mohammad Alian, and Tamzidul Hoque

1
Agenda & Announcements
• Instruction Pipeline
• 5 minute break
• Review Lab 4

2
Homework 1 Correction

3
Context

Application Program

Operating
Compiler System Ch 5. Computer Organization and
Design
Machine Language (ISA)

Digital Logic

Electronic Circuits

Transistors

4
Control Unit
• Control unit orchestrates the execution of
each instruction

• Instruction Register (IR): the current

instruction being executed on the CPU

• Program Counter (PC): the address of the

next instruction to be executed

The Von Neumann computer model

5
Function of Control Unit
• Read an instruction from
memory into Instruction
Register (IR)
• By loading the memory
address pointed by PC

• Decodes the instruction

and generate control
signals that tell other
components what to do

6
Instruction Processing

Fetch Instruction From Memory

Decode the Instruction and Generate Control Signals

Execute the Instruction

Read or Write Data to Memory

Write Back Results into Register File

7
Instruction
Smallest unit of execution in a processor
• Carries two pieces of information
• Opcode: operation to be performed
• Operands: data to be used for operation
• Registers, immediate values, memory addresses
• Instructions are sequences of bits
• Instruction Set Architecture (ISA) is the
collection of all instructions that a
processor supports
8
 Instruction Example
Assembly Machine code
addi $sp, $sp, -32 0x23bdffe0

sw $s0, 24($sp) 0xafb00018

9
 Instruction in memory
Machine code in Main
PC addi $sp, $sp, -32 0x23bdffe0 Memory
Address Data /
sw $s0, 24($sp) 0xafb0001 Instructions
8
0x00 0x23
• Q1: What is the value of PC 0x01 0xbd
before any instruction is fetched? 0x02 0xff
0x03 0xe0
0x04 0xaf
• Q2: What is the endianness of the
0x05 0xb0
processor?
0x06 0x00
0x07 0x18
0x08 ….

10
#include <stdio.h>

int main ()
{
unsigned int x = 0x76543210;
char *c = (char*) &x;

printf ("*c is: 0x%x\n", *c);

if (*c == 0x10) //16 decimal

{
printf ("Underlying architecture is little endian. \n");
}
else
{
printf ("Underlying architecture is big endian. \n");
}
return 0;
}

11
 Instruction Processing: Fetch
F
• Read next instruction (pointed by PC) from
memory into IR
D

• Increment PC (so that it points to the next

instruction in memory) EXE

• Question: How much should you increment Mem

the PC after fetch stage in a processor that is
byte addressable and the width of each WB
instruction is 8 Bytes?

12
Updating PC for Jump Instruction
But we do not always fetch from the next address!

• Control flow instructions (JAL, BEQ, etc.) set the PC value to

something other than PC + 4

• E.g., JAL rd, imm20

• Semantics
• target_addr = PC + imm
• GPR[rd]  PC + 4
• PC  target_addr

13
 Instruction Processing: Decode
1. Identify the opcode and operands F
2. Generate control signal to perform
the tasks
D

Opcode Operands EXE

Mem

WB

14
 Instruction Processing: Execute
F

• Perform the operation

D
using the source operands
• E.g., -32 $sp addi $sp, $sp, -32 EXE

ADD
Mem
$sp- 32

WB

What are we doing to the stack with this instruction?

15
Instruction Processing: Memory
Operations
F
• If the instruction is a load or
store, then perform loading D
from or storing to memory
sw $s0, 24($sp) EXE

Mem
• Load/store also involves ALU
operation in EXE stage. What WB
ALU operation is that?

16
Instruction Processing: Write Back
• Update the register file with newly calculated
results F
• E.g.,
• Here, $sp register needs update after the D
addi is performed
EXE
addi $sp, $sp, -32

Mem

-32 $sp R0 <32 bit value> WB

R1 …
ADD … …
R29 SP – 32
$sp - 32
Register File

17
Illustration of CPU Datapath for
MIPS

How this architecture

operates for:
• Fetch
• Decode
• Execute
• Memory
• Write Back

Figure from Chapter 5 of Textbook: Computer Organization and Design, Revised Printing, Third Edition
Case Study: Atmel ATmega168
8 bit data bus

Atmel ATmega168 datasheet

19
Case Study: Atmel ATmega168
8 bit data bus

Instruction PC
Memory
Register
IR
File
Control
Unit
ALU

Data
IO
Memory

Atmel ATmega168 datasheet

20
???

21
22
23
Register Value
$zero 0x00000000
$v0 0x0000000A
$v1
…
$sp 0xFFFFFF02
$fp 0xFFFFFFA5
$ra 0x00008008

24
Initial State
$t0 0
$t1 40

Register
$t2 60
$s0 200
$s1
$s2
Address Data

Inst. Memory
0 add $t0, $t1, $t2
4 sw $s0, 4($t1)
8 beq $s1, $s2, 24

Address Data

Data Memory
40 0
44 0
48 0

25
 Fetch

Mem
EXE

WB
D
F
$t0 0
$t1 40

Register
$t2 60
$s0 200
$s1
$s2
Address Data

Inst. Memory
0 add $t0, $t1, $t2
4 sw $s0, 4($t1)
0
8 beq $s1, $s2, 24

Address Data

Data Memory
40 0
44 0
48 0

26
Fetch

Mem
EXE

WB
D
F
$t0 0
$t1 40

Register
$t2 60
$s0 200
$s1
$s2
Address Data

Inst. Memory
0 0 add $t0, $t1, $t2
4 sw $s0, 4($t1)
8 beq $s1, $s2, 24

Address Data

Data Memory
40 0
44 0
48 0
Program counter starts from 0

27
 Fetch

Mem
EXE

WB
D
F
$t0 0
$t1 40

Register
$t2 60
$s0 200
$s1
$s2
Address Data

Inst. Memory
add $t0,
0 $t1, $t2 0 add $t0, $t1, $t2
4 sw $s0, 4($t1)
8 beq $s1, $s2, 24

Address Data

Data Memory
40 0
44 0
48 0
Inst mem gets 0 as input, outputs the content at address 0

28
Fetch

Mem
EXE

WB
D
F
$t0 0
$t1 40

Register
$t2 60
$s0 200
$s1
$s2
add $t0, $t1, $t2

Address Data

Inst. Memory
add $t0,
0 $t1, $t2 0 add $t0, $t1, $t2
4 sw $s0, 4($t1)
8 beq $s1, $s2, 24

Address Data

Data Memory
40 0
44 0
48 0
Content at address 0 is the first instruction

29
Decode for Add

add $t0, $t1, $t2

Inst 25-21,
rs
Inst 20-16, rt

Inst 15-11,
rd
Inst 15-0, imm

30

30
Decode

Mem
EXE

WB
D
F
$t0 0
$t1 40

Register
$t2 60
$s0 200
$s1
$s2
Address Data

Inst. Memory
add $t0,
0 $t1, $t2 0 add $t0, $t1, $t2
$t1
$t2 4 sw $s0, 4($t1)
$t0 8 beq $s1, $s2, 24

Address Data

Data Memory
40 0
add 44 0
48 0
Instruction gets broken down into segments and goes to
register and control units

31
Decode

Mem
EXE

WB
D
F
$t0 0
$t1 40

Register
$t2 60
$s0 200
$s1
$s2
Address Data

Inst. Memory
add $t0,
0 $t1, $t2 0 add $t0, $t1, $t2
$t1
$t2 4 sw $s0, 4($t1)
$t0 8 beq $s1, $s2, 24

Address Data

Data Memory
Select Rt 40 0
add 44 0
48 0
Control signals are asserted

32
Decode

Mem
EXE

WB
D
F
$t0 0
$t1 40

Register
$t2 60
$s0 200
$s1
$s2
Address Data

Inst. Memory
add $t0, 40
0 $t1, $t2 0 add $t0, $t1, $t2
$t1
$t2 60 4 sw $s0, 4($t1)
$t0 8 beq $s1, $s2, 24

Address Data

Data Memory
40 0
add 44 0
48 0
Register data Rs and Rt comes out

33
Execute

Mem
EXE

WB
D
F
$t0 0
$t1 40

Register
$t2 60
$s0 200
$s1
$s2
Address Data

Inst. Memory
add $t0, 40
0 $t1, $t2 0 add $t0, $t1, $t2
$t1 100

$t2 60 60 4 sw $s0, 4($t1)

$t0 8 beq $s1, $s2, 24

Address Data

Data Memory
40 0
add Do Add 44 0
48 0
ALU Performs Add

34
Mem

Mem
EXE

WB
D
F
$t0 0
$t1 40

Register
$t2 60
$s0 200
$s1
$s2
Address Data

Inst. Memory
add $t0, 40
0 $t1, $t2 0 add $t0, $t1, $t2
$t1 100

$t2 60 60 4 sw $s0, 4($t1)

$t0 8 beq $s1, $s2, 24

Address Data

Data Memory
40 0
add No read/Write
44 0
48 0
Mem stage only needed for Load Store

35
Write Back

Mem
EXE

WB
D
F
$t0 100
$t1 40

Register
$t2 60
Select ALU out
$s0 200
$s1
10 10
0 0 $s2
Address Data

Inst. Memory
add $t0,
0 $t1, $t2 0 add $t0, $t1, $t2
4 sw $s0, 4($t1)
$t0 8 beq $s1, $s2, 24

Address Data

Data Memory
add

Write Back the result to $t0

36
Anytime

Mem
EXE

WB
D
F
Not a branch
$t0 100
PC+ $t1 40

Register
4
$t2 60
PC+4 $s0 200
$s1
$s2
Address Data

Inst. Memory
4 0 add $t0, $t1, $t2
4 sw $s0, 4($t1)
8 beq $s1, $s2, 24

Address Data

Data Memory
add

Update PC to PC+4 before next fetch

37
5 minute break

38
Lab 4: Lidar

39
Lab 4: Lidar

40
How the TFmini sends data

This is a "data packet"

• Byte 1 and 2: "Header"

• Byte 3 and 4: actual distance data (needs to be processed to get the real distance)
• Bytes 5 to 9: other information we do not need to worry about right now
How the TFmini sends data

• The actual distance measure is a 16-bit number

• This 16-bit number is sent in two 8-bit chunks
• Byte 3 is lower 8 bits, byte 4 is the higher 8 bits

1 0 0 0 1 1 1 0 0 1 0 1 1 1 0 1

Actual 16 bit number

0 1 0 1 1 1 0 1 1 0 0 0 1 1 1 0

Lower 8 bits (stored in byte 3 of Upper 8 bits (stored in byte 4 of

dataframe dataframe
Lab 4: Lidar

43