Simulation of Digital ciruits and

Embedded Protocols using Verilog

HDL

Internship Project Report (18EC74)

Submitted by,
Bhanu Prakash Sedamkar 1RV19EC037

Under the guidance of

Arunkumar P chavan
Professor
Dept. of ECE
RV College of Engineering

In partial fulfillment of the requirements for the degree of

Bachelor of Engineering in
Electronics and Communication Engineering
2022-23
 RV College of Engineering®, Bengaluru
(Autonomous institution affiliated to VTU, Belagavi )
Department of Electronics and Communication Engineering
.

CERTIFICATE
Certified that the internship project (18EC74)work titled Simulation of Digital ciruits
and Embedded Protocols using Verilog HDL is carried out by Bhanu Prakash
Sedamkar (1RV19EC037) who is bonafide student of RV College of Engineering,
Bengaluru, in partial fulfillment of the requirements for the degree of Bachelor of En-
gineering in Electronics and Communication Engineering of the Visvesvaraya
Technological University, Belagavi during the year 2022-23. It is certified that all cor-
rections/suggestions indicated for the Internal Assessment have been incorporated in the
minor project report deposited in the departmental library. The internship project report
has been approved as it satisfies the academic requirements in respect of internship project
work prescribed by the institution for the said degree.

Guide Head of the Department Principal

Arunkumar P chavan Dr. H. V. Ravish Aradhya Dr. K. N. Subramanya

External Viva

Name of Examiners Signature with Date

1.

2.
 DECLARATION

I, Bhanu Prakash Sedamkar students of seventh semester B.E., Department of Elec-

tronics and Communication Engineering, RV College of Engineering, Bengaluru, hereby
declare that the internship project titled ‘Simulation of Digital ciruits and Embed-
ded Protocols using Verilog HDL’ has been carried out by me and submitted in
partial fulfilment for the award of degree of Bachelor of Engineering in Electronics
and Communication Engineering during the year 2022-23.

Further I declare that the content of the dissertation has not been submitted previously
by anybody for the award of any degree or diploma to any other university.

I also declare that any Intellectual Property Rights generated out of this project carried
out at RVCE will be the property of RV College of Engineering, Bengaluru and we will
be one of the authors of the same.

Place: Bengaluru

Date:

Name Signature

1. Bhanu Prakash Sedamkar(1RV19EC037)

 ACKNOWLEDGEMENT

I am indebted to my guide, Arunkumar P chavan, Professor, RV College of

Engineering . for the wholehearted support, suggestions and invaluable advice throughout
this internship work and also helped in the preparation of this thesis.

I also express our gratitude to my panel members Dr. H. V. Ravish Aradhya,

Professor and Arunkumar P Chavan, Assistant Professor, Department of Electronics
and Communication Engineering for their valuable comments and suggestions during the
phase evaluations.

My sincere thanks to the project coordinators Prof. Sindhu Rajendran R and Dr

Veena Devi for their timely instructions and support in coordinating the project.

My gratitude to Prof. Narashimaraja P for the organized latex template which

made report writing easy and interesting.

My sincere thanks to Dr. H. V. Ravish Aradhya, Professor and Head, Department

of Electronics and Communication Engineering, RVCE for the support and encourage-
ment.

I express sincere gratitude to our beloved vice Principal, Dr. K. S Geetha and
Principal, Dr. K. N. Subramanya for the appreciation towards this project work.

I thank all the teaching staff and technical staff of Electronics and Communication
Engineering department, RVCE for their help.

Lastly, I take this opportunity to thank my family members and friends who provided
all the backup support throughout the project work.
 SYNOPSIS

The primary goal of this project is to provide SPI (Serial Peripheral Interface) connec-
tion between the FPGA (Field Programmable Gate Array), which serves as the master
device, and any slave devices (which can be any device which we want to interface). For
successful communication from the master device (FPGA) to any slave device that we
want to connect, the four SPI communication modes are tested, simulated, and validated
here.

By adjusting Clock Priority (CPOL) and Clock Phase, several modes of SPI can be
activated (CPHA). When the mode is 0, Clock phase is configured such that data is
sampled on the rising edge of the clock pulse and shifted out on the falling edge of the
clock pulse. When it is mode 1, Clock phase is configured such that data is sampled on
the falling edge of the clock pulse and shifted out on the rising edge of the clock pulse.
Whereas, Clock phase is configured such that data is sampled on the falling edge of the
clock pulse and shifted out on the rising edge of the clock pulse, when the mode is 2.
While, Clock phase is configured such that data is sampled on the rising edge of the clock
pulse and shifted out on the falling edge of the clock pulse, when it’s in mode 3.

Universal Asynchronous Receiver/Transmitter is referred to as UART. It is a physical

circuit in a microcontroller or standalone IC, not a communication standard like SPI and
I2C. The primary function of a UART is to send and receive serial data. The fact that
UART just requires two wires to communicate data between devices is one of its finest
features.

The results of the UART transmission protocol was verified using Vivado and opti-
mized code for the same was developed. It is observed that UART transmission is slower
then that of SPI. The data rate of the UART devices communicating with each other
must be equal due to the asynchronous type of communication.

i
 CONTENTS

Synopsis i

List of Figures iv

1 Profile of the organization 1

1.1 Vision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Mission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Activities of the Department 4

2.1 About the department . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Manpower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Tasks Performed 7
3.1 TASK 1: Introduction to verilog . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.1 Very large scale integration . . . . . . . . . . . . . . . . . . . . . 8
3.1.2 Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 TASK 2: Software and Hardware tools that used in Verilog . . . . . . . . 11
3.2.1 VIVADO: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.2 FPGA: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 TASK 3: Building Basic circuit using verilog . . . . . . . . . . . . . . . . 12
3.3.1 Combinational Digital Circuits . . . . . . . . . . . . . . . . . . . 13
3.3.2 Sequential Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 TASK 4: Development of SPI Master using VHDL . . . . . . . . . . . . 18
3.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.2 SPI Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.3 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

ii
 3.5 Task 5: Development of UART communication using Verilog . . . . . . . 25
3.5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5.2 Working of UART . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.3 Steps involved in UART Transmission . . . . . . . . . . . . . . . 27
3.5.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4 Reflections 29
4.1 TASK 1: Introduction to verilog . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 TASK 2: Software and Hardware tools that used in Verilog . . . . . . . . 30
4.3 TASK 3: Building Basic Circuits using Verilog . . . . . . . . . . . . . . . 31
4.4 TASK 4: Development of SPI Master using verilog . . . . . . . . . . . . 31
4.5 TASK 5: Development of UART Communication using Verilog . . . . . . 32

iii
 LIST OF FIGURES

1.1 Logo of Vyorius . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3.1 Finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2 Mealy sate machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Moore sate machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Vivado tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Block diagram of combinational circuits . . . . . . . . . . . . . . . . . . . 13
3.7 Block diagram of Sequential circuits . . . . . . . . . . . . . . . . . . . . . 14
3.8 Block diagram of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.9 Independent Slave configuration . . . . . . . . . . . . . . . . . . . . . . . 19
3.10 Daisy chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11 Block diagram of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12 Mode 0 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.13 Mode 1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14 Mode 2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.15 Mode 3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16 UART communiction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17 Data packet in UART communiction . . . . . . . . . . . . . . . . . . . . 26
3.18 Block diagram of UART communiction . . . . . . . . . . . . . . . . . . . 28
3.19 Simulation results of UART communiction . . . . . . . . . . . . . . . . . 28

iv
 RV College of Engineering® , Bengaluru - 560059

Chapter 1
Profile of the organization

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CHAPTER 1
PROFILE OF THE ORGANIZATION
Name of the Organization: Vyorius,

Figure 1.1: Logo of Vyorius

Vyorius is a Delhi based semiconductor foundry that specializes in the production of

very large scale integration (VLSI) integrated circuits (ICs), Drones and Robotics The
company was founded in 1980 and has since become one of the major semiconductor
foundries in the world, with a strong focus on innovation and the development of new
technologies. In addition to its manufacturing capabilities, It also has a research and
development team that is focused on developing new VLSI technologies and designs. The
company is committed to delivering high-quality products to its customers in the VLSI
industry. The company has a strong track record of innovation and is constantly working
on new technologies and processes to improve the performance and efficiency of its ICs.
In addition to its core business, It is also involved in a number of initiatives aimed at
improving sustainability and reducing the environmental impact of its operations. In
addition to its manufacturing and R and D capabilities, It is also known for its strong
customer service and support. The company has a team of experienced technical profes-
sionals who are available to help customers with any questions or issues that may arise.
It is committed to building strong relationships with its customers and works closely with
them to understand their specific needs and requirements.
Overall, Vyorius is a great company in the VLSI industry and is known for its com-

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mitment to innovation, customer service, and sustainability. The company has a strong
track record of delivering high-quality products and services to its customers and is well-
positioned for continued growth and success in the future.

1.1 Vision
• To be a leader in the VLSI industry and a trusted partner for customers

• To be at the forefront of innovation and technology development in the field of VLSI

• To achieve long-term growth and success through a focus on excellence and contin-
uous improvement

1.2 Mission
• To design and manufacture high-quality VLSI integrated circuits (ICs) that meet
the needs of customers and end users

• To continuously improve the performance and efficiency of VLSI ICs through the
development of new technologies and processes

• To provide excellent customer service and support to ensure customer satisfaction

• Empowering innovation which enhances the human experience by delivering smart,

connected and secure technology solutions.

• To establish indigenous production capability through Industry partnership to achieve

total self-reliance in the field Robotics.

• To promote in-house Research, engage Academia and Industry to build competence

towards creating to provide Excellence in the field of VLSI and Robotic Technolo-
gies.

• To provide operationalization and life cycle support to the Users.

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Chapter 2
Activities of the Department

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CHAPTER 2
ACTIVITIES OF THE DEPARTMENT
2.1 About the department
A semiconductor foundry with its headquarters in Delhi called Vyorius produces VLSI
integrated circuits (ICs), drones, and robotics. The company subsequently emerged as
a significant semiconductor manufacturer. foundries in the globe, with an emphasis on
new technology research and innovation. It has a research and development staff that
is dedicated to creating new VLSI technology and designs in addition to its production
capabilities. The business is dedicated to providing its VLSI sector clients with top-notch
goods. The business has a proven track record of innovation and is always developing
new technologies and procedures to enhance the functionality and effectiveness of its
integrated circuits (ICs).

2.2 Manpower
Vyorius has current employer profiles, including Co-Founder and Board Member Amit
Kumar Singh.

• Amit Kumar Singh Co-Founder and Board Member

• Pankaj Kumar Co-Founder and CTO

• Nishant Singh Rana Founder and CEO

This training program conducted by Amit Kumar Singh Co-Founder and Board Mem-
ber,Pankaj Kumar Co-Founder and CTO and Nishant Singh Rana Founder and CEO,
was 8 weeks online training with strong fundamental approach towards learning basic fun-
damentals of verilog and FPGA addressing the needs of industry and society along with
development and integration of hardware and software components. The organization
provided the certification after the successful completion of the internship.

2.3 Services
• In vyorius, they make appropriate policies for planning, monitoring and effective
utilization of the grants, from time to time.

• Approving the strategies for branding of the activities of department.

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• Approve the activities of the department as planned and budget proposals.

• Approve annual report of the department.

• Perform such other functions and constitute committees, as may be necessary and
deemed fit for the proper development, and to fulfill the objectives of the depart-
ment.

• Develop employable human resource to meet the challenges in the field of Robotics

2.4 Products
The training programme was designed to give participants the opportunity to broaden
their knowledge and skills in core vlsi and embedded concepts, hardware, and software-
oriented solutions for a variety FPGA applications. Beginners (students, faculty, and
industry professionals) who are interested in developing a FPGA applications can ben-
efit from the training programme in VLSI. Provide structured training, Bridge the gap
between theoretical knowledge and market requirement.Create a pool of professional en-
gineers employable in a multitude of industries. Enhance multi-disciplinary capabilities.

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Chapter 3
Tasks Performed

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CHAPTER 3
TASKS PERFORMED
Chapter 3 deals with the various tasks performed in internship. The internship focuses
on implementation of verilog. There were 8 weeks of internship. Week 1 to week 4 was an
introductory course that dealt with understanding the basics of verilog system. Week 5
and week 6 was about implementation of basic circuits using vivado and implementation
on FPGA.Week 7 and Week 8 was about working on project.

3.1 TASK 1: Introduction to verilog

Verilog is a Hardware description language. It is a language used for describing a
digital system like a network switch or a microprocessor or a memory or a flip flop. It
means, by using a HDL we can describe any digital hardware at any level. Designs,
which are described in HDL are independent of technology, very easy for designing and
debugging, and are normally more useful than schematics, particularly for large circuits.

3.1.1 Very large scale integration

Very large-scale integration (VLSI) is the process of integrating or embedding hun-
dreds of thousands of transistors on a single silicon semiconductor microchip. VLSI
technology was conceived in the late 1970s when advanced level computer processor mi-
crochips were under development.
VLSI is one of the most widely used technologies for microchip processors, integrated
circuits (IC) and component designing. It was initially designed to support hundreds of
thousands of transistor gates on a microchip which, as of 2012, exceeded several billion.
All of these transistors are remarkably integrated and embedded within a microchip that
has shrunk over time but still has the capacity to hold enormous amounts of transistors.

3.1.2 Finite State Machine

A finite-state machine (FSM) as in figure 3.1 or finite-state automaton (FSA), finite
automaton, or simply a state machine, is a mathematical model of computation. It is an
abstract machine that can be in exactly one of a finite number of states at any given time.
The FSM can change from one state to another in response to some inputs, the change
from one state to another is called a transition.An FSM is defined by a list of its states, its
initial state, and the inputs that trigger each transition. Finite-state machines are of two

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types—deterministic finite-state machines and non-deterministic finite-state machines.A

deterministic finite-state machine can be constructed equivalent to any non-deterministic
one.[1]

Figure 3.1: Finite state machine

The behavior of state machines can be observed in many devices in modern society
that perform a predetermined sequence of actions depending on a sequence of events
with which they are presented. Simple examples are vending machines, which dispense
products when the proper combination of coins is deposited, elevators, whose sequence of
stops is determined by the floors requested by riders, traffic lights, which change sequence
when cars are waiting, and combination locks, which require the input of a sequence of
numbers in the proper order.
Types of Finite State Machine
The finite state machines are classified into two types such as Mealy state machine
and Moore state machine.

Mealy State Machine:

When the outputs depend on the current inputs as well as states, then the FSM can be
named to be a mealy state machine. The following diagram is the mealy state machine
block diagram. The mealy state machine block diagram consists of two parts namely
combinational logic as well as memory. The memory in the machine can be used to
provide some of the previous outputs as combinational logic inputs.Based on the current
inputs as well as states, this machine can produce outputs. Thus, the outputs can be
suitable only at positive otherwise negative of the CLK signal as in Figure 3.2.
Generally, the amount of required states in the mealy machine is below or equivalent
to the number of required states in Moore state machine. There is an equal Moore state
machine for every Mealy state machine. As a result, based on the necessity we can employ

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Figure 3.2: Mealy sate machine

one of them.

Moore State Machine:

When the outputs depend on current states then the FSM can be named as Moore
state machine. The Moore state machine’s block diagram is shown below. The Moore
state machine block diagram consists of two parts namely combinational logic as well as
memory as in Figure 3.3.

Figure 3.3: Moore sate machine

In this case, the current inputs, as well as current states, will decide the next states.
Thus, depending on further states, this machine will generate the outputs. So, the outputs
of this will be applicable simply after the conversion of the state.Generally, the amount
of required states in this machine is greater than otherwise equivalent to the required
number of states in the mealy state machine.

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3.2 TASK 2: Software and Hardware tools that used

in Verilog
3.2.1 VIVADO:
Vivado was introduced in April 2012 and is an integrated design environment (IDE)
with system-to-IC level tools built on a shared scalable data model and a common debug
environment. Vivado includes electronic system level (ESL) design tools for synthesizing
and verifying C-based algorithmic IP; standards based packaging of both algorithmic and
RTL IP for reuse; standards based IP stitching and systems integration of all types of sys-
tem building blocks; and the verification of blocks and systems.A free version WebPACK
Edition of Vivado provides designers with a limited version of the design environment.

Figure 3.4: Vivado tool

AS figure 3.4 Vivado Design Suite is a software suite produced by Xilinx for synthesis and
analysis of hardware description language (HDL) designs, superseding Xilinx ISE with
additional features for system on a chip development and high-level synthesis. Vivado
represents a ground-up rewrite and re-thinking of the entire design flow

3.2.2 FPGA:
Field Programmable Gate Array (FPGA) as in Figure 3.5 is an integrated circuit that
consists of internal hardware blocks with user-programmable interconnects to customize
operation for a specific application. The interconnects can readily be reprogrammed,
allowing an FPGA to accommodate changes to a design or even support a new ap-
plication during the lifetime of the part. The FPGA has its roots in earlier devices
such as programmable read-only memories (PROMs) and programmable logic devices

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Figure 3.5: FPGA

(PLDs). These devices could be programmed either at the factory or in the field, but
they used fuse technology (hence, the expression “burning a PROM”) and could not be
changed once programmed. In contrast, FPGA stores its configuration information in a
re-programmable medium such as static RAM (SRAM) or flash memory.

3.3 TASK 3: Building Basic circuit using verilog

A Digital Signal is a type of Signal that has two discrete levels, either HIGH (1) or
LOW (0). These two levels are usually represented by

• LOGIC 1 = HIGH = TRUE = ON = YES

• LOGIC = LOW = FALSE = OFF = NO

The concept of the Binary number system is the accurate representation of Digital
Signals. Digital Signals work on the principles of Boolean Algebra, binary mathematics
developed by George Boolean.
Digital Signals operate at high speeds and drive Digital Circuits that contain some
basic components such as Diodes, Inductors, Capacitors, Resistors, Batteries, and Logic
Gates.

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3.3.1 Combinational Digital Circuits

The combinational logic circuits are the circuits that contain different types of logic
gates. Simply, a circuit in which different types of logic gates are combined is known as a
combinational logic circuit. The output of the combinational circuit is determined from
the present combination of inputs, regardless of the previous input as in 3.6 [2].

Figure 3.6: Block diagram of combinational circuits

The input variables, logic gates, and output variables are the basic components of the
combinational logic circuit. There are different types of combinational logic circuits, such
as Adder, Subtractor, Decoder, Encoder, Multiplexer, and De-multiplexer.

1. Half Adder:The half adder is a basic building block having two inputs and two
outputs. The adder is used to perform OR operation of two single bit binary
numbers. The carry and sum are two output states of the half adder.

2. Full Adder:The half adder is used to add only two numbers. To overcome this
problem, the full adder was developed. The full adder is used to add three 1-bit
binary numbers A, B, and carry C. The full adder has three input states and two
output states i.e., sum and carry.

3. Half subtractor:The half subtractor is also a building block of subtracting two

binary numbers. It has two inputs and two outputs. This circuit is used to subtract
two single bit binary numbers A and B. The ’diff’ and ’borrow’ are the two output
state of the half adder.

4. Full Subtractor:The Half Subtractor is used to subtract only two numbers. To

overcome this problem, full subtractor was designed. The full subtractor is used
to subtract three 1-bit numbers A, B, and C, which are minuend, subtrahend, and
borrow, respectively. The full subtractor has three input states and two output
states i.e., diff and borrow.

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5. Multiplexer:The multiplexer is a combinational circuit that has n-data inputs and

a single output. It is also known as the data selector which selects one input from
the inputs and routes it to the output. With the help of the selected inputs, one
input line from the n-input lines is selected. The enable input is denoted by E,
which is used in cascade.

6. De-Multiplexer:A De-multiplexer performs the reverse operation of a multiplexer.

The de-multiplexer has only one input, which is distributed over several outputs.
One output line is selected at a time by selecting lines. The input is transmitted
to the selected output line.

7. Decoder:A decoder is a combinational circuit having n inputs and to a maximum

of m = 2n outputs. The decoder is the same as the de-multiplexer. The only
difference between de-multiplexer and decoder is that in the decoder, there is no
data input. The decoder performs an operation that is completely opposite of an
encoder.

8. Encoder:The encoder is used to perform the reverse operation of the decoder. An

encoder having n number of inputs and m number of outputs is used to produce
m-bit binary code which is related to the digital input number. The encoder takes
the digital word and converts it into another digital word.

3.3.2 Sequential Circuits

In our previous sections, we learned about combinational circuit and their working.
The combinational circuits have set of outputs, which depends only on the present com-
bination of inputs. Below is the block diagram 3.7 of the synchronous logic circuit.

Figure 3.7: Block diagram of Sequential circuits

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The sequential circuit is a special type of circuit that has a series of inputs and outputs.
The outputs of the sequential circuits depend on both the combination of present inputs
and previous outputs. The previous output is treated as the present state. So, the
sequential circuit contains the combinational circuit and its memory storage elements.
A sequential circuit doesn’t need to always contain a combinational circuit. So, the
sequential circuit can contain only the memory element[3].
Types of Sequential circuits
The Sequential Circuits are classified into two types such as Asynchronous sequential
circuits and synchronous sequential circuits.

Asynchronous sequential circuits

The clock signals are not used by the Asynchronous sequential circuits. The asyn-
chronous circuit is operated through the pulses. So, the changes in the input can change
the state of the circuit. The asynchronous circuits do not use clock pulses. The internal
state is changed when the input variable is changed. The un-clocked flip-flops or time-
delayed are the memory elements of asynchronous sequential circuits. The asynchronous
sequential circuit is similar to the combinational circuits with feedback.

synchronous sequential circuits

In synchronous sequential circuits, synchronization of the memory element’s state is
done by the clock signal. The output is stored in either flip-flops or latches(memory
devices). The synchronization of the outputs is done with either only negative edges of
the clock signal or only positive edges.
Flip Flop
A circuit that has two stable states is treated as a flip flop. These stable states are
used to store binary data that can be changed by applying varying inputs. The flip flops
are the fundamental building blocks of the digital system. Flip flops and latches are
examples of data storage elements. In the sequential logical circuit, the flip flop is the
basic storage element[4]. The latches and flip flops are the basic storage elements but
different in working. There are the following types of flip flops:

1. S-R flip flop:The S-R flip flop is the most common flip flop used in the digital
system. In SR flip flop, when the set input ”S” is true, the output Y will be high,
and Y’ will be low. It is required that the wiring of the circuit is maintained when

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the outputs are established. We maintain the wiring until set or reset input goes
high, or power is shutdown.

2. JK flip flop:The JK flip flop is used to remove the drawback of the S-R flip flop,
i.e., undefined states. The JK flip flop is formed by doing modification in the SR
flip flop. The S-R flip flop is improved in order to construct the J-K flip flop. When
S and R input is set to true, the SR flip flop gives an inaccurate result. But in the
case of JK flip flop, it gives the correct output.

3. D flip flop:D flip flop is a widely used flip flop in digital systems. The D flip flop
is mostly used in shift-registers, counters, and input synchronization.

4. T flip flop:Just like JK flip-flop, T flip flop is used. Unlike JK flip flop, in T flip
flop, there is only single input with the clock input. The T flip flop is constructed
by connecting both of the inputs of JK flip flop together as a single input.

Shift Registers
A group of flip flops which is used to store multiple bits of data and the data is moved
from one flip flop to another is known as Shift Register. The bits stored in registers
shifted when the clock pulse is applied within and inside or outside the registers. To
form an n-bit shift register, we have to connect n number of flip flops. So, the number
of bits of the binary number is directly proportional to the number of flip flops. The flip
flops are connected in such a way that the first flip flop’s output becomes the input of
the other flip flop.
A Shift Register can shift the bits either to the left or to the right. A Shift Register,
which shifts the bit to the left, is known as ”Shift left register”, and it shifts the bit to
the right, known as ”Right left register”.
The shift register is classified into the following types:

• Serial In Serial Out

• Serial In Parallel Out

• Parallel In Serial Out

• Parallel In Parallel Out

• Bi-directional Shift Register

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Counters
A special type of sequential circuit used to count the pulse is known as a counter, or
a collection of flip flops where the clock signal is applied is known as counters.
The counter is one of the widest applications of the flip flop. Based on the clock pulse,
the output of the counter contains a predefined state. The number of the pulse can be
counted using the output of the counter.

1. Ripple counter:Ripple counter is a special type of Asynchronous counter in which

the clock pulse ripples through the circuit. The n-MOD ripple counter forms by
combining n number of flip-flops. The n-MOD ripple counter can count 2n states,
and then the counter resets to its initial value

(a) Up-counter:The up-counter counts the states in ascending order.

(b) Down-counter:The down counter counts the states in descending order.

(c) Up-down Counter:The up and down counter is a special type of bi-directional

counter which counts the states either in the forward direction or reverse di-
rection. It also refers to a reversible counter.

2. Ring counter:A ring counter is a special type of application of the Serial IN Serial
OUT Shift register. The only difference between the shift register and the ring
counter is that the last flip flop outcome is taken as the output in the shift register.
But in the ring counter, this outcome is passed to the first flip flop as an input. All
of the remaining things in the ring counter are the same as the shift register.

3. Johnson counter:The Johnson counter is similar to the Ring counter. The only
difference between the Johnson counter and the ring counter is that the outcome of
the last flip flop is passed to the first flip flop as an input. But in Johnson counter,
the inverted outcome Q’ of the last flip flop is passed as an input. The remaining
work of the Johnson counter is the same as a ring counter. The Johnson counter is
also referred to as the Creeping counter.

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3.4 TASK 4: Development of SPI Master using VHDL

This project mainly aims at establishing an SPI (Serial Peripheral Interface) com-
munication between the master device (FPGA) and any slave device (which can be any
device which we want to interface). Here, the 4 modes of SPI communication are tested,
simulated and verified for effective communication from the master device(FPGA) to any
slave device which we want to interface.

3.4.1 Introduction
The Serial Peripheral Interface (SPI) [5]is a synchronous serial communication inter-
face specification used for short-distance communication, primarily in embedded systems.
SPI devices communicate in full duplex mode using a master-slave architecture usually
with a single master (though some Atmel devices support changing roles on the fly de-
pending on an external (SS) pin). The master (controller) device originates the frame for
reading and writing[6]. Multiple slave-devices may be supported through selection with
individual chip select (CS), sometimes called slave select (SS) lines as in Figure 3.8.

Figure 3.8: Block diagram of SPI

The SPI bus specifies four logic signals[7]:

• SCLK: Serial Clock (output from master)

• MOSI: Master Out Slave In (data output from master)

• MISO: Master In Slave Out (data output from slave)

• CS /SS: Chip/Slave Select (often active low, output from master to indicate that
data is being sent)

MOSI on a master connects to MOSI on a slave. MISO on a master connects to

MISO on a slave. Slave Select has the same functionality as chip select and is used
instead of an addressing concept. In addition to setting the clock frequency, the master
must also configure the clock polarity (CPOL) and clock phase (CPHA) with respect to

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the data. The combinations of polarity and phases are often referred to as modes which
are commonly numbered according to the following convention, with CPOL as the high
order bit and CPHA as the low order bit. Therefore, there are 4 modes of operations,
which we shall explore in this project.

3.4.2 SPI Configurations

There are two types of configurations in which the SPI devices can be connected in
an SPI bus.
They are Independent Slave Configuration and Daisy Chain Configuration:

• In Independent Slave Configuration,[7] the master has dedicated Slave Select

Lines for all the slaves and each slave can be selected individually. All the clock
signals of the slaves are connected to the master SCK. Similarly, all the MOSI pins
of all the slaves are connected to the MOSI pin of the master and all the MISO pins
of all the slaves are connected to the MISO pin of the master as in Figure 3.9.

Figure 3.9: Independent Slave configuration

Figure 3.10: Daisy chain configuration

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• In Daisy Chain Configuration, only a single Slave Select line is connected to all
the slaves. The MOSI of the master is connected to the MOSI of slave 1. MISO
of slave 1 is connected to MOSI of slave 2 and so on. The MISO of the final slave
is connected to the MISO of the master. Consider the master transmits 3 bytes of
data into the SPI bus. First, the 1st byte of data is shifted to slave 1. When the
2nd byte of data reaches slave 1, the first byte is pushed into slave 2[8]. When the
3rd byte of data arrives into the first slave, the 1st byte of data is shifted to slave
3 and the 2nd byte of data is shifted into 2nd slave as in Figure 3.10.

3.4.3 Methodology

Table 3.1: Modes of SPI

MODE CPOL CPHA
0 0 0
1 0 1
2 1 0
3 1 1

Different mode of SPI can be Activate by setting Clock priority(CPOL) and Clock
Phase(CPHA) as in Table 3.1[9]

1. Mode 0: Clock phase is configured such that data is sampled on the rising edge
of the clock pulse and shifted out on the falling edge of the clock pulse.

2. Mode 1:Clock phase is configured such that data is sampled on the falling edge of
the clock pulse and shifted out on the rising edge of the clock pulse.

3. Mode 2: Clock phase is configured such that data is sampled on the falling edge
of the clock pulse and shifted out on the rising edge of the clock pulse.

4. Mode 3:Clock phase is configured such that data is sampled on the rising edge of
the clock pulse and shifted out on the falling edge of the clock pulse.

3.4.4 Block Diagram

verilog code that demonstrates the working of these 4 modes of SPI6 Communica-
tion and the required design specifications and methodologies have been explained with
the help of a block diagram as shown in Figure 3.11. As we can see from the block
diagram there are two modules, one for Clock Division and another one which defines

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Figure 3.11: Block diagram of SPI

the working of the SPI Master. The Clock Division module is necessary to ensure that
SPI communication happens at a proper clock frequency which is usually less than the
typical clock frequency of the FPGA master device ( in our design we have the SPI
clock frequency, SCK, equal to ¼ th of the clock frequency of the Master). Generally, we
have a PS (prescale factor) and the output clock is 2 power (-PS) times the input clock
frequency[10].

PORTS
The Clock Division module has the following ports :
INPUT:

• iclk: This is the input clock frequency fed to the master device (FPGA).

• rst: This is the reset input.

• ps: ps is the Prescale factor, i.e the factor by which we want to reduce the clock
frequency of the input clock so that SPI communication can be established. ps is
configured as an input to this module.

• mode: This is the input which is used to select the mode of operation of SPI
Communication. (There are 4 modes). mode is an input to this module.

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OUTPUT:

• oclk: oclk is the output that is obtained from this module which gives the resulting
clock frequency at which SPI communication is destined to happen.

The SPI module has the following ports :

INPUT:

• iclk, rst: iclk is the input clock and rst is the input reset.

• MISO: MISO is the Master In Slave Out input pin which is used to send data to
the master device.

• t: t is an 8 bit vector which represents the Transmission byte to be transmitted

from the master to the slave device.

• tv: tv is a single bit input variable that represents a transmission byte valid signal,
which sends a control signal to the fpga board indicating it is ready for transmis-
sion[11].

• mode, ps: mode and ps are the same as defined above in the clock division module.

OUTPUT:

• r: r is an 8 bit vector which represents a received byte to be sent out by the master
device to the slave device.

• rv: rv is the received byte valid output signal which sends a control signal indicating
that the master device is ready to receive the data.

• CSN: CSN is the chip select signal which is active low, and is used to select the
slave device with which communication is to be established.

• MOSI: MOSI is the Master Out Slave In output pin which is used to send data
from the master device.

• SCK: SCK is the Serial clock output which represents the clock frequency at which
the SPI communication takes place.

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Figure 3.12: Mode 0 SPI

3.4.5 Simulation Results

Mode 0: Clock phase is configured such that data is sampled on the rising edge of
the clock pulse and shifted out on the falling edge of the clock pulse as in Figure 3.12.
Mode 1:Clock phase is configured such that data is sampled on the falling edge of
the clock pulse and shifted out on the rising edge of the clock pulse as in Figure 3.13.

Figure 3.13: Mode 1 SPI

Mode 2: Clock phase is configured such that data is sampled on the falling edge of
the clock pulse and shifted out on the rising edge of the clock pulse as in Figure 3.14.
Mode 3:Clock phase is configured such that data is sampled on the rising edge of
the clock pulse and shifted out on the falling edge of the clock pulse as in Figure 3.15.

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Figure 3.14: Mode 2 SPI

Figure 3.15: Mode 3 SPI

3.4.6 Conclusion
This project was done to test the Serial Peripheral Interfaces (SPI) communication
modes using an FPGA board as an SPI master. The results of the simulation show
that an SPI communication was established from the master device. This shows that by
interfacing with other slave devices, serial communication can be easily and effectively
established. This module is easily portable and this code can be used to test the modes
of SPI communication of any FPGA board and also can be easily used in any design
specification that makes use of SPI communication. SPI finds a lot of applications in
modern day life. It is used in MMC or SD card including SDIO variant, in audio or
video codecs, in digital potentiometers, in flash and EEPROM memories, in real time
clocks and in LCD and LED. SPI can be used to talk to a variety of peripherals such
as sensors i.e. temperature and pressure, analog to digital converter (ADC), digital to
analog converter (DAC).

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3.5 Task 5: Development of UART communication

using Verilog
UART stands for Universal Asynchronous Receiver/Transmitter. It’s not a com-
munication protocol like SPI and I2C, but a physical circuit in a microcontroller, or a
stand-alone IC. A UART’s main purpose is to transmit and receive serial data.
One of the best things about UART is that it only uses two wires to transmit data
between devices.

3.5.1 Introduction
In UART communication, two UARTs communicate directly with each other. The
transmitting UART converts parallel data from a controlling device like a CPU into serial
form, transmits it in serial to the receiving UART, which then converts the serial data
back into parallel data for the receiving device. Only two wires are needed to transmit
data between two UARTs. Data flows from the Tx pin of the transmitting UART to the
Rx pin of the receiving UART as in Figure 3.16

Figure 3.16: UART communiction

UARTs transmit data asynchronously, which means there is no clock signal to syn-
chronize the output of bits from the transmitting UART to the sampling of bits by the
receiving UART[12]. Instead of a clock signal, the transmitting UART adds start and
stop bits to the data packet being transferred. These bits define the beginning and end
of the data packet so the receiving UART knows when to start reading the bits.
When the receiving UART detects a start bit, it starts to read the incoming bits at a
specific frequency known as the baud rate. Baud rate is a measure of the speed of data
transfer, expressed in bits per second (bps)[13]. Both UARTs must operate at about the
same baud rate. The baud rate between the transmitting and receiving UARTs can only
differ by about 10 Percent before the timing of bits gets too far off.

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3.5.2 Working of UART

The UART that is going to transmit data receives the data from a data bus. The
data bus is used to send data to the UART by another device like a CPU, memory, or
microcontroller. Data is transferred from the data bus to the transmitting UART in
parallel form. After the transmitting UART gets the parallel data from the data bus, it
adds a start bit, a parity bit, and a stop bit, creating the data packet. Next, the data
packet is output serially, bit by bit at the Tx pin. The receiving UART reads the data
packet bit by bit at its Rx pin. The receiving UART then converts the data back into
parallel form and removes the start bit, parity bit, and stop bits[14]. Finally, the receiving
UART transfers the data packet in parallel to the data bus on the receiving end:[15]

Figure 3.17: Data packet in UART communiction

UART transmitted data is organized into packets. Each packet contains 1 start bit,
5 to 9 data bits (depending on the UART), an optional parity bit, and 1 or 2 stop bits:
START BIT The UART data transmission line is normally held at a high voltage
level when it’s not transmitting data. To start the transfer of data, the transmitting
UART pulls the transmission line from high to low for one clock cycle. When the receiving
UART detects the high to low voltage transition, it begins reading the bits in the data
frame at the frequency of the baud rate.
DATA FRAME The data frame contains the actual data being transferred. It can be
5 bits up to 8 bits long if a parity bit is used. If no parity bit is used, the data frame can
be 9 bits long. In most cases, the data is sent with the least significant bit first.
PARITY Parity describes the evenness or oddness of a number. The parity bit is a way
for the receiving UART to tell if any data has changed during transmission. Bits can

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be changed by electromagnetic radiation, mismatched baud rates, or long distance data

transfers. After the receiving UART reads the data frame, it counts the number of bits
with a value of 1 and checks if the total is an even or odd number[16]. If the parity bit
is a 0 (even parity), the 1 bits in the data frame should total to an even number. If the
parity bit is a 1 (odd parity), the 1 bits in the data frame should total to an odd number.
When the parity bit matches the data, the UART knows that the transmission was free
of errors. But if the parity bit is a 0, and the total is odd; or the parity bit is a 1, and
the total is even, the UART knows that bits in the data frame have changed.[17]
STOP BITS To signal the end of the data packet, the sending UART drives the data
transmission line from a low voltage to a high voltage for at least two bit durations.

3.5.3 Steps involved in UART Transmission

1. The transmitting UART receives data in parallel from the data bus

2. The transmitting UART adds the start bit, parity bit, and the stop bit(s) to the
data frame

3. The entire packet is sent serially from the transmitting UART to the receiving
UART. The receiving UART samples the data line at the pre-configured baud rate

4. The receiving UART discards the start bit, parity bit, and stop bit from the data
frame

5. The receiving UART converts the serial data back into parallel and transfers it to
the data bus on the receiving end

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3.5.4 Simulation Results

Figure 3.18: Block diagram of UART communiction

The block diagram 3.18which is observed through vivado after writing verilog code.

Figure 3.19: Simulation results of UART communiction

Using Vivado, the UART transfer protocol’s outcomes were confirmed, and optimised
code was created for it. It has been noted that SPI transfer is faster than UART trans-
mission. Due to the asynchronous nature of the communication, the data rate of the
UART devices interacting with one another must be identical and Above figure 3.19
shows UART transmission between transmitter and receiver, which is observed through
vivado using verilog code.

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Chapter 4
Reflections

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CHAPTER 4
REFLECTIONS
This chapter talks about the reflections from the internship work undertaken. The
tasks completed reflects on the understanding and working of Verilog Hardware Descrip-
tion Language

4.1 TASK 1: Introduction to verilog

VLSI (Very Large Scale Integration) is the process of integrating or embedding hun-
dreds of thousands of transistors on a single silicon semiconductor microchip, which was
initially designed to support hundreds of thousands of transistor gates on a microchip
but has since exceeded several billion. A finite-state machine (FSM) is a mathematical
model of computation that can be in exactly one of a finite number of states at any given
time and change from one state to another in response to inputs, it is classified into two
types: Mealy state machine and Moore state machine. In a Mealy state machine, the
outputs depend on the current inputs as well as states, whereas in a Moore state machine,
the outputs depend on current states only. Generally, Mealy state machine requires less
states compared to Moore state machine

4.2 TASK 2: Software and Hardware tools that used

in Verilog
Vivado is an integrated design environment (IDE) with system-to-IC level tools built
on a shared scalable data model and a common debug environment. It is a software
suite produced by Xilinx for synthesis and analysis of hardware description language
(HDL) designs and includes electronic system level (ESL) design tools for synthesizing
and verifying C-based algorithmic IP, standards-based packaging of both algorithmic
and RTL IP for reuse, and standards-based IP stitching and systems integration for all
types of system building blocks. A free version of the tool, WebPACK Edition, is also
available. Field-Programmable Gate Array (FPGA) is an integrated circuit that consists
of internal hardware blocks with user-programmable interconnects to customize operation
for a specific application, which can be reprogrammed as needed.

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4.3 TASK 3: Building Basic Circuits using Verilog

Combinational logic circuits are circuits that contain different types of logic gates and
the output is determined from the current combination of inputs. Combinational logic
circuits have different types such as Adder, Subtractor, Decoder, Encoder, Multiplexer,
and De-multiplexer. Full Adder and full Subtractor are used to add or subtract three 1-
bit binary numbers. The multiplexer selects one input from multiple inputs and routes it
to the output, whereas the de-multiplexer performs the reverse operation of a multiplexer
and distributes one input over multiple outputs. The decoder takes n inputs and produces
m (m=2 power n) outputs and performs the opposite operation of an encoder.
Sequential circuits are a special type of circuits that have both inputs and outputs,
the output depends on both the current combination of inputs and previous outputs. The
previous output is considered as the present state, they have memory elements and can
be classified into two types such as Asynchronous and synchronous sequential circuits.
The Asynchronous sequential circuits do not use clock signals and the output depends
on the input, whereas synchronous sequential circuits use clock signals and the output is
determined by the combination of present inputs and the present state.

4.4 TASK 4: Development of SPI Master using ver-

ilog
The main aims is to establish communication between a master device (FPGA) and
any slave device using the Serial Peripheral Interface (SPI) protocol. The project will
test, simulate, and verify the communication in the 4 modes of SPI, which are determined
by the Clock Polarity (CPOL) and Clock Phase (CPHA) settings. The master device
originates the frame for reading and writing and multiple slave devices can be connected
through individual Chip Select lines. The SPI bus uses four logic signals: Serial Clock
(SCLK), Master Out Slave In (MOSI), Master In Slave Out (MISO), and Chip/Slave
Select (CS/SS). Two types of configurations can be used in an SPI bus: Independent
Slave Configuration, where the master has dedicated Slave Select lines for all the slaves,
and Daisy Chain Configuration, where only a single Slave Select line is connected to all
the slaves. And further using a Verilog code can demonstrate the working of the 4 modes
of SPI communication and the required hardware will be implemented on a FPGA board
to verify the communication.

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4.5 TASK 5: Development of UART Communica-

tion using Verilog
UART, or Universal Asynchronous Receiver/Transmitter, is a physical circuit found
in microcontrollers or standalone ICs that is responsible for transmitting and receiving
serial data. It uses only two wires to transmit data between devices.
UARTs work by having two UART devices communicate directly with each other.
The transmitting UART takes parallel data from a controlling device like a CPU, con-
verts it into serial form, and sends it to the receiving UART. The receiving UART then
converts the serial data back into parallel data for the receiving device. The transmitting
UART adds start and stop bits to the data packet, which define the beginning and end
of the packet so the receiving UART knows when to start reading the bits. UART com-
munication is asynchronous, meaning that there is no clock signal used to synchronize
the output of bits from the transmitting UART to the sampling of bits by the receiving
UART. Instead, baud rate is used to ensure that both UARTs are operating at a similar
frequency. The baud rate can only differ by about 10 percent before the timing of the
bits becomes too skewed. Additionally, UARTs can include parity bit for error checking
during transmission.

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 BIBLIOGRAPHY

[1] T. Kam, T. Villa, R. Brayton, and A Sangiovanni-Vincentelli, Synthesis of finite

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[15] A. Osborne, Introductions to Microcomputers: Volume One, Basic Concepts. McGraw-

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