EMBEDDED SYSTEMS: ASSIGNMENT - II: EC - 306

Name Vasu Garg, Roll No. : 2K17/EC/181

Q.1 Compare these ARM Architectures: ARM7TDMI & ARM9TDMI.

A.1 ARM7TDMI and ARM9TDMI are two of the most popular architectures of

the ARM family.

(i) ARM7TDMI
● The ARM7 core has a Von-Neuman style architecture, where both data and

instructions use the same bus.

● The ARM7 core has a three-stage pipeline and executes the architecture

ARM4vT instruction set.

● It is a very popular core and is used in many 32-bit embedded processors.

● It is the first core to include the Thumb instruction set, a fast multiply
instruction. Thus, it supports a 16-bit Thumb instruction set and a 32-bit
ARM instruction set.
(ii) ARM9TDMI
● The memory system in the ARM9 core has a Harvard architecture, which

includes separate data(D) and instructions(I) buses .

● The ARM9 core uses a five-stage pipeline and executes the ARMv5

instruction set, which allows the processor to run at higher clock

frequencies than the ARM7 family.

● The ARM9TDMI supports both the 32‑bit ARM and 16‑bit Thumb instruction
sets, allowing the user to trade-off between high performance and high
code density. The ARM9TDMI supports the ARM debug architecture and
 includes logic to assist in both hardware and software debugging. The
ARM9TDMI also includes full coprocessor support.

Q.2 List down and explain the various enhancements in ARM9E.

A.2 The ARM9E is an ARM9 with DSP-oriented enhancements. It offers

significantly better DSP performance than the ARM7 and ARM9.

Its enhancements include:

● New 32x16 and 16x16 multiply instructions – SMLAxy, SMLAWy, SMLALxy,

SMULxy, SMULWy.

○ Allow independent access to 16-bit halves of registers.

○ Give efficient use of 32-bit bandwidth for packed 16-bit operands.
● Zero overhead fractional saturating arithmetic
○ QADD, QSUB, QDADD, QDSUB
● Count leading zeros instruction
○ CLZ for faster normalization and division
● It includes signal processing extensions to enhance 16-bit fixed-point
performance using a single-cycle 32 x 16 multiply-accumulate ( MAC) unit,
and implement the 16-bit Thumb instruction set.
○ The single-cycle 32x16 multiplier array speeds up all ARM9E multiply
instruction
● The 200 MHz ARM9E is about 70% faster than the 200 MHz ARM9 on

16-bit DSP tasks.

● The ARM9E DSP enhancements are fairly modest compared to those found
in many other DSP-enhanced general-purpose processors.
● With its improved DSP performance, the ARM9E eliminates the need for a

separate DSP in some of the applications.

Q.3 Explain with example (+ diagram) a simple ARM system. A.3

● The ARM7 processor is based on the Von Neuman model with a single bus

for data and instructions.

● ARM uses Advanced Microcontroller Bus Architecture (AMBA). The AMBA

includes two system buses: the AMBA High-Speed Bus(AHB) or the
Advanced System Bus(ASB), and the Advanced Peripheral Bus(APB).
● The ARM processor consists of Arithmetic Logic Unit(32-bit), One Booth
Multiplier, One Barrel Shifter, One Control Unit, Register file of 31 registers
of 32 bits each.
● In addition to this the ARM also consists of a Program Status Register,
Instruction Register and Priority Encoder.

Q.4 Explain ARMv5TEJ.

A.4 ARMv5TEJ is an advanced RISC based ARM architecture with the Trivial

Jazelle extension implemented.

It is a combined superset of the previous ARM architecture versions, which
include ARMv4T, ARMv5T, ARMv5TE.
Below are the general and the special features of this architecture.
The general features of the ARMv5TEJ include:
 (a) Load-Store architecture, where data-processing operations only operate on
register contents, not directly on memory contents.
(b) 31 general-purpose 32-bit registers, out of which 16 are visible at any one
time. Out of these 16 registers, 3 have special roles, which are STACK
POINTER, PROGRAM COUNTER, and LINK REGISTER.
(c) ARM supports 7 exceptions and a privileged processing mode for each. The
seven types of exception are:
• reset
• attempted execution of an Undefined instruction
• software interrupt (SWI) instructions, used to make a call to the OS.
• Prefetch Abort, an instruction fetches memory abort
• Data Abort, a data access memory abort
• IRQ, normal interrupt
• FIQ, fast interrupt.
(d)All processor state other than the general-purpose register contents is held
in status registers.
(e) It has a 32-bit ARM and 16-bit Thumb instruction set.
The special features of the ARMv5TEJ are:
(a) Extra instructions added for changing state between ARM and Thumb
instructions.
(b)Enhanced multiplication instructions.
(c) Extra DSP-type instructions.
(d)Faster multiply accumulates.
(e) Saturation instructions
(f) The Jazelle Extension enables architectural support for hardware
acceleration of opcode execution by Java Virtual Machines (JVMs).

Q.5 Elaborate on ARMv6 architecture and how it is different from other ARM
families.
A.5 ARMv6 is an ARM architecture with very advanced and astonishing
capabilities. Along with the traditional ARM architectural features from previous
versions, it has support for Advanced DSP(Digital Signal Processing) and
SIMD(Single Instruction Multiple Data) support.
Its unique features include the following:
1. 8-bit SIMD and 16-bit SIMD operations can be performed using the

improved instruction set of the ARMv6.

a. The ARM includes this “lightweight” SIMD approach that virtually

costs nothing.
b. The new instructions improve the processing throughput of some
algorithms by up to two times for the 16-bit data or four times for
the 8-bit data.
2. The ARMv6 architecture includes a new set of packing instructions that are
used to construct the new 32-bit packed data from the pairs of 16-bit
values in the different source registers.
a. These instructions are particularly useful for pairing 16-bit values so
that the 16-bit SIMD instructions can be used.
3. Complex Arithmetic Support
a. It is commonly used in communication signal processing, and in
particular in the implementation of transform algorithms such as the
Fast Fourier Transform.
b. ARMv6 adds new multiply instructions to accelerate the complex
multiplications.
4. Sum of Absolute differences instructions
a. The 2 new instructions USAD8 and USADA8 are the most application-
specific instructions within ARMv6.
b. They are used to compute the absolute difference between 8-bit
values and are particularly useful in motion video compression
algorithms, such as MPEG.
 c. These 2 special instructions allow tremendous performance
advantage for this application, as compared to a similar ARMv5TE
implementation.
5. Dual 16-bit multiply instructions
a. Implementations of ARMv6 have a dual 16x16 multiply capability,
which is comparable with many high-end dedicated DSP devices.
6. Cryptographic multiplication extensions
7. Most Significant word multiplies
8. Mixed-Endianness Support
9. Exception processing
10.Multiprocessing Synchronisation primitives

Q.6 Explain Intel’s ARM Derivative with the help of a diagram.

A.6 Intel’s ARM derivatives are Intel XScale and StrongArm.

● XScale is a microarchitecture for central processing units initially designed

by Intel implementing the ARM architecture (version 5) instruction set.

XScale comprises several distinct families: IXP, IXC, IOP, PXA, and CE.

● All the generations of XScale are 32-bit ARMv5TE processors.

 Fig. INTEL X-SCALE ARCHITECTURE.

● The Intel XScale core implements the integer instruction set architecture of
ARMv5 but does not provide hardware support of the floating-point
instructions. The Intel XScale core provides the Thumb instruction set
(ARMv5T) and the ARM V5E DSP extensions.
● The Intel XScale core comes with either a 16K or 32K byte instruction cache.
The instruction cache is 32-way set associative and has a line size of 32
bytes. All requests that “miss” the instruction cache generate a 32-byte
read request to external memory.
● The Intel XScale core supports software debugging through two instruction
address breakpoint registers, one data-address breakpoint register, one
data-address/mask breakpoint register, and a trace buffer.
● The Intel XScale core made a few extensions to the ARM Version 5TE
architecture to meet the needs of various markets and design
requirements.
The following is a list of the extensions:
○ A DSP coprocessor (CP0) has been added that contains a 40-bit
accumulator and eight new instructions.
○ New page attributes were added to the page table descriptors. The C
and B page attribute encoding was extended by one more bit to
allow for more encodings: write allocate and mini-data cache.
○ Additional functionality has been added to coprocessor 15.
Coprocessor 14 was also created.
○ Enhancements were made to the Event Architecture, which includes
instruction cache and data cache parity error exceptions, breakpoint
events, and imprecise external data aborts.