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ruthvik_BRN49_Verilog-coding-test

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9 views5 pages

ruthvik_BRN49_Verilog-coding-test

Uploaded by

ruthvikvyshnav
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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1.

Write an RTL code and a task-based test for an 8-bit BCD counter RUTHVIK BJ, BRN 49

RTL:

module bcd_counter (
input wire clk,
input wire reset,
output reg [7:0] bcd
);

reg [3:0] units;


reg [3:0] tens;

// Counter update logic


always @(posedge clk or posedge reset)
begin
if (reset) begin
units <= 4'b0000;
tens <= 4'b0000;
end
else
begin
if (units == 4'b1001)
begin
units <= 4'b0000;
if (tens == 4'b1001) begin
tens <= 4'b0000;
end
else
tens <= tens + 1;
end
else
units <= units + 1;
end
end

always @* begin
bcd = {tens, units};
end

endmodule
test bench:

module tb_task_bcd_counter;

reg clk;
reg reset;
wire [7:0] bcd;

bcd_counter uut (
.clk(clk),
.reset(reset),
.bcd(bcd)
);

always #5 clk = ~clk;

initial begin
clk = 0;
reset = 0;
apply_reset();

#100; check_bcd_counter();
#200;
$stop;
end

task apply_reset;
begin
$display("Time %0t: Applying reset...", $time);
reset = 1;
#10;
reset = 0;
$display("Time %0t: Reset deasserted. Counter should be at 0.", $time);
end
endtask

task check_bcd_counter;
integer i;
begin
$display("Time %0t: Starting BCD counter check...", $time);

for (i = 0; i < 100; i = i + 1) begin


#10;
$display("Time %0t: BCD Counter value: %b (Hex: %h)", $time, bcd, bcd);
end
$display("Time %0t: BCD counter check completed.", $time);
end
endtask

endmodule

output:

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