DEPARTMENT OF ELECTRICAL AND ELECTRONICS

ENGINEERING

ACADEMIC YEAR 2023 - 2024 EVEN SEMESTER

EE3022 VLSI DESIGN LABORATORY

III YEAR / V SEMESTER

PREPARED BY
R.HINDUJA
AP / ECE
EE3022 VLSI DESIGN LT P C
2023

1. Laboratory exercise : Use any FPGA Board /IDE/open source package/ platform to give

hands on training on CMOS design/ reconfigurable processor based applications.

a) CMOS logic circuit simulation using any open source software package

b) Experiments : structural and behavioural modeling based Verilog HDL programs

c) Experiment: Combinational and sequential Digital logic implementation with FPGA.

d) Implementation of carry look ahead adder with FPGA

e) Implementation of ALU with FPGA

2. Assignment : Low Power VLSI.

3. FPGA based Mini project.

30 PERIODS
Expt. No: 1 (a) DESIGN AND SIMULATE A CMOS LOGIC CIRCUIT
Date :
AIM: To design and analyze a CMOS logic circuit using dsch2.6.
APPARATUS/TOOLS REQUIRED:
 PC with Windows XP.
 Microwind Dsch2
PROCEDURE:
Steps to design gates:
 Open DSch2.6 File-New.
 Draw the MOS device input buttons and output LED from symbol pallete and draw the inverter
schematic.
 Run the simulation
 Give the Input to the button.
 Click the chromogram to view the graph.
AND GATE:
Circuit Diagram:

TIMING DIAGRAM:
VERIOLG CODINGS:

LAYOUT:

VOLTAGE VS TIME:
OR GATE:

Circuit Diagram:

TIMING DIAGRAM:

VERILOG CODINGS:
LAYOUT:

VOLTAGE VS TIME:

NAND GATE:
TIMING DIAGRAM:

VERILOG CODINGS:

LAYOUT:
VOLTAGE VS TIME:

NOR GATE:
CIRCUIT DIAGRAM:

TIMING DIAGRAM:
VERILOG CODINGS:

LAYOUT:
VOLTAGE VS TIME:

EXOR:
CIRCUIT DIAGRAM:

TIMING DIAGRAM:
VERILOG CODINGS:

LAYOUT:

VOLTAGE VS TIME:

RESULT: Thus the design and simulation of CMOS logic circuit using Dsch2.6 was executed and
implemented successfully.
Expt. No: 1 (b) DESIGN AND SIMULATE A CMOS INVERTER USING STRUCTURAL
AND BEHAVIORAL MODEL
Date :
AIM: To design and implement a CMOS inverter using structural and behavioral model using Verilog HDL
and simulate it using Xilinx project navigator.
APPARATUS/TOOLS REQUIRED:
 PC with Windows XP.
 XILINX software.
 FPGA kit.
 JTAG cable.
PROCEDURE:
1. Start the Xilinx ISE by using Start Program files Xilinx ISE project navigator
2. Click FileNew Project
3. Enter the Project Name and select the location then click next
4. Select the Device and other category and click next twice and finish.
5. Click on the symbol of FPGA device and then right clickclick on new source.
6. Select the Verilog Module and give the file name click next and define portsclick next and
finish.
7. Writing the Verilog Code in Verilog Editor.
8. Run the Check syntax Process windowsynthesizedouble click check syntax. If any
errors found then remove the errors with proper syntax & coding.
9. Click on the symbol of FPGA device and then right click click on new source.
10. Select the Test Bench Waveform and give the file name select entity click next and finish.
11. Select the desired parameters for simulating your design. In this case combinational circuit and
simulation time click finish.
12. Assign all input signal using just click on graph and save file.
13. From the source process window. Click Behavioral simulation from drop-down menu
14. Select the test bench file (.tbw) and click process buttondouble click the Simulation Behavioral
Model
15. Verify your design in wave window by seeing behavior of output signal with respect to input signal.

PROGRAM
Structural modeling
module not_gate(c,a);
input a;
output c;
not (c,a);
endmodule
Behavioral Modeling
module not_beh(c,a);
input a;
output c;
reg c;
always@(a)
begin
if (a==0)
c=1;
else
c=0;
end
endmodule

TESTBENCH CODINGS:
module inverter_tb;
// Inputs
 reg a;
// Outputs
wire Yinv;
// Instantiate the Unit Under Test (UUT)
inverter uut (
.a(a),
.Yinv(Yinv)
);
initial begin
// Initialize Inputs
a=0;#100;
a=1;#100;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule

RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

SIMULATION OUTPUT:

DESIGN UTILIZATION SUMMARY:

RESULT: Thus the inverter was designed using Verilog HDL and implemented in FPGA
Expt. No: 1 (c)i) Design of basic combinational circuits using HDL. Simulate it using Xilinx Software
and implement by Xilinx FPGA
Date :
AIM:
To design and implement basic combinational circuits using Verilog HDL and simulate it using Xilinx project
navigator.
APPARATUS/TOOLS REQUIRED:
 PC with Windows XP.
 XILINX software.
 FPGA kit.
 JTAG cable.
THEORY:
Digital systems are said to be constructed by using logic gates. These gates are the AND, OR, NOT, NAND,
NOR, EXOR and EXNOR gates. The basic operations are described below with the aid of truth tables.

AND gate:
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is
used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB

OR gate:
The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A
plus (+) is used to show the OR operation.

NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also
known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also
shown as A', or A with a bar over the top, as shown at the outputs. The diagrams below show two ways
that the NAND logic gate can be configured to produce a NOT gate. It can also be done using NOR logic
gates in the same way.
EXOR gate:
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two inputs
are high. An encircled plus sign () is used to show the EOR operation.

PROCEDURE:
16. Start the Xilinx ISE by using Start Program files Xilinx ISE project navigator
17. Click FileNew Project
18. Enter the Project Name and select the location then click next
19. Select the Device and other category and click next twice and finish.
20. Click on the symbol of FPGA device and then right clickclick on new source.
21. Select the Verilog Module and give the file name click next and define portsclick next and finish.
22. Writing the Verilog Code in Verilog Editor.
23. Run the Check syntax Process windowsynthesizedouble click checksyntax. If any
errors found then remove the errors with proper syntax & coding.
24. Click on the symbol of FPGA device and then right click click on new source.
25. Select the Test Bench Waveform and give the file name select entity click next and finish.
26. Select the desired parameters for simulating your design. In this case combinational circuit and
simulation time click finish.
27. Assign all input signal using just click on graph and save file.
28. From the source process window. Click Behavioral simulation from drop-down menu
29. Select the test bench file (.tbw) and click process buttondouble click the Simulation Behavioral
Model
30. Verify your design in wave window by seeing behavior of output signal with respect to input signal.

PROGRAM:
module gates(a,b,Yand, Ynand, Yor, Ynor, Ynot, Yxor,Yxnor);
input a,b;
output Yand, Ynand, Yor, Ynor, Ynot, Yxor,Yxnor;
assign Yand = a & b;
assign Ynand = ~(a & b);
assign Yor = a | b;
assign Ynor = ~(a | b);
assign Ynot =~ a ;
assign Yxor = a ^ b;
assign Yxnor = ~(a ^ b);
endmodule

TESTBENCH CODINGS:
module gates_tb;
// Inputs
reg a;
reg b;
// Outputs
wire Yand;
wire Ynand;
 wire Yor;
wire Ynor;
wire Ynot;
wire Yxor;
wire Yxnor;
// Instantiate the Unit Under Test (UUT)
gates uut (
.a(a),
.b(b),
.Yand(Yand),
.Ynand(Ynand),
.Yor(Yor),
.Ynor(Ynor),
.Ynot(Ynot),
.Yxor(Yxor),
.Yxnor(Yxnor)
);
initial begin
// Initialize Inputs
a = 0;b = 0; #100;
a = 0;b = 1; #100;
a = 1;b = 0; #100;
a = 1;b = 1; #100;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule
SIMULATION OUTPUT:
RTL SCHEMATIC: TECHNOLOGY SCHEMATIC:

DEVICE UTILIZATION SUMMARY:

RESULT: Thus the design of basic combinational circuits using Verilog HDL was executed and implemented
successfully.
Expt. No: 1(c) ii) Design of basic sequential (Flip-flops) circuits using HDL. Simulate it using Xilinx
Software and implement by Xilinx FPGA
Date :
AIM:
To design and implement basic sequential (Flip-flops) circuits using Verilog HDL and simulate it using Xilinx
project navigator.
APPARATUS/TOOLS REQUIRED:
 PC with Windows XP.
 XILINX software.
 FPGA kit.
 JTAG cable.
THEORY:
 In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to
store state information. A flip-flop is a bistable multivibrator. The circuit can be made to
change state by signals applied to one or more control inputs and will have one or two
outputs. It is the basic storage element in sequential logic. Flip-flops and latches are
fundamental building blocks of digital electronics systems used in computers,
communications, and many other types of systems.
 Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary
digit) of data; one of its two states represents a "one" and the other represents a "zero". Such
data storage can be used for storage of state, and such a circuit is described as sequential
logic.
D FLIP-FLOP: TRUTH TABLE:

SR FLIPFLOP:
TRUTH TABLE:

JK FLIPFLOP:

TRUTH TABLE:
T-FLIPFLOP:

TRUTH TABLE:

D-FLIPFLOP:
PROGRAM:
module DFF(d,clk,rst,q,qb);
input d,clk,rst;
output q,qb;
reg q;
always @ (posedge clk)
begin
if(rst)
q<=1'b0;
else
q<=d;
end
assign qb=~q;
endmodule

TESTBENCH CODINGS:
module DFF_TB;
// Inputs
reg d;
reg clk;
reg rst;
// Outputs
 wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
DFF uut (
.d(d),
.clk(clk),
.rst(rst),
.q(q),
.qb(qb)
);
initial
begin
clk=0; forever #5 clk=~clk;
end
initial begin
// Initialize Inputs
rst=1;
#10 rst=0;
#70 rst=1;
#10 rst=0;
#70 rst=1;
end
initial
begin
d=0;
#15 d=1;
#15 d=0;
#15 d=1;
#30 d=0;
end
endmodule

RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:
SIMULATION OUTPUT:

DESIGN SUMMARY:

SR FLIP FLOP:
PROGRAM:
module SRFF(s,r,clk,rst,q,qb);
input s,r,clk,rst;
output q,qb;
wire s,r,clk,rst,qb;
reg q;
always @ (posedge clk)
begin
if(rst)
q<=1'b0;
else
if (s==1'b0 && r==1'b0)
q<=q;
else if (s==1'b0 && r==1'b1)
q<=1'b0;
else if (s==1'b1 && r==1'b0)
q<=1'b1;
else if (s==1'b1 && r==1'b1)
q<=1'bx;
end
assign qb=~q;
endmodule

TESTBENCH CODINGS:
module SRFF_TB;
// Inputs
reg s;
reg r;
reg clk;
reg rst;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
SRFF uut (
.s(s),
.r(r),
.clk(clk),
.rst(rst),
.q(q),
.qb(qb)
);
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
rst=1;
#10 rst=0;
#80 rst=1;
#10 rst=0;
end
initial
begin
s=0; r=0;
#15 s=0; r=1;
#15 s=1; r=0;
#15 s=1; r=1;
#15 s=0; r=0;
end
endmodule
RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

SIMULATION OUTPUT:
DESIGN SUMMARY:

JK FLIPFLOP:
PROGRAM:
module JKFF (j,k,clk,rst,q,qb);
input j,k,clk,rst;
output q,qb;
wire j,k,clk,rst,qb;
reg q;
always @ (posedge clk)
begin
if(rst)
q<=1'b0;
else if (j==0 && k==0)
q<=q;
else if (j==0 && k==1)
q<=1'b0;
else if (j==1 &&k==0)
q<=1'b1;
else if (j==1 &&k==1)
q<=~q;
end
assign qb=~q;
endmodule

TESTBENCH CODINGS:
module JKFF_TB;
// Inputs
reg j;
reg k;
reg clk;
reg rst;
// Outputs
wire q;
wire qb;
// Instantiate the Unit Under Test (UUT)
JKFF uut (
.j(j),
.k(k),
.clk(clk),
.rst(rst),
 .q(q),
.qb(qb)
);
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
rst=1;
#15 rst=0;
#80 rst=1;
#15 rst=0;
end
initial
begin
j=0; k=0;
#15 j=0; k=1;
#15 j=1; k=0;
#15 j=1; k=1;
#15 j=0; k=0;
end
endmodule

RTL SCHEMATIC:
TECHNOLOGY SCHEMATIC:

SIMULATION OUTPUT:

DESIGN SUMMARY:

T FLIPFLOP:
PROGRAM:
module TFF (T,clk,rst,q,qb);
input T,clk,rst;
output q,qb;
wire T,clk,rst,qb;
reg tq;
always @ (posedge clk)
begin
if(rst)
tq<=1'b0;
else
begin
if(T==1'b1)
tq<=~tq;
end
end
assign q=~tq;
assign qb=~q;
endmodule

TESTBENCH CODINGS:
module TFF_TB;

// Inputs
reg T;
reg clk;
reg rst;

// Outputs
wire q;
wire qb;

// Instantiate the Unit Under Test (UUT)

TFF uut (
.T(T),
.clk(clk),
.rst(rst),
.q(q),
.qb(qb)
);

initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
rst=1;
#10 rst=0;
#80 rst=1;
#10 rst=0;
end
initial
begin
T=0;
#15 T=1;
#15 T=0;
#15 T=1;
#15 T=0;
end
endmodule

RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:
SIMULATION OUTPUT:

DESIGN SUMMARY:

RESULT: Thus the design of basic sequential (Flip-flops) circuits using Verilog HDL was executed and
implemented successfully.
Expt. No: 1 (d) DESIGNS AND IMPLEMENTATION OF CARRY LOOK AHEAD ADDER
Date :
AIM:
To design and implement the carry look ahead adder using Verilog and simulate it using Xilinx
project navigator.
APPARATUS/TOOLS REQUIRED:
 PC with Windows XP.
 XILINX software.
 FPGA kit.
 JTAG cable.
PROCEDURE:
1. Start the Xilinx ISE by using Start Program files Xilinx ISE project navigator
2. Click FileNew Project
3. Enter the Project Name and select the location then click next
4. Select the Device and other category and click next twice and finish.
5. Click on the symbol of FPGA device and then right clickclick on new source.
6. Select the Verilog Module and give the file name click next and define portsclick next and finish.
7. Writing the Verilog Code in Verilog Editor.
8. Run the Check syntax Process windowsynthesizedouble click check syntax. If any errors found
then remove the errors with proper syntax & coding.
9. Click on the symbol of FPGA device and then right click click on new source.
10. Select the Test Bench Waveform and give the file name select entity click next and finish.
11. Select the desired parameters for simulating your design. In this case combinational circuit and simulation
time click finish.
12. Assign all input signal using just click on graph and save file.
13. From the source process window. Click Behavioral simulation from drop-down menu
14. Select the test bench file (.tbw) and click process buttondouble click the Simulation Behavioral Model
15. Verify your design in wave window by seeing behavior of output signal with respect to input signal.

Inputs –
A3 A2 A1 A0
B3 B2 B1 B0
And Cin
Output
Sum = S3 S2 S1 S0
And Cout

Sum Sj = Pj ^ Cj = Aj ^ Bj ^ Cj
C0 = Cin
C1 = G0 + (P0·C0)
= A0·B0 + (A0^B0)·C0
C2 = G1 + (P1·C1)
= A1·B1 + (A1^B1)·(A0·B0 + (A0^B0)·C0)

C3 = G2 + (P2·C2)
= A2·B2 + (A2^B2)·C2
= A2·B2 + (A2^B2)·(A1.B1 + (A1^B1)·(A0B0 + (A0^B0)·C0))
C4 = G3 + (P3·C3)
= A3·B3 + (A3^B3)·C3
= A3·B3 + (A3^B3)·(A2.B2 + (A2^B2)·(A1.B1 + (A1^B1)·(A0B0 + (A0^B0)·C0)))
Cout = C4;

PROGRAM
module CarryLookAheadAdder(
input [3:0]A, B,
input Cin,
output [3:0] S,
output Cout
);
wire [3:0] Ci; // Carry intermediate for intermediate computation

assign Ci[0] = Cin;

assign Ci[1] = (A[0] & B[0]) | ((A[0]^B[0]) & Ci[0]);
assign Ci[2] = (A[1] & B[1]) | ((A[1]^B[1]) & ((A[0] & B[0]) | ((A[0]^B[0]) & Ci[0])));
assign Ci[3] = (A[2] & B[2]) | ((A[2]^B[2]) & ((A[1] & B[1]) | ((A[1]^B[1]) & ((A[0] & B[0]) |
((A[0]^B[0]) & Ci[0])))));
assign Cout = (A[3] & B[3]) | ((A[3]^B[3]) & ((A[2] & B[2]) | ((A[2]^B[2]) & ((A[1] & B[1]) |
((A[1]^B[1]) & ((A[0] & B[0]) | ((A[0]^B[0]) & Ci[0])))))));

assign S = A^B^Ci;
endmodule

RESULT:

Thus the carry look ahead adder using verilog HDL was designed and implemented in FPGA.
Expt. No: 1 (e) DESIGN AND IMPLEMENTATION OF ALU

AIM:
To design and implement ALU using Verilog HDL and simulate it using Xilinx project navigator.
APPARATUS/TOOLS REQUIRED:
 PC with Windows XP.
 XILINX software.
 FPGA kit.
 JTAG cable.
PROCEDURE:
1. Start the Xilinx ISE by using Start Program files Xilinx ISE project navigator
2. Click FileNew Project
3. Enter the Project Name and select the location then click next
4. Select the Device and other category and click next twice and finish.
5. Click on the symbol of FPGA device and then right clickclick on new source.
6. Select the Verilog Module and give the file name click next and define portsclick next and finish.
7. Writing the Verilog Code in Verilog Editor.
8. Run the Check syntax Process windowsynthesizedouble click check syntax. If any errors found
then remove the errors with proper syntax & coding.
9. Click on the symbol of FPGA device and then right click click on new source.
10. Select the Test Bench Waveform and give the file name select entity click next and finish.
11. Select the desired parameters for simulating your design. In this case combinational circuit and simulation
time click finish.
12. Assign all input signal using just click on graph and save file.
13. From the source process window. Click Behavioral simulation from drop-down menu
14. Select the test bench file (.tbw) and click process buttondouble click the Simulation Behavioral Model
15. Verify your design in wave window by seeing behavior of output signal with respect to input signal.
PROGRAM:
module alu (op,a,b,opcode);
output reg [13:0] op; //output of alu
input [7:0] a,b; //inputs to alu
input [3:0] opcode; //control signal for different operation
always @(*)
begin
case (opcode)
4'b0000 : begin op = a + b; $display("Addition operation"); end
4'b0001 : begin op = a - b; $display("Subtraction operation"); end
4'b0010 : begin op = a * b; $display("Multiplication operation"); end
4'b0011 : begin op = a & b; $display("Bit-wise AND operation"); end
4'b0100 : begin op = a | b; $display("Bit-wise OR operation"); end
4'b0101 : begin op = a && b; $display("Logical AND operation"); end
4'b0110 : begin op = a || b; $display("Logical OR operation"); end
4'b0111 : begin op = a ^ b; $display("Bit-wise XOR operation"); end
4'b1000 : begin op = ~ a; $display("Bit-wise Invert operation"); end
4'b1001 : begin op = ! a; $display("Logical Invert operation"); end
4'b1010 : begin op = a >> 1; $display("Right Shift operation"); end
4'b1011 : begin op = a << 1 ; $display("Left Shift operation"); end
4'b1100 : begin op = a + 1; $display("Increment operation"); end
4'b1101 : begin op = a - 1; $display("Decrement operation"); end
default:op = 8'bXXXXXXXX;
endcase
end
endmodule
TESTBENCH CODING:
module ALUTB;
// Inputs
reg [7:0] a;
reg [7:0] b;
reg [3:0] opcode;
// Outputs
wire [13:0] op;
// Instantiate the Unit Under Test (UUT)
alu uut (
.op(op),
.a(a),
.b(b),
.opcode(opcode)
);
initial begin
// Initialize Inputs
a = 10;b = 2;opcode = 4'b0000;#100;
a = 10;b = 2;opcode = 4'b0001;#100;
a = 10;b = 2;opcode = 4'b0010;#100;
a = 10;b = 2;opcode = 4'b0011;#100;
a = 10;b = 2;opcode = 4'b0100;#100;
a = 10;b = 2;opcode = 4'b0101;#100;
a = 10;b = 2;opcode = 4'b0110;#100;
a = 10;b = 2;opcode = 4'b0111;#100;
a = 10;opcode = 4'b1000;#100;
a = 10;opcode = 4'b1001;#100;
a = 10;opcode = 4'b1010;#100;
a = 10;opcode = 4'b1011;#100;
a = 2;opcode =4'b1100;#100;
a = 3;opcode =4'b1101;#100;
// Add stimulus here
end
endmodule

SIMULATION OUTPUT:
RTL SCHEMATIC:

DESIGN SUMMARY:

RESULT: Thus the ALU was designed using verilog HDL and implemented in FPGA.