Types of Dram Theory
Types of Dram Theory
Types of DRAM
Slide 2
Introduction
• In DRAM, several capacitors are used for storing every bit of data
Slide 3
Types of DRAM
DRAMs can be classified as follows.
• FPM
• EDO
• BDO
• SDRAM
• ADRAM
• RDRAM
• FPM DRAM stands for “fast page mode DRAM”, and this DRAM has fast speed to other
conventional drams
• FPM DRAM mostly used in the personal computers, but today it is not useful because it
was only capable to support memory bus speed rate up to 66 MHz
• EDO DRAM stands for “Extended Data Out DRAM”, and it had great performance than
FPM DRAM but its speed was same FPM DRAM like as 66 MHz
• In EDO, a new data cycle is started while the data output of the previous cycle is still
active
• This process of cycle overlapping, called pipelining, increases processing speed by about
10 nanoseconds per cycle, increasing computer performance
Slide 6
• It is also called hyper-page-mode DRAMs, represent a small design change in the output
buffer relative to a standard fast page mode DRAM
Slide 7
BEDO DRAM
• BEDO DRAM stands for “Burst EDO DRAM”, and it provided the best performance
compare to EDO DRAM
• The “burst” refers to the fact that all read and write cycles occur in bursts of four,
automatically sequenced by the memory chip
• To accomplish that, a special pipeline stage and a two-bit counter are added.
• The advantage of the BEDO DRAM type is that it could process four memory addresses in one burst saving three
clock cycles when compared to EDO memory.
Slide 8
• BEDO DRAM also added a pipelined to enable the page-access cycle to be divided into
two components:
• the first component accessed the data from the memory array to the output stage
• the second component drove the data bus from this latch at the appropriate logic level
• Since the data was already in the output buffer, a faster access time is achieved
• Asynchronous DRAM is basic form of the DRAM, and it controls the timing of all
memory devices with asynchronous nature, and memory controller circuit arises the
useful control signals to control timing
Slide 10 RDRAM
• RDRAM stands for “Rambus DRAM”, and it was designed by Rambus Inc; especially
for graphic card
• Now these days, modern RDRAM has higher data transfer rate to CPU memory bus
because it includes several new speedup techniques such as synchronous memory
interface system, caching enabled DRAM chips and faster signal timing. RDRAM consist
8 or 9 bits width data bus.
Slide 11 CDRAM
• CDRAM stands for “Cache DRAM”, and it is designed specially with enabling on-chip
cache memory
• This device integrates a DRAM and a L2 (level two) SRAM cache memory on the same
chip
• The transfer between the DRAM and the SRAM is performed in one clock cycle through
a buffer
Slide 12 SDRAM
• SDRAM stands for “Synchronous Dynamic Access Memory”, and it can access any
element of data within 25 to 10 ns
• Synchronous DRAM is a type of DRAM that is much faster than previous, conventional forms of RAM and
DRAM. It operates in a synchronous mode, synchronizing with the bus within the CPU.
• It has different versions such as SDR DRAM, DDR DRAM, QDR DRAM etc.
• SDR SDRAM stands for “Single Data Rate synchronous DRAM”, and it can allow only
one instruction and transfer one frame of data’s word on per clock cycle
• These types of chips are designed with several data buses forms such as 4, 8, or 16 bits,
and they are assembled into 168 pin DIMM package module
Slide 14
• Exchanges data with the processor synchronized to an external clock signal and running
at the full speed of the processor/memory bus without imposing wait states
• With synchronous access the DRAM moves data in and out under control of the system
clock
Slide 15 DDR SDRAM
• DDR SDRAM stands for “Double Data Rate SDRAM”, and it provides the more
bandwidth to all users
• Double Data-Rate Synchronous DRAM-Double Data Rate uses both rising and falling edge of the clock.
• It is capable to accept the same commands at the once per cycle, and it can transfer
double words of data with one clock cycle at a same time
Slide 16
• The purpose of the DDR DRAM is to read data of an SDRAM at two times the frequency
clock
• Because device delivers data on both edges of the clock, it doubles effective bandwidth at
a given frequency
• The purpose of the DDR DRAM is to read data of an SDRAM at two times the frequency
clock
• Because device delivers data on both edges of the clock, it doubles effective bandwidth at
a given frequency
• DDR1, DDR2, DDR3, DDR 4 increase in number of stages of the pipelining, increase in
latency, increase in overall speed
1. the data transfer is synchronized to both the rising and falling edge of the clock, rather
than just the rising edge
2. DDR uses higher clock rate on the bus to increase the transfer rate
• This memory package consist the eight or nine RAM chip, where eight is used in MAC
and nine in the personal computer but 9th chip is reserved to parity checking
• SIMM used the 32 bit bus width, and it was available in 30 or 72 pin modules
• Now these days, DIMM works on the latest technology like as fourth generation double
data rate (DDR4) SDRAM, and it contains the 288 pin connectors
• This memory package is similar as a DIMM but it is known as RIMM because of their
manufacture companies slot needed
Slide 22
Summary
In this module we have studied various types of Dram and their features.
For example fpm, bedo, rdram, synchronous and asynchronous dram and their applications.
We have also studied their further classification sdr dram on the basis of functionality