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Placement Stages

Placement_stages and fixes

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cottilard1995
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24 views27 pages

Placement Stages

Placement_stages and fixes

Uploaded by

cottilard1995
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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PLACEMENT

STAGES
PLACEMENT

• Placement is the process of placing the standard cells inside the core
boundary in an optimal location. The tool tries to place the standard cell
in such a way that the design should have minimal congestions and the
best timing. Every PnR tool provides various commands/switches so that
users can optimize the design in a better way in terms of timing,
congestion, area, and power as per their requirements.
• Netlist
• SDC

Input • Library files (.lib ,lef)


• Technology file

Files •
•
Mcmm file
Scan def file
• TLU+ file
• Floorplan C Power plan (DEF)
Pre-Placement Stage

Checks :
➢ Perform checks on port placement
➢ Perform checks on end-cap cells and tap-cells placement
➢ Perform checks on macro-placement and use blockages at required places
➢ Set local density limit (G-cell density)
➢ Perform Power planning check
• Check_pg_drc
• Check_pg_connectivity
• Check_pg_missing_vias
Pre-placement stage

Initial placement / global placemnet / coarse


placement
Legalization

Placement HFNS (High Fanout Net Synthesis)

stages Iteration for timing , congestion , DRVs and power


optimization
Multibit flop conversion

Timing,Power s Area optimization iterations

Scan-chain reorder
Initial Placement /Coarse Placement

During the coarse placement, The placed cells don’t fall on


the tool determines an the placement grid and might
approximate location for each overlap each other. Large cells
cell according to the timing, like RAM and IP blocks act as
congestion and multi-voltage placement blockages for
constraints. standard cells
Initial Placement /Coarse Placement
Legalization

• During legalization, the tool moves the cells to legal locations on the
placement grid and eliminate any overlap between cells.
• These small changes to cell location cause the lengths of the wire
connections to change, possibly causing new timing violations.
• Such violations can often be fixed by incremental optimization, for
example: by resizing the driving cells.
Legalization
Tie Cell insertion
Scan-chain reorder

➢ If block contains scan chains by default Placement and CTS tools perform
DFT optimization.
➢ During initial placement, the tool focuses on the QOR for the function nets
by ignoring the scan chains. After initial placement, the tool further
improves the QOR by repartitioning and reordering the scan chains based
on the initial placement.
➢ Scan chains reordering reduces wire length so timing will improve.
➢ Scan chains reordering minimize congestions and improves routability
Scan-chain reorder
High Fanout Net Synthesis

• The process of buffering the high fan-out to reduce the fanout load is
called as High fanout net Synthesis. because if design has too many loads
then it affects delay and transition time.
• High fanout nets are mainly reset, preset, scan enable etc. these nets are
not synthesized in the synthesis stage, also make sure you set an
appropriate fan-out limit for your library
High Fanout Net Synthesis
Multibit flop conversion
Placement Optimization stage:
• In this stage tool tries to optimize placement to reduce
congestion , improve timing and to fix timing DRVs .
• Tool optimizes timing DRVs and setup violation by
different methods like
• Cell sizing
• Vt swapping
• Buffering
• Cloning
• Pin-swapping
• Logical restructuring
Stage by stage through
ICC2 tool
Initial_drc
End of initial_drc
Initial_opto
Global
routing
(initial_opto)
Path group s scenario summary
(initial_opto)
Final_place
:-Timing s
Congestion
Iterations
Tie-cell insertion
Final_opto (final timing report)
• Provide legal location for
entire netlist
• Meeting Power,Timing, and
area targets
Goals of • Minimum cell density and pin
density
Placement

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