Course Title: Digital Electronics Course Code: 22EEG35

Course Type: IPCC (Integrated) CIE: 50 Marks

Credits:4 SEE:50 Marks
HOURS /WEEK:5 3:0:2 (L:T:P) Total Contact Hours: 39 + 26
PREREQUISITE: NIL
COURSE OBJECTIVES
1. Gain a solid foundation in the fundamental concepts of digital electronics.
2. Acquire the skills to design and analyse combinational circuits.
3. Understand how to represent the behaviour of sequential systems using state diagrams.
COURSE CONTENTS
UNIT – 1 ( 7 Hours)
Introduction to different logic families: Electrical characteristics of logic gates – logic levels and noise
margins, fan-out, propagation delay, transition time, power consumption and power delay product, operation of
TTL NAND, ECL and CMOS.
Numbering systems- conversion from one numbering system to another, binary addition, subtraction (1’s and
2’s complement), Simplification and realization of Boolean expressions using basic and universal gates, SOP,
POS forms and standard Canonical forms.
UNIT – 2 ( 8 Hours)
K-map: Introduction, Terms used in K-map, representation, and minimization of 3, 4 and 5 variable functions.
Combinational logic: Half adder, full adder, half subtractor, full subtractor, parallel adder/subtractor, BCD
adder, comparators (1bit, 2 bit &4 bit), 4:1& 8:1 MUX and 1:4&1:8 DeMUX.
UNIT – 3 ( 8 Hours)
Flip Flops: Operation, characteristics and excitation tables of S-R, J-K, D & T Flip flops, Master Slave Flip
Flops,
Conversion from one flip flop to another.
Ripple counter: Introduction, operation of different types, design of Mod N Ripple counter.
UNIT – 4 ( 8 Hours)
Sequential Circuits Analysis: Introduction to Synchronous counter and operation of different types of
Synchronous counter, design of Mod N counter. Design of synchronous counters (self-starting counter)
Synchronous sequential Machines: State table, state diagram, Mealy and Moore Machines, Design and
Analysis of Sequential Circuits using D /T Flip Flops.
UNIT – 5 ( 8 Hours)
Memory and Programmable Logic Devices: Memory and Programmable logic devices definitions, random
access memory (RAM), RAM integrated Circuits, Array of RAM IC’s, Programmable logic technologies, read
only memory (ROM), Programmable Logic Array, Programmable Array Logic Devices.
Experiments
1. Realization of Boolean Expression using Basic gates.
2. Realization of Boolean Expression using NAND gates.
3. Realization of Full Adder and Full Subtractor using MUX74153.
4. Realization of parallel adder/Subtractor using IC7483.
5. Realization of Binary to Gray code conversion and vice versa using DEMUX.
6. Verification of Priority encoder using IC 74147.
7. Realization One bit comparator and study of IC 7485 magnitude comparator.
8. Demonstration of Decoder chip to drive LED display using IC 7446.
9. Verify Truth table of JK Master Slave, T type and D type using IC 7476.
10. Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using IC 74S95.
11. Verify Ring counter and Johnson counter using IC 7495.
 12. Realization of Synchronous MOD 10 Counter using IC 74192.
Text Books
1. M.Morries Mano and Charles Kime, “Logic and computer design Fundamentals”, Pearson Learning, 4 th
edition, 2014.
2. John M Yarbrough, “Digital Logic Applications and Design”, Cengage Learning, 8th Indian reprint,
2011.
Reference Books
1. Donald D Givone, “Digital Principles and Design”, Tata McGraw-Hill, 2002.
2. Charles H Roth, JR and Larry L. Kinney, “Fundamentals of logic design”, Cengage Learning, 6th edition.
Course Assessment Methods
Theory:
1. MSE1 &2 conducted for 30marks and weightage is 40% (12marks), MSE-3 conducted for 30marks
weightage is 20% (6marks).
2. Theory weightage is 70% = 35 Marks, Eligibility is 40% = 14 marks (40% of 35).
3. Learning Activity-1 for 10marks & Learning Activity-2 for 10marks.
Lab:
1. Record & Observation = 25 Marks, Viva-Voce = 05 Marks, Lab test =20 Marks.
2. Lab weightage is 30% = 15Marks (30% of 50), Eligibility is 40% = 06 Marks.
3. Eligibility to appear for SEE: Theory (40% -14 Marks) + Lab (40% -6 Marks)= 40%(20 Marks out of 50
Marks).
4. Final Examination will be conducted and evaluated for 100 Marks and then reduced to 50 Marks.
Course Outcomes
Students will be able to:
1. Analyze the operation of logic family and Boolean expressions.
2. Design various combinational circuits.
3. Analyze the behaviour of sequential circuits.
4. Design simple synchronous and asynchronous counters.
5. Understand several memory technologies and programmable logic devices
 Course Outcomes and their mapping with POs & PSOs
(1: SLIGHT; 2: MODERATE; 3: SUBSTANTIAL)
Course POs PSOs
Outcomes
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4

1 2 3 -- -- -- - - - 2 1 -- -- 1 2 1 --
- - -

2 2 3 -- -- 2 - - - 2 1 -- -- 1 2 1 --
- - -

3 2 3 -- -- 2 - - - 2 1 -- -- 1 2 1 --
- - -

4 2 3 -- -- -- - - - 2 1 -- -- 1 2 1 --
- - -

5 2 3 -- -- -- - - - 2 1 -- -- 1 2 1 --
- - -