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DLD lab 3-

Digital Logic Design

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8 views5 pages

DLD lab 3-

Digital Logic Design

Uploaded by

ffhayatomax26
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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LAB REPORT

Task no : 03
Course code : CSE 224
Course Title : Digital Logic Design Lab

Submitted By
Name :Thoushif Ahammed Farash
ID No : 0242310005101237
Section : M 1
Batch : 64
Dept. of CSE,DIU

Submitted To
Name : Rimi Akter
Designation : Lecturer
Dept. of CSE,DIU
Experiment name: verification of dc morgans theorem.

Equipment:
• Breadboard
• Digital Logic ICs (7400, 7404, 7408, 7432, etc. as required)
o 7400: NAND gate
o 7404: NOT gate
o 7408: AND gate
o 7432: OR gate
• Connecting wires
• Power supply (5V DC)
• LED (for output indication)
• Resistors (330 ohm for current limiting)

Circuit Diagram:
Working Process:
Step-by-Step Procedure:
For First Law Verification:
1. Connect the AND gate: Apply inputs A and B to the AND gate, and the output will be
A⋅BA \cdot BA⋅B.
2. NOT gate for negation: Connect the output of the AND gate to a NOT gate. The output
will now be (A⋅B)′(A \cdot B)'(A⋅B)′.
3. Individual NOT gates: Apply inputs A and B to two separate NOT gates to get A′A'A′ and
B′B'B′.
4. OR gate: Connect the outputs of the two NOT gates to the input of the OR gate. The
output will be A′+B′A' + B'A′+B′.
5. Verification: Compare the outputs of (A⋅B)′(A \cdot B)'(A⋅B)′ and A′+B′A' + B'A′+B′ using
LEDs or other output indicators. Both should give the same result for all combinations of
inputs.
For Second Law Verification:
1. Connect the OR gate: Apply inputs A and B to the OR gate, and the output will be A+BA +
BA+B.
2. NOT gate for negation: Connect the output of the OR gate to a NOT gate. The output will
now be (A+B)′(A + B)'(A+B)′.
3. Individual NOT gates: Apply inputs A and B to two separate NOT gates to get A′A'A′ and
B′B'B′.
4. AND gate: Connect the outputs of the two NOT gates to the input of the AND gate. The
output will be A′⋅B′A' \cdot B'A′⋅B′.
5. Verification: Compare the outputs of (A+B)′(A + B)'(A+B)′ and A′⋅B′A' \cdot B'A′⋅B′. Both
should give the same result for all combinations of inputs.

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