DepartmentofComput

er
SystemsEngineering

DigitalSystemDesign

Handout#09
HDLdesigninVivadoSuite(Int
roductionandSimulation)

LabLearningObjectives:

Aftercompletingthissession,studentshouldbeableto:
 developHDLcodesinVivadoSuite.
 simulatethedesignusingtestbench.

Note:Submitthelabreport(solvedactivitiesandexercises)beforethenextlab.
LabHardwareandSoftwareRequired:

1. Desktop/Laptop Computerwithinternetconnection.
2. XilinxVivado2016.2
3. DigilentNEXYS4DDRFPGABoard

BackgroundTheory:

Vivado Design Suite is a software suite produced by Xilinx for synthesis and analysis
ofhardware description language (HDL) designs. It is a proprietary software to
configureXilinx FPGA boards. We will make HDL designs in Vivado Suite for Digilent NEXYS
4 DDRFPGAboardbyXilinxinourlab.ThisboardisproducedbyXilinx.

Figure9.1:DevelopmentFlow*

*Ref:Book FPGAprototypingbyVerilogexamplesbyPongP.Chu,JohnWiley&Sons
The simplified development flow of an FPGA-based system is shown in figure 9.1.
Theleft portion of the flow is the refinement and programming process, in which a system
istransformedfromanabstract(textual)HDLdescriptiontoadevice(cell-
levelconfiguration)andthendownloadedtotheFPGAdevice.Therightportionisthevalidationpr
ocess,whichcheckswhetherthesystemmeetsthefunctionalspecificationandperformancego
als.Themajorsteps inthefloware:

1. Design the system and derive the HDL file(s). We may need to add a
separateconstraint file to specify certain implementation constraints e.g. input
and outputpins.

2. Develop the testbenchin HDL and perform RTL simulation. The RTL
termreflectsthefactthattheHDLcodeisdoneattheregistertransferlevel.Thisisanoptio
nalbut recommendedsteptoverifythatthedesignisworkingas intended.

3. Performsynthesisandimplementation.
 The synthesisprocess is generally known as logic synthesis, in which
thesoftware transforms the textual description to generic gate-level
components,suchassimplelogicgates andFFs.
 The implementationprocess consists of merging multiple design files
andderivingthephysicallayout(electronic components and their
connectionswithI/Opins)insidetheFPGAchip.threesmallerprocesses:translat
e,map,andplace androute.

4. Generateanddownloadtheprogrammingfile.Inthisprocess,aconfigurationfileis
generated according to the final netlist. This file is downloaded to an
FPGAdevice serially to configure the logic cells and switches. The physical circuit
canbe verified accordingly.
LabActivity:

TheobjectiveofthislabactivityistodemonstratehowasimpleHDLdesignisdeveloped,and
finally downloaded to the Xilinx board using Vivado Design Suite. We are going
tomakeANDcircuitwith2-bitinputand1-bitoutput.Pleasefollowthestepsgivenbelow.

> PART#1:Writingamodule.
YouwilllearnhowtocreateaprojectandwriteaVerilogfileinVivadoSuite.

1. Open Vivadoinyourcomputer.

2. ClickCreateNewProject.

3. Entertheprojectnameandlocation.
4. SelectRTLProject.

5. ChooseNexys4DDRboard.

Note:Ifyoudonotfindthisboard,youneedtodothefollowing:
a. Downloadlatestboardsfrom:
https://github.com/Digilent/vivado-boards/tree/master/new/board_files
b. Unzipandcopyallthefilesto<VivadoPath>\2016.2\data\boards\board_files
c. RestartVivado.
6. Afterfinishingthewizard,youmayseethefollowingscreen.

7. NowyouneedtocreateamoduleforyourVerilogdesign.ClickProjectManager>AddSource
s.
8. ClickCreateFileandthenspecifyVerilogasfiletypeandgiveanametoyourmodule,saymyA
ND.

9. Youmayspecifyintendedinputs andoutputs(optional,but recommended)

10. NowyoumayseethemodulemyAND.vwithspecifiedinputsandoutputsalreadydeclared.

11. YoumaywritetheHDLcodeofyourdesigninthismyAND.vfile.Pleasemakesuretosaveyou
rcode(useCtrl+S).
>PART#2:Simulation.
Youwillwriteatestbenchfileandsimulateyourdesign(Optional,butrecommended)

1. ClickAddSourcesbyrightclickingon SimulationSources.

2. Createatestbenchfile,e.g.,myAND_tb.(Donotspecfiyanyinputs/outputs)

3. Editthetestbenchfile(myAND_tb.v)andsave.Youwillseethehierarchychangesasfoll
ow:
 4. Nowyoumayrunbehaviouralsimulation.

Atthisstageyoumayobservewhethertheoutputofyourdesignmatcheswiththeintendedoutput.

Exercise:
MakethefollowingHDLdesignswithtestbenchesandsimulate.
1. Afulladdercircuit.
Design code:
`timescale 1ns / 1ps

module fa(input a,b,cin, output sum,carry);

assign sum=a^b^cin;
assign carry=(a&b)|(b&cin)|(cin&a);

endmodule
Testbench code:
`timescale 1ns / 1ps

module fatb;
rega,b,cin;
wire sum,carry;

fa uut(a,b,cin,sum,carry);
 initial begin

$monitor (" a=%b b=%b cin=%b carry=%b sum=%b", a, b, cin, carry, sum);
a = 0; b = 0; cin = 0;
#10
a = 0; b = 0; cin = 1;
#10
a = 0; b = 1; cin = 0;
#10
a = 1; b = 1; cin = 0;
#10
a = 1; b = 1; cin = 1;
#10
$finish;
end

endmodule

2. AsequentialcircuitofyourchoiceusingD-FF.
 Design code:
module binary_counter (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk or posedge reset) begin
if (reset)
q <= 4'b0000; // Reset counter to 0
else
q <= q + 1; // Increment counter
end
endmodule

module top_module #(parameter CLOCK_FREQ = 100000000) (

input wire clk, // External clock input
input wire reset, // Reset input
output wire [3:0] q // 4-bit binary counter output
);

wire one_second; // Output from time_divider

// Instance of time_divider
time_divider #(.CLOCK_FREQ(CLOCK_FREQ)) time_div (
.clk(clk),
.reset(reset),
.one_second(one_second)
);

// Instance of binary_counter
binary_counter counter (
.clk(one_second),
.reset(reset),
.q(q)
);

endmodule

module time_divider #(parameter CLOCK_FREQ = 100000000) (

input wire clk, // External clock input
input wire reset, // Reset input
output reg one_second // One second output signal
);

reg [31:0] counter = 0; // 32-bit counter to track clock cycles

always @(posedge clk or posedge reset) begin

if (reset) begin
counter <= 0;
 one_second <= 0;
end else begin
if (counter == (CLOCK_FREQ - 1)) begin
counter <= 0;
one_second <= ~one_second; // Toggle the one_second signal
end else begin
counter <= counter + 1;
end
end
end
endmodule

Testbench:
`timescale 1ns/1ps
module tb_top_module();
reg clk;
reg reset;
wire [3:0] q;

// Parameter for the simulation clock frequency

parameter CLOCK_FREQ = 100;

// Instantiate the top module

top_module #(.CLOCK_FREQ(CLOCK_FREQ)) uut (
.clk(clk),
.reset(reset),
.q(q)
);

// Generate a 10ns clock period for simulation

always #5 clk = ~clk;

initial begin
// Initialize signals
clk = 0;
reset = 0;

// Apply reset
reset = 1;
#20;
reset = 0;

// Run simulation for a sufficient duration to observe one-second toggles

#2000;

// End simulation
$stop;
end
 initial begin
// Monitor the counter value
$monitor("Time: %0dns, Reset: %b, Counter: %b (%0d)",
$time, reset, q, q);
end
endmodule
HDLdesignandtestbenchcodeusedinthislabactivity:

//myAND.v //myAND_tb.v
`timescale1ns/1ps
`timescale1ns/1ps

module modulemyAND_tb;
myAND(input //signaldeclarationr
[1:0] eg[1:0]
i,outputout test_in;wiretest_out
); ;

assignout=i[1]&i[0];en //instantiatethecircuitundertestmy
ANDuut(test_in,test_out);
dmodule
//testvector generatorinitial
begin
test_in = 2'b00;
#200;test_in = 2'b01;
#200;test_in = 2'b10;
#200;test_in=2'b11;#
200;
$stop;
end
endmodule