SYLLABUS

ANNA UNIVERSITY, CHENNAI

VLS! AND CHIP DESIGN
UNIT I MOSTRÄNSISTOR PRINCIPLES [CHAPTERS 1,2,3]
MOS logic families (NMO and CMOS), Ideal and Non Ideal IV Characteristics, CMOS
devices. MOS(FET) Transistor Characteristic under Static and Dynamic Conditions,
Technology Scaling, Power consumption.
UNIT II COMBINATIONAL LOGIC CIRCUITS CHAPTERS - 4,5,6] 9
Propagation Delays, stick diagram, Layout diagrams, Examples of combinational logic
design, Elmore's constant, Static Logic Gates, Dynamic Logic Gates, Pass Transistor Logic,
Power Dissipation, Low Power Design principles.

UNIT I SEQUENTIAL LOGIC CIRCUITS AND CLOCKING STRATEGIES

[CHAPTER 7I 9
Static Latches and Registers, Dynamic Latches and Registers, Pipelines, Nonbistable
Sequential Circuits. Timing classification of Digital Systems, Synchronous Design,
Self-Timed Circuit Design.

UNIT IV INTERCONNECT, MEMORY ARCHITECTURE AND ARITHMETIC

CIRCUITS [CHAPTERS- 8,9,10,11]
Interconnect Parameters – Capacitance, Resistance, and Inductance, Electrical Wire Models,
Sequential digital circuits: adders, multipliers, comparators, shift registers. Logic
Implementation using Programmable Devices (ROM, PLA, FPGA), Memory Architecture
and Building Blocks, MemoryCore and Memory Peripherals Circuitry.

UNIT V ASIC DESIGN AND TESTING [CHAPTERS 12,13, 14]

Introduction to wafer to chip fabrication process flow. Microchip design process & issues
in test and verification of complex chips, embedded cores and SOCs, Fault models, Test
coding. ASIC Design Flow, Introduction to ASICs, Introduction to test benches, Writing test
benches in Verilog HDL, Automatic test pattern generation, Design for testability,
Scan design: Test interface and boundary scan.

TOTAL: 45 PERIODS
 CONTENTS
UNIT 1: MOS TRANSISTOR PRINCIPLES

CHAPTER 1: INTRODUCTION TO VLSI. 1.1 -1.31

1,1 Introduction .. ...... 1,1

.....1.2
1.1.1 Classifications of Integration (1Cs)
1.1.2 Advantages, Disadvantages AndApplications of VLSI............1.3
...
1.2 MOS Transistor. 1.5
Introduction
.....1.5
1.2.1
..... 1.6
1.2.2 Working Principle...
Á2.3 MOS Transistor Switches: Switch-Level Models:Simple ON/OFF
Switches.. ....1.7
1.2.4 Modes of Operation. .....1.9
1.2.5 MOSFETApplications ..1.10
1.2.6 CMOS. .1.11
..
1.3 MOS Logic Families 1,12
1.3.1 Introduction .1.12
1.3.2 NMOS Logic Families ...1.12
1.3.3 PMOS Logic Families. ......1.15
1.3.4 CMOS Logic Families... ...1.15
14 Two Marks Questions And Answers .1,25
1.5 Review Questions. ....
1.31

CHAPTER 2: MOSTRANSISTOR THEORY ..2.1 -2.35

2.1 Long-Channel (Ideal) I-V Characteristics... ...2.1
2.1.1 Average Gate to Channel Voltage... ....2.1
2.1.2 Transistor Dimensions. ...2.3
 VLSI and Chip Design
2

2.1.3 Mobility. ...2. 4

Operations..
....2.5
2.1.4
I-V Effects..s... 2,7
.2 Non-Ideal I-V Characteristics (Or) Non-ldeal
2.2.1 Introduction.... ...............2.
2.2.2 Mobility Degradation and Velocity Saturation.... ..2.7

2.2.3 Channel Length Modulation (CLM) ..2.11

2.2.4 Threshold Voltage Effects OIOATMi E4A
2.2.5 Leakage.. ...2.14
2.2.6 Temperature Dependence ....2. 15
-L. 2.2.7 Geometry Dependence .....2.16
.. 202,16
2.3 CMOS Devices
2.3.1 Transmission Gates (TGs):Transmission Gate Logic (TGL)....2.16
2.3.2 Multiplexers: Data Selectors ..2.19
2.4 Solved Problem. .2.26
...
2.5 TwoMarks Questions and Answers.... 2.30
2.6 Review Questions .... .2.35

CHAPTER.3: MOSFET TRANSISTOR CHARACTERISTICS.... 3.1-3.24

3.1 Dc Transfer Characteristics: Static ...
Behavior. 3.1
3.1.1 Introduction ....3.1
3.12 Static CMOS Inverter DC Characteristics. ...3.1
3.2 C-V Characteristics: a..3.5
Dynamic Behavior.
3.2.1 Introduction 3.5
3.2.2 Simple MOS Capacitance 2tiuisesu) wor91 3.6
Model
3.2.3 Detailed MOS Gate Capacitance .....3.8
Model ...
2E3.2.4 Detailed MOS Diffusion Capacitance aaTO3.11
Model.....
3.3 Technology Scaling.
.3.13
....
3.3.1 Introduction 3.13

3.3.2 Scaling Models. ...3. 14

 Contents
C3
3.3.3 Scaling Factors ....3.15
3.3.4 Scaling Factors for Device Parameters. ....3.15
3.3.5 Summary of Scaling Effect for Different Devices.. ....3.17
3.3.6 Merits and Demerits of Scaling.. ....3.19
3.4 Power Consumption (or) Power Dissipation.
s.3.19
3.5 Two Marks Questions and Answers...
3.20
3.6 Review Questions...
3.23

UNIT 2: COMBINATIONAL LOGIC CIRCUITS

CHAPTER 4: COMBINATIONAL LOGIC CIRCUITS

4.1-4.32
4.1 Propagation Delays.. ...4.1
4.1.1 Introduction ..4.1
4.1.2 Delay Estimation. .4.2
4.1.3 Critical Path. 4.3
4.1.4 Rc Delay Model... .4.4
4.2 Stick Diagram...
..4.5
4.2.1 Introduction .4.5
4.2,2 Example. .4.7
4.2.3 Gate Area Estimation... 4.9
4.3 Layout Diagrams....
4.12
4.3.1 LayoutDesign Rules .4.12
4.3.2 Gate Layouts.... ..... 4.17
4.4 Exarmples of Combinational Logic
Design.. ....4.21
4.5 Examples
.4.24
4.6 Two Marks Ouestions And Answers
.4.27
4.7 Review Questions.
.4.32
 VLSI and Chip Design
C4
CHAPTER 5: CMOS DESIGN.. 5.1 -5.42

Constant. *..5.1
5.1 Elmore's Delay (0r) Elmore's
Introduction ..5.1
5.1.1
Example.... .5.2
5.1.2
Normalized Delay...... .5.2
5.1.3
.5.3
5.1.4 Delay Components
Elmore Delay of a CMOS Inverter..... ..5.3
5.1.5
5.2. Circuit Families.. ...5.4
5.3 Static CMOSDesign: Static Logic Gates.... .....5.5
... .5.5
Introduction
5.3.1
CMOS.
... 5.5
Li.t 5.3.2...Complementary
5.3.3 Bubble Pushing.. ....5.7
5.3.4 Compound Gates 5.8
....... 5.10
5.3.5 Skewed Gates
Asymmetric Gates.
....... 5. 11
5.3.6
.....5.12
5.3.7PN Ratio
5.4 Ratioed Circuits.... 5.13
........
5.4.1 Introduction ... 5.13

5.4.2 Pseudo-NMOS Logic Gate. ....5.15

5.5 Dynamic Circuits: Dynamic Cmos Design: Dynamic Logic Gates.... 5.17
5.5.1 Introduction ...5.17
.... 5.19
5.5.2 Basic Principles
S14 5.5.3..Properties of Dynamic Logic Gate. ..........5.21
5.5.4 Examples of Dynamic Logic ....5.21.
...5.23
5.6 Domino Logic
5.6.1 s..5.23
Introduction
5.6.2 Working Principle... ...5.24
5.7 Dual-Rail Domino Logic. .5.26
5.8 NP Domino Logic (Nora Logic):NP-CMOS
5.9 Solved Examples.
.. 5.29
5.30
5.10 Two Marks Questions and Answers ..5.35
Contents C.5
5.11 Review Questions. 5.42

CHAPTER 6: PASS-TRANSISTORS LOGIC.... ...6.1 -6.25

6.1 Pass-Transistors Logic (Ptl) .6.1
6.1.1 Introduction .....6.1
( 6.1.2 Basics of Pass-Transistor.... .6.4
CT.6.1.3 Complementary Pass- Transistor (CPL) Logic.. ...6.5
At 6.1.4 Examples ...6.6
6.1.5 Properties...
*... 6.8
6.1.6 Advantages of PTL..... ...6.9
6.2 Power Dissipation... ...
6.9
6.3 DYNAMIC POWER DISSIPATION...
6.10
Ki6.3.1 Dynamic Power Dissipation Due to Switching: Charging/
Discharging... ...6.10
6.3.2 Dynamic Power Dissipation Due to Short Circuit Current .......6.13
6.3.3 Dynamic Voltage Scaling (DVS) [ORI
Dynamic Voltage/ Frequency Scaling (DVFS) ...6.14
6.4 STATICPOWER DISSIPATION 6.15
6.4.1. Introduction .....6. 15
6.4.2 Power Gating.. .... 6.17
6.5 LOW POWER DESIGN PRINCIPLES (OR) TECHNIQUES
.6.18
6.6 TWO MARKS QUESTIONS AND ANSWERS
6.21
6.7- REVIEW QUESTIONS.
.6.25

UNIT 3: SEQUENTIAL LOGICCIRCUITS AND

CLOCKING STRATEGIES

CHAPTER 7: SEQUENTIAL LOGIC CIRCUIT

DESIGN ... 7.1 -7.65
7.1 Introduction... ..7.1
C.6 VLSI and Chip Design

7.1.1 Classification of Memory Elements 13

7.2 Static Latches and Registers...
.7.4
7.2.1 Bistability Principle.... .7.4
7.2.2 Multiplexer-Based Latches... .7.6
7.2.3 Master-Slave Edge-Triggered Register . ...7.9
7.2.4 Low-Voltage Static Latches.. ..7.11
7.2.5 Static SR Flip-Flops ...7.12
7.3 Dynamic Latches and Registers. 7.14
7.3.1 Introduction ..7.14
7.3.2 Dynamic Transmission-Gate Edge-Triggered Registers ... ..... 7.15
e.7.3.3 Clocked CMOS (C'MOS) Register...
....7.16
7.3.4 True Single-Phase Clocked Register (TSPCR) ..... .7.17
7.4 Pipelining: An Approach to optimize Sequential
Circuits...... 7.20
7.4.1 Introduction
...7.20
7.4.2 Pipeline Concept..
.7.21
7.4.3 Latch-Versus Register Based Pipelines.
.....23
7.4.4 NORA-CMOS Latches.
..7.25
7.5 Nonbistable Sequential Circuits.
7.27
7.5.1 Schmitt Trigger...
.7.27
7.5.2 Monostable Sequential Circuits.
...7.30
7.5.3 Astable Sequential Circuits
7.6 Timing Classification ...7.30
of Digital Systems... .7.34
7.6.1 Introduction
7.6.2
...7.34
Synchronous Interconnect
...7.35
7.6.3 Mesochronous Interconnect. ....7.36
7.6.4 Plesiochronous Interconnect...
7
7.6.5 Asynchronous Interconnect.. .......3
7.7 Synchronous 7.38
Design.
7.7.1 7.39
Synchronous Timing Issues
(or) Timing Basics .7.39
Contents.lrt C.7
F
7.7.2 Clock-Distribution Techniques... ......1.47
7.8 Self-Timed Circuit Design... 7.49
¿7.8.1 Self- Timed Logic- An Asynchronous Technique... ...7.49
7.9 Two Marks Questions and Answers....
...7.54
7.10 Review Questions... ....7.63

UNIT 4: INTERCONNECT, MEMORY ARCHITECTURE

AND ARITHMETIC CIRCUITS !

CHAPTER 8: INTERCONNECT .s.. 8.1-8.22

8.1 Interconnect Parameters. .8.1
8.1.1 Capacitance.... .8.1
8.1.2 Resistance. ...8.5
8.1.3 Inductance... .8.9
8.2, Electrical Wire Models.... ... 8.9
8.2.1 The Ideal Wire. ....8.9
8.2.2 Lumped Model .8.10
8.2.3 The Lumped RC Model.... ....8.11
8.2.4 The Distributed rc Line ....8.13
Ep 8.2.5 Transmission Line Model ....8.15
8.6: Two Marks Questions and Answers... 8.19
8.7 Review Questions. B.. 8.22

CHAPTER 9: SEQUENTIAL DIGITAL CIRCUITS 9.1 -9.52

9.1 Adders.
.9.1
9.1.1 Introduction.
...9.1
9.1.2 Single- Bit Binary Adder ....9.1
9.1.3 CMOS Implementation of Full Adder. ....9.4
C.8 VLSIand Chip Design

9.1.4 Ripple-Carry Adder ....9.7

.9.1.5 Carry-Bypass (Skip) Adder. ..9.9

9.1.6 Linear Carry-Select Adder. ....9.13

9.1.7 Square-Root Carry-Select Adder

..... .......9.14
9.1.8 Carry Look ahead Adder (CLA).... .9.17
9.2 Multipliers. ...9.23
9.2.1 Introduction ...9.23
Definitions of Multiplier. ...9.23
9.2.2
9.2.3 DOT Diagrams ...9.25

9.2.4 Partial -Product Generation: Booth's Multiplication.... ......9.25

.....
9.2.5 Partial-Product Accumulation: Array Multipliers 9.29

9.2.6 Tree Multiplier: Wallace Tree Multiplier... ....9.33

9.2.7 Final Addition.. ....9.36

9.3 Shift Registers (0r) Shifters.... eoso 9.36

9.3.1 Introduction ...9.36

9.3.2 Barrel Shifter ...9.38

9.3.3 Logarithmic Shifter .9.40

9.4 Comparators .... .9.41

9.4.1 Magnitude Comparator... ..9.41

9.4.2 Equality Comparator ...9.43

9.5 Two Marks Questions and Answers.... 9.43
9.6 Review Questions. esess 9.51

CHAPTER 10: LOGIC IMPLEMENTATION USING PROGRAMMABLE

DEVICES .10.1-10.13
10.1 Programmable Logic 10.1
Array (Pla)...
10.2 Field Programmable Gate
Array(Fpga)
10.2.1 Introduction....
.. 10.4
10.4
 Contents
C9
10.2.2 General FPGAArchitecture
.10.6
10.3 Two Marks Questions And Answers..
.10.11
10.4 Review Questions.ss...
.10.13

CHAPTER 11: DESIGNING MEMORY AND ARRAY

STRUCTURES... ... 11.1 -11.52
11.1 Memory Classification 11,1
11.2 Memory Architectures and Building Blocks. 11,3
11.2.1 Architectures For N- word Memory.. 11.3
11.2.2 Array- Structured Memory. ....11.5
11.2.3 Hierarchical Memory Architecture.. ....11.6
11.2.4 Contents Addressable Memory (CAM) Architecture .11.7
11.3 Memory Core.. .....11.10
11.3.1 Read Only Memory (ROM) .... 11.10
11.3.2 Nonvolatile Read-Write (NVRM) Memories. ........11.15
11.3.3 Read-Write (NVRWM) Memories 11.21
11.3.4 Contents-Addressable or Associative memory (CAM)......... 11.29
11.4 Memory Peripheral Circuitry. ..11.31
11.4.1 The Address Decoders.. 11.31
11.4.2 Sense Amnplifiers. ..
11.36
114.3 Voltage References ... 11.42
11.5 Two Marks Questions and Answers .11.46
11.6 Review Qustions..... ..11.51

UNIT 5: ASIC DESIGN AND TESTING

CHAPTER 12: ASIC DESIGN ..

12.1- 12.26
12.1 Introduction to Wafer to Chip Fabrication Process Flow (0r)
Semiconductor Manufacturing Process..... .12.1
C.10
VLSI and Chip Design
12.1.1 Introduction
12.1
12.1.2 Steps .. ....12.2
12.2 Microchip Design Process And Issues In Test and Verification Of I
Complex Chips. 12.8
12.2.1 Introduction 12.8
12.2.2 Trends in Chip Design... .12.9
12.2.3 Chip Design Flow. .12.9
12.2.4 Issues in Test and Verification. .12.12
12.3 Embedded Cores And Socs... y0112.12
12.3.1 Embedded Cores.... 12.12
12.3.2 General Purpose and Domain specific Processors ... 12.13
12.3.3 Application Specific Integrated Circuits (ASIC) .12.15
2 12.3.4 Programmable Logic Devices (PLDS)... 12.15
12.3.5. Commercial off-the-shelf components (COTs) 12.16
12.3.6 System On Chips(SOCs).... .. 12.16
12.3.7 Design Flow of SOCs.... ....12.17
12.3.8 Advantages of SOCs... ....12.23
12:4 Two Marks Questions And Answers... .12.24
12.5 Review Questions... ...12.26

CHAPTER 13: TEST BENCHES. ...13.1 -13.27

13.1 Fault Models.... 13.1

13.1.1 Introduction ....13.1

13.1.2 Stuck-At Faults. 13.1

13.1.3 Examples. 13.2

13.3
13.1.4 Switch Level Fault Model
.. 13.6
13.2 Introduction To ASICs...
13.7
13.2.1 Types of ASICs.
13.3 ASICDesign Flow ...13.16
Contents C.11|

13.4 Introduction of Test Benches.. ..13.18

13.4.1 Components of Simulation. ....
13.18
13.5 Writing Test Benches in Verilog HDL.... .13.19
13.5.1 Instantiating the DUT. .13.19
13.5.2 Modeling Time in Verilog .13.20
13.5.3 Timescale Compiler Directive.... .13.21
13.5.4 Verilog Initial Block 13.21
13.5.5 Example. .....13.21
13.6 Two Marks Questions and Answers... ...13.22
13.7 Review Questions... .13.27

CHAPTER 14: TESTING. ...

14.1 -14.16
...
14.1 Automatic Test-Pattern Generation (ATPG)..... 14.1
14.2 Design Of Testability.. 14.2
... 14.2
14.2.1 Introduction
14.2.2 Ad.Hoc Testing. .14.3
14.2.3 Scan Design .... 14.4
14.2.4 Built -In Self-Test (BIST). 14.7
14.2.5 IDDQ Testing 14.12

14.2.6 Design For Manufacturability .14.13

14.3 Scan Test... ...14.14

Model Anna University Question Papers... ..MQ.1- MQ.10

 UNIT MOS TRANSISTOR
PRINCIPLES

Chapter-1
INTRODUCTION TO VLSI

1,1 INTRODUCTION

aDefinition of VLSI

Very- Large- Scale - Integration (VLSI) is the process of creating an Integrated

Circuit (1C) by combining thousands of transistors into a single chip:
In 1958, Engineers managed to put two transistors onto a silicon crystal and then
created the first integrated circuit, which was subsequently led to the first
microprocessor.
ko
The vacuum tubes that ruled in first half of 20" century were large, expensive,
power-hungry, inefficient and unreliable. Before transistors, computers used
vacuum tubes and mechanical switches to process information.

Then IC is developed to replace vacuum. tubes which are accommodating

hundreds, thousands, or even billions of passive and active electronics
components onto a tiny single chip of silicon.

ICs dissipates less heat; consumes less energy and very reliable çompared to the
Vacuum tubes.
12| VLSIand Chip Design

e Need ofIntegration
- To
increase the number ofcomponents in a chip.
Toreduce the size of the device.

Toincrease the device speed.

VLSI was begun in 1970s when complex semiconductor and communication

technologies were being developed. Before the introduction of VLSI technology
most ICs had a limited set of functions they could perfom.
An electroniccircuit might consist of a CPU, ROM, RAM and other gate logics.
VLSI lets IC designers to add all of these into one chip.
The microprocessor is a VLSI device which is essential for making many of the
products we use every day such as TVs, cars, radios, home appliances and
computers. Transistors are the main components of microprocessors.

1.1.1Classifications of Integration (ICs)

The integration is classified based on the number of components (transistors) to be
integrated on a single silicon chip. They were mainly categorized as,

(1) Small Scale Integration (SSI)

The SSI is a first integrated technology which contains 1-100 transistors and is
fabricated on a single chip.
Examples: Logic gates, Flip-flops.

(2) Medium Scale Integration (MSI)

Using this technology, 100-1000 number of
transistors can be integrated on a
single chip.

Examples: 4 -bit microprocessors, Amplifiers, Counters.

(iii) Large Scale Integration (LSI)

In LSItechnology, 1000-10000 transistors can be integrated on a single chip.

Examples: 8 -bit Microprocessors, RAM, ROM

Introduction to VLSI |1.3|

(iv) Very LargeScale Integration (VLSI)

In VLSI technology, 10000-1 million transistors can be accommodated on a
single chip.
Examples: 16 bit and 32 bit microprocessors.

(v) Ultra Large Scale Integration (ULSI)

In ULSI technology, I million-10million transistors can be integrated on a single
chip.
Examples: Special purpose registers, Smart sensors.
(vi) Giant Scale Integration (GSI)
In GSItechnology, nore than10 million transistors can be integrated on a single
chip.

Example: Embedded Systems.

1.1.2 Advantages, Disadvantages And Applications of VLSI

Advantages
VLSI has many advantages are,
() Reduces the size of circuits (compactness).
(ii) Reduces the effective cost of the devices (low cost).
(iii) Increases the operating speed of circuits due to absence of parasitic
y
capacitance effect.
(iv) Requires less power than discrete components.
(v) Higher reliability.
(vi) Occupies a relatively smaller area (effective use of space).
(vii) Mobility.
(vii)The small size of IC's causes lesser power consumption and thus reduces
power loss.
(ix) Easy available productivity.

(x) Large market background.

 VLSIand Chip
14 Design

Disadvantages:

The disadvantages of VLSI are, cisyt

) Some complex IC's may be costly. We cannot repair an individual

component inside the ICwhich is too small.
more than 10 watts.
(ii) The power rating for most of the IC's does not exceed
Thus,it is not possible to manufacture high power IC's.
cannot be integrated into
(ii) Some components like transformers and inductors
an IC.They have to be connected externally to the semiconductor pins.

(iv) High grade p-n-p assembly isnot possible.

(or) exposed to excessive
(v) The ICwill not work properly if wrongly handled
heat.

(vi) It is difficult to achieve low temperature coefficient.

(vii) It is difficult tofabricate an IC with low noise.

that exceed a value of 30pF. Thus,
(vii)It is not possible to fabricate capacitors
are to be connected externally to an IC.
high value capacitors

a Applications
are widely used in various branches of Engineering
In today's world VLSIchips
like:

() Voice and data communication networks.

(ii) Digital Signal Processing (DSP).

(ii) Computers.
(iv) Commercial electronics.

(v) Automobiles.

(vi) Medicine and many more.

 Introduction to VLSI
15
K2 MOS TRANSISTOR

1.2.1 Introduction
The most basic element in the design of a large scale integrated circuit
is the
Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) which is a type
of Field- Effect Transistor (FET).
o MOSFET has an insulated gate, whose voltage determines the conductivity of the
device. This ability to change conductivity with the amount of applied voltage
can be widely used for amplifying (or) switching electronic signals in the
electronic devices.
Gate (G)

Oxide layer

Drain (D)
Source (S) Channel

Substrate

Body (B)
Fig 1.1 Internal structure ofMOSFET
oo
Figure 1.1 shows the internal structure of MOSFET transistors and it have.three
terminals, such as Drain (LD), Source (S) and Gate (G) and also one more
terminals called Substrate (or) Body (B) is used in the circuit connections.

The gate electrode is insulated from the channel near an extremely thin layer of
metal oxide.

The body of the MOSFET is frequently connected to the source terminal so

making it into a three terminal devices like FET, MOSFET which has three
layers namely,
(i) Metal gate electrode layer.
(ii) Insulating oxide (SiO2) layer.
(iii) p (or) n type substrate.
|1.6 VLSI and Chip Design

Transistors are built on nearly flawless single crystals of silicon, which are

available as thin flat circular wafers of 15-30 cm in diameter.

1.2.2 Working Principle

MOSFET also acts as a voltage controlled resistor when no current flows into
a
the gate terminal. It works electronically by varying the width of channel along
which charge carriers flow(electrons or holes).

The small voltage at the gate terminal controls the current flow through the
channel between the source and the drain terminals (channel length L).

a
Types of MOSFET
The main types of MOSFET based on the charge carriers namely,
() n-channel MOSFET (or) nMOS transistor (or) NMOS tranistor.
(1)p- channel MOSFET (or) pMOS transistor (or) PMOS transistor.

4 If the MOSFET channel consists of electrons then it is called as nMOS

transistor, and if MOSFET consists of holes, then it is called as pMOS
transistor.
D D

P N

Substrate G Substrate
N P
n-channel
p-channel

P N

p-channel MOSFET n-channel MOSFET

Fig 1.2 Types of

MOSFET
Introduction to VLSI
1.7

The channel is formed between the drain and source

in the opposite type to the
substrate, n -channel is made with a p-type substrate and
p-channel is made
with an n-type substrate. The conductivity of the channel due to an
electrons (or)
holes depends on n-type (or) p-type channel respectively.
(Conductor)
Source Gate Drain Polysilicon Source Gate Drain

SiO,
(Insulator)

p-doped semiconductor substrate n-doped semiconductor substrate

Fig 1.3Cross Section View

The n+ and p+ regions indicate heavily doped n- orp- silicon. Since the 1970,
the gate has been formed from polycrystalline silicon. i.e. polysilicon. The body
is typically grounded.

a MOSFET Symbols:
D D

G G
T
S

Fig 1.4 Symbols of MOSFET

L,2.3 MOSTransistor Switches: Switch-Level Models: Simple

ON/OFF Switches
The positive voltage is usually called Vop (or) Power which is represented as
logic I value in digital circuits.
 VLSI and Chip Design
1.8
or Vss and it is represented as logic0
The low voltage is called Ground (GND)
which is normally 0 volts.
G=0 G=1

nMos ON
OFF

ON OFF
pMos

Fig 1.5 MOSFET as switcles

MOS transistors to be viewed as simple ON/OFF switches.

(i) nMOS Transistor:

When the gate (G=1) of an nMOS transistor is '1 then the transistor is
(a)
ON.
I acts as a closed switch" and there is a conducting path from the
Source to the drain.

(b) When the gate is low, then the nMOS transistor is OFF. It acts asa
(G-0)
"opened switch" and almost zero current will flows fom source to the
th
drain.

(i) pMOS Transistor:3vai aiii

loW.
the gate is (G=0)
A
pMOS transistor is just the opposite. II
is ON when
and OFF when the gate (G =l) is high.
Introduction to VLSI 1.9

1,2.4 Modes of Operation

In MOSFET, the two types of operation modes corresponding to whether the
transistor is in ON state (or) OFF state at zero gate-source voltage (Vos = 0)
are,

() Enhancement mode, and

(i) Depletion mode.

(1) Enhancement Mode
The Enhancement mode MOSFET is equivalent to a "normally open" switch.
These devices are OFF at zero gate-source voltage for both nMOS and
pMOS. These types of transistors require Vos to switch ON the device.

It will turn ON by pulling the gate voltage higher than the source voltage for
nMOS(or) lower than the source voltage for pMOS.
Drain (D) Drain (D)

-o Substrate o Substrate
Gate (G) Gate (G) o

Source (S) Source (S)

(a) N-Channel (b) P-Channelt

Fig 1.6 Symbols of enhancement mode MOSFET

The symbols of both n-channel and p-channel enhancement mode MOSFET

transistors are shown in Fig 1.6. Here, the broke line represents connection
between the source and drain which represents the enhancement mode type.

In this mode, the conductivity increases by increasing the oxide layer which
an
adds the carriers to the channel. Generally, this oxide layer is called
Inversion layer'.
|1.10 VLSI and Chip Design

(2) Depletion Mode

are generally "switched ON" at
The depletion mode MOSFET transistors
to a "normally closed»
zero gate-source voltage (Vos = 0)and it is equivalent
Switch and requires Vas to switch OFF the
device. If the gate voltage

increases in positive, then the channel width increases.

Drain (D)
Drain (D)

Substrate o Substrate

Gate (G) o Gate (G)

Source (S) Source (S)

(a) nMOS (b) pMOs

Fig 1.7Symbols depletion mode MOSFET

of

The symbols used for depletion mode of MOSFETs in both n-channel and
p-channel types are shown above in Fig 1.7. The fourth terminal substrate is
connected to the source terminal.
The continuous thick line which is connected between the drain and the
source terminal represents the depletion type. The arrow symbol indicates the
type of channel, such as n-channel (or) p-channel.
The conductivity of the channel in depletion MOSFETs is less when
compared to the enhancement type of MOSFETS.

2.2.5 MOSFET Applications

The main applications of MOSFET are as follows:
) MOSFETs are used in digital integrated circuits, such as microprocessors.
(ii) Used in calculators.
(ii) Used in memories and in logic CMOS gates.
(iv) Used as analog switches.
(v) Used as amplifiers.
 Introduction to VLSI
|1.11|

(vi) Used in the applications

a
of power electronics and switch mode power
supplies.
(vii) MOSFETs are used as oscillators in radio systems.
age
(viiil)Used in automobile sound systems and in sound reinforcement systems.

1.2.6 CMOS
The term CMOS stands for "Complementary Metal
Oxide Semiconductor". It is
one of the most important
technologies in the computer chip design industry
and
broadly used today to form Integrated Circuits numerous
(1Cs) in varied
applications.
CMOS fabrication technology, which
requires both n-channel (nMOS) and p
channel (pMOS) transistors to be built on the same
chip substrate.
To accommodate both nMOS
and pMOS devices, special regions must be
created in which the semiconductor type is
opposite to the substrate type. These
and regions are called wells (or) tubs.
e
is
A CMOS Applications
The CMOS technology has been used for the following designs:
the
) Microprocessors.
the
(ii) Microcontrollers chips.

hen (i) Computer memories like RAM, ROM and

Flash memory chip designing.
(iv) All digital logic circuits.

() Application Specific Integrated Circuits

(ASICs),orf
Advantages
The main advantages
of CMOS over NMOS and BIPOLAR technology are:
) Low static power dissipation.
(1) This allows integrating more
CMOS gates on an IC than
resulting in much better performance. bipolar technology,
1.12| VLSI and Chip Design

(iii) This technology makes use of both p' channel and 'n' channel
semiconductor devices.
(iv) High noise margin.

(v) High packing density. avs

source are interchangeable.
(vi) Bidirectional capability, that is, drain and

(vii) Scalable threshold voltage.

(viii) Low output drive current.

1.3 MOS LOGIC FAMILIES

1.3.1 Introduction
All thelogic gates that are built with MOSFET devices will come under MOS
logic family and it can be classified into three categories:

) NMOS Iogicfamily - Built with N-channel MOSFET:

() PMOS Iogic family -Built with P-channel MOSFET.
(iti) CMOS logic family–Built with both N-channel and P-channel MOSFET.

CMOS logic family is a group of logic circuits which are built with
complementary MOS devices. Off all the MOS families, NMOS and CMOS are
used in making an integrated circuit, because of its advantages.

1.3.2 NMOS Logic Families

In the N-channel MOS family, current conductionis because of the electrons.
The negatively charged electrons are fast-moving than holes, which is positively
charged. So the speed of operation of NMOS isfasterthan PMOS.

(1) NMOS Inverter

The NMOS inverter circuit has two N-channel MOSFET devices.

Among tio
two MOSFETs, O, acts as the load MOSFET,
ànd O2 acts as a Switching
MOSFET.
Introduction to VLSI |1.13|

+VbD

ViN Q2 Vo

Vo Logic 0 (LOW) OFF Logic 1 (HIGH)

Logic 1 (HIGH) ON Logic 0 (LOW)

VIN

(a) Schematic diagram (b) Truth table

Fig 1.8 NMOS inverter

The gate is always connected to the supply +VpD, the MOSFET Q; is always
ON. So, the internal resistance of Q1 acts as the
load resistance R.
Compared to both MOSFETs, Q, is designed to have more resistance than Q2.
(2) NMOS NAND Gate
+Vop

B Q3 Vo
Vo
OFF OFF 1 (HIGH)
Qg 1
OFF ON 1(HIGH)

1 0 ON OFF 1
(HIGH)
ON ON 0(LOW)

(a) Schematic diagram (b) Truth table

Fig 1.9 2-input NMOS NAND gate
1.14| VLSI and Chip Design

Fig 1.9 shows a 2-input NMOS NND gate. It consists of threa

N-channel MOSFETs, in which Q1 acts as the load resistance, whereas
O

are given to
and Q3 act as the switching MOSFETs. The two inputs A andB
MOSFETQ and Q3 respectively.

(i) When both inputs Aand B are given LOW input, both the MOSFET:
are turned OFF, which makes the output Vo as HIGH.

(i) When either

A or B is LOW, the MOSFET with low input will be
turned OFF, thus making the output to be HIGH.
turn ON the
If HIGH input is given to both the input terminals, it will
VpD
MOSFETs Q2 and Q3.Therefore, the current due to the supply voltage
will flow towards the ground making the output as LOW.

(3) NMOS NOR Gate

+Vpp

A B Q2 Q3 Vo
Q4
0 OFF OFF 1 (HIGH)
1 OFF ON 0 (LOW)
Vo 1 ON OFF 0 (LOW)
1 1 ON ON 0 (LOW)

A B

(a) Schematic diagram (6) Truth table

Fig 1.10 2-input NMOS NOR gate

The Fig 1.10 shows the circuit of the 2-input NMOS NOR
gate. It has

3 N-channel MOSFETs, in which Q, ácts as the load resistance, MOSFETs 2

and Q3 act as switching devices.

If any of the input, either A or B is given HIGH input, then the correspondins
MOSFET with HIGH input will turn ON making the output to be LOW.
Similarly, if both the inputs are HIGH, it will urn ON both the MOSPE
which will make the output to be LOW.
Introduction to VLSI |1.15|

1,3.3 PMOS Logic Families

Thedigital logic family can be built with P-channel MOSFETs and those circuits
are known as PMOS logic circuits. The operation of PMOS is similar to the
NMOS circuits, except that the mode of conduction is different.

For a P-channel M0SFET, a negative voltage is to be given at the gate terminal to

create a channel. Thus negative voltage (LOW voltage) is enough to turn ON the
PMOS devices.

1.3.4 CMOS Logic Families

CMOS (Complementary MOS) logic family uses both N-channel and P-channel
MOSFET devices. CMOS has greater complexity than PMOS and NMOS.
However, the speed of operation is high and power dissipation is less in CMOS.
CMOS also has more fan-out and better noise nargin.

(1) CMOS Inverter (or) NOT Gate

Fig 1.11 shows the symbol and schematic diagram for a CMOS inverter (or)
NOT gate by using one nMOS transistor and one pMOS transistor.

Vpo

-Y
A
oY A =Ã

GND
(a) Symbol (b) Schematic

Fig 1.11 CMOS inverter (NOT gate)

The drain of pMOS transistor is connected to supply voltage Vpp and the
source of the nMOS is connected to the ground (GND).
 VLSI and Chip Design
1.16|

OFF and pMOS transistor is

When an input A is 0, the nMOS transistor is
1 as it is connected to VpD but not to
ON. Thus, an output Y is pulled to
GND.
an output
an input A is '1,the pMOS transistor is OFF and
Similarly, when
to This is summarized in Truth Table 1.1.
Y is pulled down 0.
Input Output

Y=A
1

Table 1.1 CMOS Inverter trutlh table

(2Two Input NAND Gate

the two inputs NAND gate, which consists of two series
Fig 1.12 shows
output Y and GND and two parallel pMOS
nMOS transistors between
voltage Vpp.
transistors between output Y and supply
VpD

Y
Y =A•B

GNDs
(a) Symbol (b) Schematict L;
eit iC 34.3
Fig 1.12 Two input NAND gate
Introduction to VLSI 1.17

If either an input A (or) B is 0', one of the nMOS transistor will be OFF that
breaks the path between output Y and GND. At the same time atleast one
of
pMOS transistor is ON, making a path from Y to VpD. Therefore, an output
wili be 1'.

If both the inputs are 1', both nMOS transistors will be ON and both pMOS
willbe OFF, hence an output will be '0°. Truth table
of two input NANDgate
is shown in the Table 1.2.

Input Transistors Output

A B nMOS pMOS Y=A.B
OFF ON 1

1 OFF ON 1

1
OFF ON
1 1
ON OFF

Table l.2 Two input NAND gate truth table

VoD

Y= A.B.C
A

Fig 1.13 3-input NAND gate schenaticdiagram

1.18 VLSI and Chip
Desig

(3} Two Input NOR Gate

VDD

B
+
Y =A+ B
= Y=A B

(a) Schematic (b) Symbol

Fig 1.14 Tivo input NOR gate

The two input CMOS NOR gate is shown in Fig 1.14. The nMOS transistors
are in parallel to pull an output low when any of an input is high. The pMOS
are low as
transistors are in series to pull an output high when both inputs
shown in truth table 1.3.

Input Output

A B Y=A +B
1
0 0

0 1 0

0 0

Table 1.3 NOR gate truth table

Introduction to VLSI |1.19

VDD

Y=A+B+C

GND

Fig 1.15 3-input NOR gate schematicdiagram

(4) CMOS LogicGates: Combinational Logic
The inverter and NAND gates are examples of static CMOS logic
gates,which is also called as conplementary CMOS gates.

In general, a static CMOS gate has an nMOS pull-down netyvork to connect

an output to 0 and pMOS pull-upnetwork to connect an output to that is,
l
VpD.

Fig 1.16 show a networksthat are arranged one is ON and the other OFF for
any input pattern. The pull-up and pull-down networks in the inverter with
each consist of a single transistor.

In general, when we join a pull-up network and pull-down network to form a

logic gate which is shown in Fig 1.16. The possible levels at the output of the
logic gate is shown in table 1.4.

When both pull-up and pull-down are OFF, then,t enne output state is impedance
(or) floating Z. This logic is very important in multiplexers, memory element,
and trisate bus drivers.
20
VLSIand ChipDesio

VoD

pMOS
Pull-up
Network
Inputs
Output

nMOS
Pull-down
Network

Gnd

Fig 1.16 General logic gate using pull-up and pull-down networks

Pull-up OFF Pull-up ON

Pull-down OFF Z
Pull-down ON 0 Crowbarred (X)

Table 1.4 Output states of CMOS logic gates

The crowbarred (or contention) X level exists when
both pull-up and pull
down are simulatneously turned ON.Contention between
the two networks
results in an indeterminate output level and
dissipates static power. It is
usually an' unwanted condition.
(i) Construction of PUN and PDN
The PUN network consists of pMOS
transistors and the PDN consist of
nMOS transistors. The main reason is
nMOS transistors produce strong
zeros" and pMOS transistors generates "strong
one".
By using combinations of these constructions,
CMOS combinational gates can
be constructed.

A transistor can be assumed as a switch controlled

by its gate signal. A nMOS
switch is ON when the controlling signal is
HIGH and is OFF when the
controlling signal is LOW.
sign
ntroduction to VLSI
1.21

A pMOS is an inverse switch ON when

the controlling signal is LOW and is
OFF when the controlling signal is HIGH.
(a)nMOS Transistors in Series
Connections: AND Gate Operation
nMOS transistors are connected in series
which represents an AND function.
With all the inputs HIGH, the series
combination conducts and the value at
one end of the chain is
transferred to another end.

X X

1
! 1

Y
eisYetaitse
OFF OFF OFF ON

Input X Output
A
Y=A·B
B

bull
1
orks

t is 0 0
1
(X=Y)
Fig 1.17 Series connections of nMOS transistors
(b) nMOSTransistors in Parallel
Connections: OR Gate Operation
of
ng Input X Output
A B Y= A+B

-an 0 0
0 1

S 1
1
 VLSIand Chip Design
1.22
X
X

1
0
-
Y ON
ON ON
OFF

Fig 1.18 Parallel connections

of nMOStransistors
represents an OR
Similarly nMOS transistors connected in parallel normally
if
output and input terminal
function. A conducting path exists between the
atleast one of the inputs is HIGH.
(c) pMOS Transistors in Series Connections: NOR Gate Operation
X X
X X

0 4
A

1
0
B

Y Y Y Y
Y
ON OFF OFF OFF

InputX inoOutput
B Y=A+B
0 0 1

1
0
1.
1 1

Fig 1.19 Series connections ofpMOS transistors

'and
A areLOW
series connection of pMOS transistors conducts if both inputs
representing a NOR function.
Introduction to VLSI |1.23|

A OMOS Transistorsin ParallelConnections: NAND Gate Operation

X X X X X

A B o fo of

Y Y Y
ON ON ON OFF

Input X Output
A B Y= A-B
1

-
1

Fig 1.20 Parallel connections of pMOS transistors

A parallel connection of pMOS transistors is shown in Fig 1.20. A conducting
path exists between the output and input terminal if at least one the
of input is
HIGH and a
representing NAND function.
(5) Compound Gates
Compound gates are used jor performing a more complex logic function in
a
single stage of logic and it is formed by using a combination of series and
parallel switch structures.

a Example of Compound Gates

A function Y = (A· B)+ (C D) is a good example of
compound gate. This
is called AND -AND -OR-INVERT- 22 (AOI 22), because
it performs the
a
NOR function of pair of 2-input ANDs.

Fig 1.21shows the implementation of function Y = (A- B)+ (C•

D). In
Fig 1.21 (a), for the nMOS pull-down network, the
AND expression (A.B)
and (C.D)may be implemented by a series connections switches.
of
 VLSI andChip Design

In Fig 1.21 (b), now for the OR function requires the parallel connections
switches ((A-B) + (CD)).
combination
In Figs 1.21 (c & d), for the pMOS pull-up network, the parallel
and D. The
C

of A andB is placed in series with the parallel combination of

are shown in Figures 1.21 (e & f).
full schematic diagram and symbol

(a) (b)

(d)

A B' Y

Y D

(e)
Symbol
Schematic

Fig 1.21 CMOS compound gate for function.

 Iatroductiön to VLT
1.25
A
TWO MARKS QUESTIONS AND ANSWERS

What do you mean by VLSI?

Very- Large- Scale Integration (VLSI)
is the process creating an Integrated
of
Circuit([C) by combining thousands
of transistors into a single chip.
2. Write the nee J
1.ihg ibt vlasti382'tizictÁncw.20n 1n a
The need of ICs are, Di (
To increase the number
of components in a chip,
Toreduce the size of the device, and
To increase the device speed.
3. What are the different generations of integrated circuits?
The different generations of integrated circuits are,
SSI (Small Scale Integration).
MSI (Medium Scale Integration).
LSI (Large Scale Integration).
VLSI (Very Large Scale Integration).
4. Write the advantages ofVLSI.

VLSI has many advantages are,

i) Reduces the size of circuits (compactness).
(ii) Reduces the effective cost of the devices (low cost).

(ii) Increases the operating speed of circuits due to the absence of parasitic
capacitance effect.
(iv) Requires less power than disc«eie components.
(v) Higher reliability.
5. List the disadvantages of VLSI.
The disadvantages of VLSIare,
(i) .Some complex IC's may be costly. We cannot repair an individual
Component inside an IC which are to0 small.
 VLSI and Chip Design
26
more than 10 wat
does not exceed
(i) The power rating for most of the IC's
power IC's.
Thus, it is not possible to manufacture high
components like transformers and inductors cannot be integrated int
(ii) Some
to semiconductor pins.
an IC. They have to be connected externally the
not possible.
(iv) High grade p-n-p assembly is
handled (or) exposed to excessive
(v) An IC will not work properly if wrongly
heat.
6. Mention the applications of VLSI.
are widely used in various branches of Engineering
In today's world VLSI chips
like:

(i Voice and data communication networks.

(i) Digital Signal Processing (DSP).
(iüi) Computers.

(iv) Commercial electronics.

(v) Automobiles.
(vi) Medicine and many more.
7. Name the types of
MOSFET.

The main types of MOSFET which is based on the charge carriers namely,

() n-channel MOSFET (or) nMOS transistor (or) NMOS transistor.

(i) p- channel MOSFET (or) pMOS transistor (or) PMOS transistor.

If the MOSFET channel consists of electrons then it is called as nMOS transistor,
and if MOSFET consists of holes, then it is called as pMOS transistor.
8. Name the two modes ofMOSFET.

In MOSFET, the two types of operation modes corresponding to whether

transistor is in ON state (or) OFF state at zero gate-source voltage (VGS0)

) Enhancement mode, and

(ü) Depletion mode.
 Introduction to VLSI
1.27|
o Draw the symbol of nMOS and pMOS
transistor.hka 135kts
D ptf Dei4

S
(a) pMOS it (6)
nMOS:25i:
Symbols of MOSFET
10. Defne enhancement mode ofMOSFET.
The Enhancement mode MOSFET is
equivalent to a "normally open" switch.
These devices are OFF at zero gate-source
voltage for both nMOS and pMOS.
These types of transistors require Vas to switch
ON the device.
I1. What is a
depletion mode in MOSFET?
The depletion mode MOSFET transistors are
generally “switched ON" at zero
gate-source voltage (VGs= 0) and is
it equivalent to a "normally closed" switch
n
and requires Vas to switch OFF the device.
If the gate voltage increases in
positive, then the channel width increases.
12. List the applications of MOSFET.

The main applications of MOSFET are as follows:

1) MOSFETs are used in digital integrated
circuits, such as microprocessors.
(ii) Used in calculators.
(iii)Used in memories and in logic CMOS
gates.)
(iv) Used as analog switches.
ith
(v) Used as amplifiers.
(vi) Used in the applications of power,
electronics and switch mode power
supplies.
(vii) MOSFETS are used as
oscillators in radio systems.
(vii) Used in automobile sound systems
and in sound reinforcement systems.
 VLSI and Chip Design

Compare enhancement and depletion modes.

Depletion Mode
S.No Enhancement Mode
1. The Enhancement mode MOSFET The depletion mode MOSFET
is equivalent to a "normally open'" transistorsare generally "switched
switch.
ON" at zero gate-source voltage
These devices are OFF at zero (VGs =0 ) and it is equivalent to
a

gate-source voltage for both "normally closed" switch

NMOS and PMOS.
2.
Channel exits even with zero
No conducting channel between voltage from gate to source. In
a
source and drain unless a positive order to control the channel
voltage is applied. negative voltage is applied to the
gate.
In the symbol, the continuous
3. In the symbol, the broken line is
connected between the source and thick line connected between the
drain which represents the drain and the source terminal
enhancement mode type. represents the depletion type.

The conductivity of the channel in The conductivity of the channel in

4.
enhancement MOSFETs is high. depletion MOSFETs is less
compared to the enhancement type
of MOSFETs.

What is CMOS?
Oxide Semiconductor". It
The term CMOS stands for "Complemnentary Metal
on the same chip([C).
requires both nMOS and pMOS transistors to be built

Write the applications of CMOS.

The CMOS technology has been used for the following designs:
(i). Microprocessors.
(i). Microcontrollers chips.
(111). Computer memories like RAM, ROM and Flash memory chip designt
Introduction to VLSI |1.29|

(iv). Alldigital logic circuits.

(V). Application Specific Integrated Circuits (ASICs).sg sgoh st
16.Give the comparisons between NMOS and PMOS.
Sr.
PARAMETERS NMOS PMOS
No

1. Fabrication NMOS is built with n- | PMOS is built with

type source and drainp-type source and drain
and a p-type substrate. and a n-type substrate.

2. Majority Carriers Electrons. Holes.

3. Applied Voltage When a high positive When a low negative

voltage is applied to the voltage is applied to the
gate, NMOS will gate, NMOS will not
conduct, while PMOS conduct and PMOS will
will not conduct.
4.Operating Speed NMOS are considered toPMOS device is slower
be faster than PMOS, than NMOS.
since the carriers in
NMOS, which are
electrons can travel twice
as fast as holes.

17. Mention the advantages of CMOS.

The main advantages of CMOS over NMOS and BIPOLAR technology are:
(). Low static power dissipation.
(ii). This allows integrating more CMOS gates on an IC than bipolar
technology, resulting in much better performance.
(i). This technology makes use of both 'p' channel and
n' channel
semiconductor devices.
(iv). High noise margin.
(v). High packing density.
(vi). Bidirectional capability, that is, drain and source are
interchangeable.
 VLSI and
Name the types ofMOSFET ChipDesign
logic family.
All the logic gates that are
built with MOSFET devices
logic family and it can be classified will come under MOs

into three categories:

() NMOS logic family - Built with N-channel MOSFET.
(ii) PMOS logic family -Built with P-channel MOSFET.
(iii) CMOS logic family- Built with both N-channel and P-channel MOSFET.
.
Draw the symbol of nMOS inyerter.i

+VpD

Q.

VIN

Draw the symbol and schematic diagram of CMOS nverter.. rsy sth aaitat

A
-Y E

GND

(b)
Schematicg
(a) Symbol
Introduction to VLSI 1.31

1.5 REVIEW QUESTIONS

1 Discuss in.detail about the working operation of MOSFET and its mode of
operation with neat sketches.
2. Explain n detail about NMOS logic families with neat diagrams.

3. Explain in detail about CMOS logic with examples.

4. Discuss in detail aboutcompound gates with anexample.
 s
UNIT-1
Chapter 2
opMOS TRANSISTOR THEORY

2.1 LONG-CHANNEL (IDEAL) I-V CHARACTERISTICS

MOS transistors have normally three region operations:
of
) Cutoff (or) sub threshold region,
(ii) Linear (or) non saturation region, and
(ii) Saturation region.

2.1.1 Average Gate to Channel Voltage

a Long-ChannelModel
The long-channel, ideal, first-order (or) Shockley model relates the current
and
voltage (1-V)for a nMOS transistor in each of the three operating regions. This
model assumes that the channel length is long enough and the lateral electric
field (the field between source and drain) is relatively low, which is no longer in
the case of nanometer devices.

Gate

Source Drain

V Channel
V

nt n

Vds
p-type BodyfEiBpe J:is

Fig 2.1 Average gate to channel voltage

 VLSI and Chip Design
|2.2
transisto
assumes that the current through an OFF
The long-channel model attracts carriers (electrone
turns ON (Vg> V), the gate
is '0°, When a transistor
toform a channel.
source to drain at a rate proportional tothe electri
the
The electrons drift from can be expressed as,
channel
Thus, the charge in the
field between these regions.
...(1)
Qo = C,lV-)
channel.
Cg Capacitance of the gate to the
where,
charge to the channel beyon
Amount of voltage attracting
Ve-V)-
from p to n.
the minimum required to invert
grounded. If th
gate voltage is referenced to the channel, which is not
The
average is given as,
source is at V, and the drain is at Vd. Then the
...
(2)
2

Source-drain voltage, Vis = V-V,

(3)

equation (2), we get

By substituting equation (3) in
V,+VtV,
2

.. (4)
2
are defined as,
The mean difference between the gate and channel potentials

=
.(5)

By substituting equation (4) in equation (5), we get

MOS Transistor Theory 2.3

2
-v,-V)

gc gs
2

2.1.2 Transistor Dimensions

p-type Body

SiO, Gate Oxide

(insulator, Eox =3.9Eo)

Fig 2.2 Transistor dimensions

o Now, we can model the gate as a parallel plate capacitor
with capacitance
proportional to an area over thickness. If the gate has length L and width W and
the oxide thickness is tor which are shown in Fig 2.2. Then the gate
capacitance
is expressed as,

WL
C = kox E

WL
= Co WL ...(7)
Iox

where 8.85 x 10-1 F/cm= Permittivity of free space,

kox Permittivity of Si02, and

Eox
Cox =Capacitance per unit area of the gate oxide.
Tox
 VLSI and Chip Design
|2.4|

2.1.3 Mobility
an average velocity v which i
Each carrier in the channel is accelerated to
to lateral electric field
called as carrier drift velocity and it is proportional the
i.e. the field between source and drain.

where, A- Carrier mobility

difference between the drain and
The lateral electric field Eat is the voltage
source, ds which is divided by thechannel length.

Eta! L
(9)

the
The long-channel model assumes that carrier mobility is independent of
a
applied fields. The velocity saturation means that the carriers approaches
maximum velocity vsot when high fields are applied.

The time required for carriers to cross the channel is the channel length which
is divided by the carrier velocity.
... (10)
I, = L

The current between source and drain, la, is the total amount of charge in the

channel which is divided by the time required to cross.

Lcha
.. (11)

By substituting equations (1), (7) and (10) in equation (11), we get

CV-)
Substitute equations (7) and (8) in above equation,
Ca
WL(-,)
 MOS Transistor Theory 2.5

Now, substitute equation (9) in above equation, we get

Substitute equations (6) in above equation, we get

as = H,
CaV-V,-Va/2)Va... (12a)

Equation (12a) alsO represented as,

= B(VG-Vá! 2) Vt .. (12b)
1
W
where, B= H Cox & Vor= V-V,

2.1.4 Operations
(1) Cutoff Region
o In this region, when Vgs< V the transistor is OFF, thus no channel is formed
between the source and drain with almost zero current i.e., Iás =0.
... (13)

(2) Linear Region

In linear region, when Vgs > V, the transistor is ON, but Vas is relatively small
and gate attracts charge carrier to form a channel. lás is the current flow
between source and drain.
When Vá << VaT, Iis increases almost linearly with Vás and it isexpressed as,
 VLSIand Chip Design
2.6
... (14a)

can be also represented as,

o Equation (14a) ... (14b)
V
B(VGr-Va/2)

(3) Saturation Region pinched off. Beyond

when Vás >Vdsst the channel gets
In the saturation region, increasing
drain saturation voltage (Vasat), thus
the
this point it is called as,
no further effect on the current and it is given
drain voltage which has
... (15)
,-,}va 2
source to drain
(14b) and (15), it summarizes the
Based on equations (13),
current Ios in the three regions:
Cutoff

Linear (16)
V<Vd sat

Saturation

- 0.5
I4s (A)
Vgs
-1

1501 Vgs = 1.0

Vos -0.6 - 50
100
Vos =0.8
Vos -0.8
-
504
Vos -1.0 100

Vos =0.6

- 150
Vos
0.5
los (A)

(a) nMOS (b) pMOS

Fig2.3 I-Vcharacteristics of
MOSFET
MOS Transistor Theory |2.7

Fig 2.3(a) shows the I-V characteristics for the transistor. According to the
first-order model, the current is zero for gate voltages below V;.
For higher gate voltages, current lis increases linearly with Vas. As Vas

reaches the saturation point, i.e., Vaso VcT ,current rolls off andeventually
becomes independent of
of Vps when the transistor is saturated.
pMOS transistors behave in the same way, but with the signs of all voltages
and currents reversed which is shown in Fig 2.3(b).
The mobilityof holes in silicon is typically lower than that of electrons. This
means that pMOS transistors provide less current than nMOS transistors of
comparable size and hence they are slower.

2.2 NON-IDEAL I-VCHARACTERISTICS (OR) NON-IDEAL

I-V EFFECTS

2.2.1 Introduction
4 The long-channel LV model equations neglects many effects that are important
to devices with channellengths below 1 micron. Some of these effects includes:

(i) Mobility degradation and velocity saturation,

(ii) Channel Length Modulation,
(ii) Threshold Voltage Effects,
(iv) Leakage,
(V) Temperature Dependence, and
(vi) Geometry Dependence.

2.2.2 Mobility-Degradation and Velocity Saturation

& The carrier drift velocity is proportional to the lateral electric field between
Source and drain.
... (1)
vc Eat
where, constant of proportionality ,-
.U=H, Eat
Carrier mobility.
 VLSland Chip Design

2.8
voltage difference between drain and source
betw
Elat is the
The lateral electric field
the channel length. sit lseat it3-21t
..
by
Vps which is divided
tsi (2)
olsng

assumes that the carrier mobility is

independent of the
The long-channel model
down
is a good approximation for low fields, but breaks
applied fields. This
are applied.
when strong lateral or vertical fields
means that the cárriers approaches maximum velocity
a
The velocty saturation
Uag when high fields are applied.

a Mobile Degradation carriers to the edge of the

A high voltage at the gate of the transistor attracts the
channel, causing collisions with the oxide interface that slow the carriers. This is
called mobility degradation.

4 The mobility degradation can be modeled by replacing 4, with smaller that is

a function of
Ves.h i

uif s40 cm/V.s

Hef-n V.+V, \1.85 : (3a)
gs
1+
0.54 ox
nm
185 cm²/V.s
Hef-p ... (3b)
|+1.5 V,|
1+ V

0.338
nm 'ox
Fig 2,4 shows measured data for carrier velocity as a function
of the electric fielo
E, between the drain and source. 3eiav krE rioil6L
At low fields, the velocity increases linearly with
the electric field. The slope
the mobility, ef
he fields above a critical level (E) that is the velocity leve
are Usat•
MOS Transistor Theory
2.9
i i1
w10° cm/s for electrons. i0)2*Fi

'sal-p
8x10° cmls for holes.

Vsat-n
Electrons
(cm/s)

107
v
Velocity APeff-n Holes

Measured
Carrier 106
Curve Fit

10

Elat (V/cm)

Fig 2.4 Carrier velocity Vs electric field at 300K

can be approximated reasonably as
4 Based on the above Fig 2.4, the velocity
follows:

E<E, ... (4)

1+ E

sa!
The critical electric fieldis expressed as,

20sat •..5)

a Critical Voltage:
The critical voltage Ve is the arain-source vottage at which the. critical electric
wh
field is reached.
VeE, L

where, L is the channel length between source and drain.

2.10| VISI and Chip Design

If the transistor is completely velocity saturated (Vás =Vása), then the saturation
current is expressed as,
... (7)
V>V,
dependent on voltage in
* In an above expression, the drain current is quadratically
saturated.
the long-channel regime and linearly dependent when velocity is fully

a a-Power Law Model

For moderate supply voltages, transistors operate in region where:
Velocity no longer increases linearly with field, and
- Not completely saturated.

This behaviour is approximated by using -power law model. a is called the

velocity modulation index which is determined by the curve fitting measured

by 1-V data.

The model is based on three parameters that can be determined empirically

from a curve fit of I-Vcharacteristics: a, B, P, and P,:
(0 Cutoff

Linear ... (8)

dsat

Ldsat Saturation

where,

GT

Vdat= P. v
GT:

Fig 2.5 compares the a power law model against simulated results, usinE
= matches
fit is poor
a
1.3. The at low Vat, but the current at
V= Vpp

simulation fairly well across the full range of Vgs.

MOS Transistor Theory 2.11

Simulated
C - pOwer law
Ids (A)
800 Vas = 1.0

600
Vie =0.8
400
Vas =0.6
200
Vas = 0.4
Vds
*g9! :0: 0.20.4s0.60.81.
Fig 2.5 Comparison of power law modelwith simulated transistor belhavior
a

2,2.3 Channel' Length Modulation (CLM)

a Definition of CLM
The current between the drain and source terminals is constant and independent
of an applied voltage over the terminals. The effective lengthof the conductive
channel is actually modulated by the applied Vds increasing Vds causes the
2A
depletion at the drain junction togrow, also reducing the length of the effective.

channel.

If a transistor is in saturation, ideally lás is independent of Vds, this makes

transistor a perfect current source.

Th p-n junction between the drain and body forms a depletion region with a

l width La that gets increases with Vdbs as shown in Fig 2.6. This depletion region
effectively shortens the channel length to:,
 VLSI and Chip Design
.12|

Leff

Vgs
.

Vdb

p-type body

b
Depletion
region

Fig 2.6 Depletion region shortens effective channel length

Assume, that the source voltage is close to the body voltage (V s V).
Increasing Va decreases an effective channel length. Thus the shorter channel
length results in, higher current; thus, la increases with Vá in saturation and it is
expressed as,

L= ... (10)
2

Where, V isthe early voltage, which is proportional

to thechannel length. As
the channel length gets shorter, an effect
of the channel length modulation
becomes more important. CLM is very important
to analog designers because it
reduces the gain of amplifiers.

2.2.4 Threshold Voltage Effects

For all previous discussion, we have
treated the tlreshold voltage as a
constanl.
If V increases with the source voltage,
then decreases with the body voltag
decreases with the drain voltage,
and increases with channel length.
This sectuou
models each of these effects.
 MOS Transistor Theory 2.13|

(1) Body Effect

A transistor is to be considered as a three-terminal device with gate, source,

and drain. However, the body is an implicit fourth terminal.

a Definition
The variation of the threshold voltage due to source to substrate voltage Vsb, is
referred to as body effect (or) substrate-bias effect.

When a voltage sb is applied between the source and body, it increases the
amount of charge required to invert the channel. Hence, it increases the
threshold voltage and it can be modeled as,
.. (11)

nel
, = 2 U, In ...
(12a)

it is ...
Cox
(12b)
Eox

where,
Vio - Threshold voltage when the source is at the body potential.

As
,- Surface potential at threshold.

tion y- Body effect coefficient depends on gate oxide thickness and

ce
ubstrate doping.
it
– Doping level in the channel.
N
tox - Gate oxide thickness.

Eox Relative permittivity of gate oxide.

nt. E - Relative permittivity of silicon.
age,
tion
n, - Intrinsic electron concentration.
NA – Impurity concentration in substrate.
 VLSI and Chip Design
2.14|

(DIBL)
(2) Drain- Induced Barrier Lowering

a Definition
affects the threshold voltage.
Vá creates an electric field that
The drain voltage
n
as DIBL effect, especially in short-channel transistors.
This is called

DIBL can be modeled as,

=
... (13)
V, Vo-n Vs

where, is the DIBL coefficient.

DIBL increases the sub threshold leakage at high Vás.

(3) Short Channel Effect

The threshold voltage typically increases with respect to channel length. For

Small channel length L, where the source and drain depletion regions extend into
a significant portion of the channel and it is called as short channel effect (or)
V, rolloff.

2.2.5 Leakae
G D

Isub nt

jun

P-Substrate

°Body

Fig 2.7 Leakage current paths

o
Normally, when the transistots are OFF, currents.
they leak small amounts of
This leakage includes:
MOS Transistor Theory 2.15|

m Sub threshold
conduction between source and drain: subl.
It is caused by thermal emission of carriers over the potential barrier set by the
threshold.
(ii) Gate leakage fromthe gate to body: Igatel.
It is a quantum-mechanical effect caused by the tunneling
through an extremely
thin gate dielectric.
(iii) Junction leakage from the source to body and drain to body: ljunl
It is caused by a current through the p-n junction between the source/drain
diffusions and the body.
The leakage becomes an important design consideration in nanometer processes.

2.2.6 Temperature Dependence

Temperature plays a vital role in transistor characteristics. The carrier mobility
gets decreased with the temperature and it is approximated as,

-ku
u(T) *.. (14)

where, - Absolute temperature.

T, - Room temperature.

ke - Fitting parameter with a typical value of about 1.5.

sat
also decreases with temperature and dropping about 20 % from 300 to
400 K. The magnitude of the threshold voltage decreases nearly linearly with
temperature and it may be approximated as,

V,(T) = V,(T) -kpt (T-T,) ... (15)

where k... is typically about 1-2 mV/K.

The transistor ON current, lon at high Vpp decreases with temperature whereas
the OFF current increases. But the subthreshold leakage increases exponentially
with temperature.
 VLSI and Chip Design
2.16|

IonluA)
800

780

7604

740

7204

20 40 60 80 100
120s itsi0ast
Temperature (C)

Fig 2.8 lsat Vs temperature

2.2.7 Geometry Dependence

The layout designer draws the transistors width
and length as Wa and Ld, butthe
some factors Xw and XI. The effective
actual gate dimensions may be differ by
as follows:
length and width of the transistor calculated
.. (16a)
Lef = L+X,-2 Lp
... (16b)
Wef = W,+X-2 Wp

a
The source and drain tend to diffuse laterally into the gate by Lp that produces
shorter effective channel length that the carriers must transverse between the
source and drain. Similarly, Wp accounts for other effects that shrink the

transistor width.

2.3 CMOS DEVICES

2.3.1 Transmission Gates (TGs): Transmission Gate Logic (TGL)
Definition Transmission Gate (TG)
of

nMOS pass transistor passes a strong 0 and a weak1. pMOS pass transisto
passes a strong I and a weak 0. Combine this two in parallel to make a CMOS
which
pass gate(CMOS based switch) which will pass a strong 0
and a strong
as transmission gate. That pMOS and
is called is, in transmisison gates both
nMOS works simultaneously.
MOS Transistor Theory
2.17
A It is an analog gate similar to a relay that can
conduct in both directions (or)
block by a control signal with almost any
voltage potential.
CMOS transmission gate which uses nMOS
and pMOS tranistors as a voltage
controlled bilateral switch.Here, both the control
input(A) and its complement
are required by the transmission gate.

4 Fig 2.9 shows the CMOS transmission gate. Fig 2.9 (b & c) respectively
shows
the truth table ofTG and its symbol.

IN OUT
H H
B -

H L L

L X (don't z (High
care) Impedance)
A

(a) Schematic representation (b) Truth table

In/out o o In/out

(c) Symbol i

Fig 2.9 Transmisison gate

Fig 2.9(a) shows the CMOS transmission gate operates as a bidirectional switch
between the nodes B and C which is controlled by control voltage A.
 VLSI and Chip Design
2.18

If the control signal

A
is

() High:
are turned e ON and provide a low-resistance
Equal to Vpp, then both transistors
C.
current path between the nodes B and
(ii) Low:
will be an
transistors will be OFE, and the path between the nodes B and C
Both
high-impedance (Z) state.
open This condition is also called the
circuit.

ØAdvantages
The advantages of TGL are,
power reduction as compared to the
(i) TGL technique achieves 83%
conventional CMOS design.
to reduce complexity, leakage
(ii) TGL is used in combinational circuit design
current and leakage power.
(iii) Complex gates can be implemented using minimum number of transistors,
which also reduces parasitics.
(iv) The combination of both PMOS and NMOS in transmission
gate
arrangement avoids the problem of reduced noise margin, increase
Switching resitance and increased static power dissipation (caused by
increased threshold voltage), but requires that control and its complement
be available.

Disadvantages:
The disadvantages of transmission gates are:

() Time- skew problems can lead to short circuits.

(ii) Slower. speed.
(iii) Due to charge sharing problem, not more than 3TG can be connected in
cascade. After 3TG a buffer circuit is required.

a Applications of TG
The main applications of TGs are:

(i) Multiplexing element of path selector.

MOS Transistor Theory
2.19

(iü) A latch element

(ii) An analog switch.
(iv) Act as a voltage controlled resistor connecting the input
and output.
2,3.2 Multiplexers: Data Selectors
Multiplexers are widely used and have many applications. They are also
commonly available in a number of standard configurations in TTL and other
logic families.

Multiplexers are the most important components in CMOS memory elements and
data manipulation structures. A multiplexer selects an output from among the
several inputs based on the select signal.

(1) Four-Input (4:1) Multiplexer

I4 Output y
Inputs MUX

-Select
I3

S So

S1 So

Fig 2.10 4:1 multiplexer logic circuit

Fig 2.10 shows the most commonly used 4:l multiplexer, which uses 4 inputs
and produced one output. It is easy to construct and simple to implement the
logic.

Here. Si andSo are the select signals. Io, Ii, Ih and I; are the inputs and Y is
the output. If S, and So have defined logic states, output Y must always be
connected to one of Lo to I3.
 VLSI and Chip Design
.20|
can be expressed in
this 4:1 multiplexer
The output (or) logic function of
as,
terms of inputs and select signals

Y=h S, So +1,•S,S+,·S, S, +1,·S, S

1 multiplexer. The output may be written
o Table 2.1 shows the truth table of 4:
as,
Select lines Output
S S Y
0
1

I3
Table 2.1 Truthtable of
4:1 multiplexer

(b) Symbol

(a) Mutiplexer using NOT gates

Fig 2.11 4:1MUX

 MOS Transistor Theory 2.21|

So

So

S1

Y
S
-

So S1

So

Fig 2.12 4:lmultiplexer using transmission gates

(2) 2:1 Multiplexer
Ina 2-input, or 2:1 multiplexer, the inputs are Do and D and the select lines

are S and S. The input Do is selected when S=l and S=0 and the input D, is

· selected when S= 0
and S=1.
 VLSIand Chip Design
|2.22

ty
expression is given as Y = S-D, + S-D,. The truth table for
The logic
inputs MUX is shown in Table 2.2.
Select lines Output
Inputs
D
S Y
D,
1

X 0
1 1
X 1

0 X 0
1
X 1 0

Table 2.2 Tvo input MUX truth table

A compact two input multiplexer can be formed. by connecting two

transmission gates together, as shown in Fig 2.13 (a). The select and its
complement enable exactly one of the two transmission gates at any time. Th:

complementary select S is often not drawn in the symbol, as shown it

Fig 2.13(b).

Do

Do

D,

(a) Transmission Gate multiplexer

(b) Symbol*2!
a
Fig 2.13 2:1 MUXs
Large multiplexers can be built from multiple 2-input multiplexers.
practice, both inverting and calle!
non-inverting multiplexers are simply
multiplexers (or) muxes.
2.3.3 Sequential Circuits
Sequential circuits have memory: their outputs depend on both current and
previous inputs. We can now build sequential circuits such as latches and
fip-flops.
(1]Latches:
CLK
CLK
Q Q
DH1
CLK
CLK

CLK

(a) (b)

D
D-o Q

= 0
CLK= 1
eCLK

(c) (d)

CLK
CLK
D
D

(e) ()

Fig 2.14 CMOS positive -level sensitive D latch

A latch built from a 2-input multiplexer and two inverters is shown in

D

Fig 2.14 (a). The multiplexer can be built from a pair of transmission gates,
shown in Fig 2.14 (b), because the inverters are restoring.
 VLSI and Chip Design
24

output, 0. When CLK= 1, the latch

produces a complementary
This latch also CLK falls to 0,
flows through to (Fig 2.14 (©)). When
1S transparent and D
the latch becomes opaque.
established (Fig 2.14 (d) to hold
feedback path around the inverter pair is
A
indefinitely.
the current state of
state of the
known as a level-sensitive latch because the
The D latch is also 2.14(e).
dependent on the level of
the clock signal, as shown in Fig
output is
in
shown is a positive-level-sensitive latch and its symbol shown
The latch
Fig 2.14().
becomes
connections to the multiplexer, the latch
o By inverting the control
negative-level-sensitive.

(2) Flip-Flops

By combining the two level-sensitive latches such as one is negative-sensitive

is positive-sensitive, we can construct the edge-triggered flip
and another one
flop shown in Fig 2.15(a) and the it can be built from the transmission gates
are shown in Fig 2.15 (b). The first latclh stage is called the master and the

second is called the slave.

When CLK is low, then the master negative-level-sensitive latch output (QM)
follows the D input while the slave positive-level-sensitive latch holds the
previous value (Fig 2.16(a).

When the clock transitions from 0 to the master latch becomes opaque and
1,

Jatch becomes
holds the D value at the time of the clock transition. The slave
to the output of the slave
transparent, passing the stored master Value (QM)
latch ().
affecting the output because the master is
from
The D input is blocked transitions from
input (Fig 2.16(b)). When the clock
disconnected from the D
value and the master starts sampling the input
1to 0, the slave latch holds
its

again.
MOS Transistor Theory 2.25

CLK

CLK

QM
D
(a)

CLK CLK

QM

CLK CLK CLK

CLK

(b) CLK CLK

Fig 2.15 CMOS positive-edge triggered Dflip-flop

OM
D-t

CLK = 0
(a)

QM
Do

CLK = 1
(b)

Fig 2.16 Operations ofD latch

The flip-flop copies D to on the rising edge of the clock, as shown in

Fig 2.17 (a). Thus, this device is called positive-edge triggered flip-flop
a

or master-slave flip-flop. Fig

which is also called a D flip-flop, D register,
D flip-flop.i
2.17 (b)shows the circuit symbol for the
 VLSI and Chip Design

2.26

CLK CLK

(b)
(a)
symbol ofD flip-flop
Fig 2.17Clock signal and

a Register:
flip-flops which sharing a common clock input is called a
A collection of D
register.

2.4 SOLVED PROBLEM

Problem-1
For the oxide thickness tox = 500 A', find the capacitance per unit area Cor
Solution:
tox = 500
A'= 500x10 = 0.5x 10 Cm

E, isthe permittivity (a dielectric constant) of Si0,=0.345 pF/cm

The gate-oxide capacitance per unit area is expressed as

0.345x10-12
Car =
tox 0.5x10-5

0.69 x 10 F/om?

Cox = 69 nF/cm?

Problem-2

, &p devices are

Typical values for n as follows:
= S00
cn'V:s, H, = 180 cVs,
MOS Transistor Theory
2.27
E
=3.9E, =3.9x 8.85 x10 =0.345 pFlcmn
lox = 200 4'

Find the ß values.

Solution:

() For n-device, B=nEor

500 x 0.345 x10-2 W

0.2x105 L

172.5x10-7 =
86.25.
B= 0.2

= 180× 0.345 x10-2 IW

(ii) For p-device, B
0.2x10-S L

62.1x107 =
B = 31.05u4/ V?
0.2 L

Problem-3
Consider an nMOS transistor in a 65 nm process with a mininum dravwn
channel length off 50nn, the gate oxide thickness is I0.5 A', the high-field
mobility of electrons to be 80 cm'/ Vs. Find tlhe value of B
using the long

channel model.
O Solution:

lox

80x 3.9x8.85 x 10-14

10.5x 10

2761.2 x 10-14
10.5x10- (L)
 VLSI and Chip Design
2.28|

W uA/V2
263
B=
Problem-4
ON nMOS and pMOS transistors using
voltage for fully
Find the critical
following parameters. L = 50 nm.
36 cm²/V and
=1.0)=
Hef-n„Vs
=1.0)= 96 cm' IV, ur-(Vos

Solution: cm
L= 50 nm
=
50x 10 n=5x 10°
w 10'cm/s for electrons.
Already we know, Dsat-n

8x 10° cm/s for holes.

Dyat-p

() For nMOS,
20gat 2x107
where the electric field E. = 96
Heff

2x10?
Ve-n = -x5x10-6
Then, 96

200 =
1:04 V
96

(i) ForpMOS,
2x8x10
V- -x5x10-6
36

80 =
Ve-p 2.22
36

Problem-5
nm process with a nominal threshold
Consider the nMOS transistor in a 65
8 x 10 cm. Thebody is tied to ground
voltage of0.3 V anda doping level of
cm, relati
with a
substratecontact. Gate oxide thickness (tar)=10.5 x 10
MOS Transistor Theory
|2.29

permittivity of silicon () = I1.7, impurity

concentration in substrate
N) = 8 X I0/cm. How much does
the threslhold change at room
temperature if the source is at 0.6 V
instead of 0.
O Solution:

At room temperature (300 = kT

K), the thermal voltage, u,

where, Boltzmann's constant (k) = 138 x 10 J/°K

Electron charge (g) = 1.6 x 109

= 11.7 E0 = 11.7 x 8.85 x 10-14 = 103.5 x 10-14
Ei
Intrinsic electron concentration (N,) = 1.45 x 10'°/l cm

1.38x10-23 x300
Then,
1.6x10-19

414x10-4 41.4x10-3
1.6 1.6

U, = 25.87 x 1026 mV

() Surface potential at threshold,

8x10!7"
= 2 (0.026)x ln
1.45x 10o

= 0.052 x ln (5.5 x 10')

= 0.052 x 17.82

. = 0.923 ~ 0.93 V
 VLSI and Chip Design
2.30

(ii): Body effect coefficient

Ox 24e,N4

10.5x10-8 V2x1.6x10-19 x103.5 x 10-l4 x 8x10!7

34.5x10-14
x
= 0.3 x 10°/3.2 x 10-l 828

= 0.3x 10 2649.6
~
0.1544 0.16
Y= 0.3 x 51.47x 10=
(iii) Change in threshold voltage,

0.3 +
0.16(0.93 +
0.6 -V 0.93 )

= 0.3+0.16 (1.24–0.96)

V= 0.3 +
0.0448 = 0.345 V

2.5 TWO MARKS QUESTIONS AND ANSWERS

1. What is long- channel model (or) Shockley model?
The long-channel, ideal, first-order (or) Shockley model relates the current and
voltage (1-V) for a nMOS transistor in each of the three operating regions. This
model assumes that the channel length is long enough and the lateral electric
field (the field between source and drain) is relatively low, which is no longer in
the case of nanometer devices.

2. Define carrier drift velocity.

Each carrier in the channel is accelerated to an average velocity which is called
as carrier drift velocity and it is proportional to the lateral electric field. i.e., the

field between source and drain.

 MOS Transistor Theory
2.31

where, - Carrier mobility.

3. What is lateral electric field?

The lateral electric field Elat is the voltage
difference between the drain and
source, Vds Which is
divided by the channel length.

Ea .Vs
4.
What is velocity saturation effect?
APRMAY-2018]
The velocity saturation mneans that the carriers approaches a
maximum velocity
Dgat when high fields are applied.

Define threshold voltage of

MOSFET. 4PRMAY -2019, APRMMAY-2020]
Thresholdvoltage is the voltage applied between gate and source of a MOSFET
that is needed to turn the device on for linear and saturation regions of operation.

6. Whatis mobile degradation?

A high voltage at the gate of the transistor attracts the carriers to the edge of the
channel, causing collisions with the oxide interface that slow the carriers.. This is
called mobility degradation.

7. Define critical voltage.

The critical voltage Ve is the drain-source voltage at which the critical electric
field is reached.
V = EL
where, L is the channel length between source and drain.
8. What is meantby channel length modulation in nMOS transistors?
APRMAY-2017)

State channel -length modulation. [MAY/JUNE -2016]

The current between the drain and source terminals is constant and independent
of an applied voltage over the terminals.
2.32 VLSI and Chip Design

modulated by the
The effective length of the conductive channel is actually
causes the depletion at the drain junction to grow, also
applied ds, increasing Va;
reducing the length of the effective channel.

equation for describing the channel length modulation effect in

9% Write down the
. [MAY/JUNE -2016]|
nMOS transistor

Assume, that the

source voltage is close to the body voltage
( V.
an effective. channel length. Thus the shorter channel
Increasing Vás decreases
Iás increases with Vás in saturation
and it is
higher current; thus,
length results in,
expressed as,

V
L=v1+
2

to the channel length.

Where, VA isthe early voltage, which is proportional

Ig.lWhat is body effect in MOSFETs? APR/MAY-2021]

(or)

Define body bias effect. [NOVDEC-2016/

The variation of the threshold voltage due to source to substrate voltage Vsb, is

referred to as body effect (or) substrate-bias effect.

When a voltage Vát is applied between the source and body, it increases the
amount of charge required to invert the channel. Hence, it increases the
threshold voltage and it can be modeled as,

V,=Vo+y, +Va-a)
where,

Vo-Threshold voltage when the source is at the body potential.

.- Surface potential at threshold.
Y - Body effect coefficient depends on gate oxide thickness and substrate
doping.
11. What is DIBL?
The drain voltage Vds Creates an electric field that affects the threshold voltage.
This is called as Drain-Induced Barrier Lowering (DIBL) effect, especially in
short-channel transistors. It can be modeled as,

V =Vo-nV.
where, is the DIBL coefficient.

13yhat is transmission gate? [APRMAY-2017]

nMOS pass transistor passes a strong 0 and a weak 1. pMOS pass transistor
passes a strong 1 and a weak 0. Combine this two in parallel to make a CMOS
pass gate(CMOS based switch) which willpassa strong 0 and a strong 1 which is
called as transmission gate. That is, intransmisison gates both pMOS and nMOS
works simultaneously.

13gDraw the symbol of transmission gate.

A

In /Out -o In/Out

14. State the advantages of trasmission gate. APRMAY-2017]

The advantages of TGL are,
() TGL technique achieves 83% power reduction as compared to the

conventional CMOS design.

() TGL is used in combinational circuit design to reduce complexity, leakage

current and leakage power.
(ii) Complex gates can be implemented using minimum number of transistors,
which also reduces parasitics.
 VLSI and ChipDesign
|2.34|
gate
both PMOS and NMOS in transmission'
(iv) The combination of
problem of reduced noise margin, increase
arrangement avoids the
increased static power dissipation (caused by
switching resistance and
but requires that control and its complement
increased threshold voltage),
be available.

of transSmission gates.
15. Mention the disadvantages
gates are:
The disadvantages of transmission
can lead to short circuits.
) Time- skew problems
(i) Slower speed.
can be connected in
problem, not more than 3TG
(iii) Due to charge sharing
cascade. After 3TG buffer circuit is required.

16. Write the applications of TGs.

(or)

What is the use transmission gates? APRMAY-2021]

of TGs are:
The main applications
(i) Multiplexing element of path selector.
(ii) A latch element

(i) An analog switch.

(iv) Act as a voltage controlled resistor connecting the input and output.

17. Draw the 2:1 Multiplexer using transmission gate.

Do

Do

(a) Transmission Gate multiplexer (b) Symbol

MOS Transistor Theory 2.35

18. Compare Registers and Latches. APRMAY-2018/

Latch is a circuit that can hold 1
bit of data and is asynchronous i.e. without a
clock.

Registers are combination of flip-flops (which are the same as latch but have a
clock pulse to trigger). Registers can hold 2" data (n bit of data) if it consists of
n
number of flip-flops.

Latch can hold 1 bit of data while registers hold multiple number of data based
on number of flip-flops which are in it.

2.6 REVIEW QUESTIONS

1. Discuss in detail about long channel J-V characteristics of CMOS transistor.
2 Brief aboutthe non-ideal I-V effects of aCMOS devices.
3. Explain in detail about channel length modulation.
4. Explain the significance of threshold voltage and body effect with their
equations.
5. Explain in detail about the body effect and its effect in MOS device.
[MAY/JUEN -2016

6. Explain the basic principle of transmission gate in CMOS design.

[NOVDEC-2017 & APRMAY-2018]

7. Explain in detail about design of multiplexers in CMOS using transmission

gates.
8. Tllustrate the circuit designs for basic latches, then build the flip-flops and
pulsed latches. [APRMAY-2021]
9. Sketclh the4:1 multiplexer using transmission gates.
NOVDEC-2020 & APRMAY-2021]
 UNIT -I
Chapter 3
MOSFET TRANSISTOR CHARACTERISTICS

3.1 DC TRANSFER CHARACTERISTICS:

STATICBEHAVIOR
3.1.1Introduction s

The DC transfer characteristics

ngei
relate the output voltage to
the input voltage,
assuming that an input votage changes
slowly so that internal capacitance can
charge (or) discharge fully.

Specific ranges of input and output voltages are

defined as valid O
and1 logic
levels.

3.42 static CMOS Inverter DC Characteristics

CMOS inyerters are the most widely used as
inverter in chip design. It can be
obtained by connecting pMOS and nMOS transistors
in series. CMOS operates
with very little power and operate at higher speed.
A static CMOS inverter is shown in Fig 3.1. Its DC
transfer function is actually
curve between Vout VS Vin.

The pMOS and nMOS transistors are connected by

their drain terminals. A
Supply.voltage Vnn is given at the pMOS source terminal and
GND is connected
at nMOS source terminal.

The input voltage is applied at the gate terminals of pMOS and an output
voltage
1s taken from the interconnected drain termninal.
3.2 VLSI and Chip Design

pMOS

D ldsp
Vout
Vin
D ldsn

nMOS

¿3ITZATJASAHO As 1i24AST TZ20M

OIVAHH8 Fig 3.1 A CMOS inverter

is threshold voltage of n-channel device and Vtp is threshold voltage of

Let Vn
summarizes the reltionship between
.3LR:p-channel. device. The following table. 3.1
a inverter.
voltages for the three rgions of operation of CMOS

Cutoff Linear Saturated

tn gsn
>V gsn
gsn

V,,>V,
V,<Vm V>V,m in
nMOS
dsn <V gsn dsn
> V osn V

Vou<V in tn out
V in -V
Ve>V gSptp il.
in DD in Vi <V+Vpp
pMOS
dsp Vtp Vdsp <V-Vmp
Out in-V Out in

Table 3.I
The source of nMOStransistor is grounded 1.e. gsn =
As the
V
and Vásn Vou
source of pMOS transistor is connected in
to Vpp that is,
onnected to VpD Vgsp
Vn-VpD and
YgspVin
Vdsp = Vout -VDD.
MOSFET Transistor Characteristics
|3.3
For the given Vin, Vout May be
found for considering the following assumptions:

(iü) Vp =-Vm
(i) ,p
& A
plot of ldsn and ldsp in terms of Vdsn and Vásn for various values of Vgsn and Vgsp
are shown in Fig 3.2.

Vgsn4
+Idsn
Vgsn3

Vgsn2
VoD -Vdsn Vgsnt

Vgspt +Vdsn VoD

Vgsp2
Vgsp3
-dsn
Vgsp4

Fig 3.2 Variations ofla Vs Vis

The CMOS inverter DC transfer characteristics (Vout Vs Vin) is shown in

Fig 3.3 with the possible operating points.

VoD
A B

Vout

D
+Vin
Vn Vop/2 VoD
Vpp - Vp l

Fig 3.3 CMOS inverter voltage transfer characteristics

3.4| VLSI and Chip Desig,

the CMOS inverter is divided into five regions that indicated or

The operation of
is OFF thus, the pMOS transistor pull
Fig 3.3. In region A, the nMOS transistor
the output to VDD.
down. I
nMOS transistor starts to turn ON, pulling the output
In region B, the
transistors will be in saturation i.e. Vout drops sharply.
region C, both
transistor is partially ON and in region E, it is completel
In region D, the pMOS to GND.
leaving the nMOS transistor to pull the output down
OFF, by

p-device n-device Output

Region Condition
< V
Linear Cutoff
A 0sV,,
Saturated Vou Vpp /2
B
<Vpp/2 Linear

Saturated Saturated Vout drops sharply

Vin =Vpp/2

Vpp /2 <Vi, S Vpp-ViplSaturated Linear Vou<Vpp/2

D

Cutoff Linear V
E Vi, >VpD -Vl
Table 3.2Summary of CMOS inverter operation
passes through voltages between GNL
When both these transistors are ON ,Vin
power supply will be show
and Vpp. The resulting current Ipp with respect to
in Fig 3.4.

Ldsn =-Idsp
Current
in
CMOS
(Ipp)

VpD

Vin

Fig 3.4 CMOS current Vs input voltage

MOSFET Transistor Characteristics
3.5
Fig 3.5 shows simulation results
of an inverter from a 65 nm process. The pMOS
transistor is twice as wide as the nlMOS
transistor to achieve approximately equal
betas.

Vout

;T 1.0

0.8

0.6

0.4

0.2

0.04
+Vin
0.0 0.2 0,4 0.6 0.8 1.0

Fig 3.5 Simulated CMOS inverter DC characteristic

-3.2 C-V CHARACTERISTICS: DYNAMIC BEHAVIOR

3.2.1 Introduction
In a MOS transistor, there is an inter-electrode
capacitance between the
terminals. These capacitances are non-linear and are depèndent on
voltage
(C-y).

These capacitances can be approximated as simple capacitance

models. These
models are used for estimating delay power and
consumption of transistors and
mainly used for circuit simulation. The different MOS capacitance
models are:
i) Simple MOS capacitance model,
(ii) Detailed MOS gate, capacitance model.
(i11) Detailed MOS diffusion capacitance model.
3.6 .aVLSl andChip Design
A

3.2.2 Simple MOS Capacitance Model'ue noinie zvute211

act as a good capacitor and its
The gate terminal of a MOS transistor is
gate
necessary to attract charge to invert the channel. A high
capacitance is
capacitance is desirable to obtain high
can be viewed as a parallel plate capacitor
capacitance (or) capacitor
The gate dielectric
on top and channel at-the bottom with the thin oxide
with a gate
as,
between them and it can be expressed ... (1)
= C, WL
C
where, Cox - Capacitance per ünitarea of gate oxide,
Channel width, and
W-
L- Channel length.

In order to achieve a high speed and lower

power consumption, the transistor
as a constant for
length L' is kept minimum. Thus, taking this minimum L
as,
particular process. Then, the gate capacitance is defined
... (2a)
Gg= Cper micron X W

Cpe 6,oxL = Eox

L
... (26)
where, per micron
Iox tos
tor
stii shosG Oxide thicknesste:
= Permittivity of oxide

a Parasitic Capacitances
The capacitances of source and drain that oes
not affect an operation of the
devices but they normally affects the circuit performance and are called s
ey

parasitic capacitances.
(1) Diffusion Capacitance

The source and drain capacitances arise fromm p-n junctions between the
source (or) drain difusion and the body. So it is also called as diffust0"
capacitance Csb and Cdb.
MOSFET Transistor Characteristics
3.7

Gate 102i0 bsto6tnont bsgsM (5)

Cgs
FCgdta
Source Drain

Csb
Substrate

Fig 3.6 Various parasitic capacitance of MOS

From the Fig 3.6, the various parasitic capacitances are:

Ces - Gate to source capacitance,
- Gate to
substrate capacitance,
Cgd - Gate to drain capacitance,
-
Csb Source to substrate capacitance, and
-
Cab Drain to substrate capacitance.

Difusion exhibits high capacitance and high resistance. It is generally made

as small as possible in the layout.o

The total capacitance seen from gate terminal of CMOS transistor in Fig 3.6
29
S expressed as,
...(3)
(a) Types of Diffusion Regions
There are three types of diffusion regions are:

0) lsolated Contact Diffusion

Transistors are connected in series. Each source and drain has its own isolated
region of
contacted diffusion, as shown in Fig 3.7 (a).
(i) Shared Contact Diffusion
The drain of bottom transistor and source of the top transistor are connected to
form the shared contacted difusion region, as shown in Fig 3.7 (b).
3.81
tt VLSI and Chip Design

Diffusion
(iii) Merged Uncontacted
are into a un contacted region, as shown
The source and drain
merged

Fig 3.7 (c).

Drain 2

Gate 2

Source 2

Isolated9ei Shared Merged

Drain 1
52 Diffusion 6À Diffusion 32. Diffusion

1
Gate

52. 52 52
Source 1

W W

fc)
Fig 3.7 Difusion region geometries

3.2.3 Detailed MOS Gate Capacitance Model:tot all

The MOS gate sits above the chanel and may partially overlap the source and

drain diffusion areas. Hence, gate capacitance has two components:

()) Intrinsic capacitance (over the channel) C

ciuitia io 29qyT(6)
gc
(ii) Overlap capacitances (to the source and drain) -

+ Overlap(bottom plate) capacitance depends on the

mode of operation of transisto
and the intrinsic capacitance is
approximated as a simple parallel
plate as,

(1)Intrinsic Capacitance:i ud
Co =
Co WL . (4),

o2so: 0tkang
otdo NISd 3
The intrinsic capacitance has
three components representing
terminals which the dittere
is connected to the bottom
plate:
MOSFET Transistòr Characteristics |3.9

() Cp gate-to-source), and
(üi) C (gate-to-drain),

oiThen the total intrinsic gate capacitance, Co

ge is expressed
as, a
94

Co Ogb Co -- Cgc

Co Co 3
2
Cgd Cgd
Vds
Vdsat

(a)
as Vgs and (b) Vs
Fig 3.8 Cgc functionof (4)
Fig 3.8 (a) plots intrinsic gate capacitance Vs Vg in cutoff region and for
small Vas. Fig 3.8 (b) plots intrinsic gate capacitance Vs Vds in the linear and
saturation regions.
(a) Cut-off

When Ves<V. the MOS transistor is OFF, thus, there is no channel is formed.
i.e., Cgs =Cgd = 0.

When V,s is below.the threshold level, a depletion region forms at the surface.
Because of this, bottom plate moves downward from the oxide and resulting
in reducing the capacitance, as shown in Fig 3.8 (a).
(b) Linear

When Vo > V, the channel inverts and again serves as a good conductive
bottom plate. But, the channel is connected to the source and drain rather than
 VLSI and Chip Design
3:10| source
shared between the
channel charge is roughly
At low values of Vas, the
and drain.
(
Co
ie, Cg= Cgd ) (0)
near the drain becomes less inverted, therefore
When Vas increases, the region a smaller
capacitance is attributed to the source and
more fraction of the
3.8(b).
fraction to the drain, as shown in Fig

(c) Saturation
at this mode the channel is heavily
inverted. The drain
When Vá; > Vdsats

region of the channel is pinched off.

i.e., Cgd = Ccb
=0.

All capacitance is attributed to the source. Because of. pinchoff, the

capacitance in saturation region reduces to Cp C:

4 The intrinsic MOS gate capacitance in thesethree regions are summarized in the
7
following table 3.3:

Parameter Cut-off region LinearSaturation

sC
to-u)(s)
gs
2 3

2
Table 3.3 Approximation
for intrinsic MOS gate capacitance 769rij(d
(2) Overlap Capacitance tl o
beiottrus i
In a
real device, the gate
iats
sci: tu4.sriz !:*1
overlaps the source
to added overlap capacitances, as and the drain partialy. This leads
shown in Fig 3.9.
MOSFETIransistor.Characteristics
3:11
Source Gate
ADrai
Cgsol

t8)

(0).

Fig 3.9 Overlap capacitance

Overlap capacitances are proportional to the width of the transistor and it is
expressed as,
C gsol = (6a)
(overlap)880d: Sr3 ao tr3 ...
(6b)

The effective gate capacitance varies with the switching activity of the sourçe
and drain. The overlap capacitance is dependent on voltage. For delay
caleulation of digitalcicuits, the overlap capacitance can be approximated as,
...(7)
Ce =
Cps
t Cgd t Cgs Co +2 Cgol W
3.2.4 Detailed MOS Diffusion Capacitance Model
p-n junction
4 The parasitic capacitance across the depletion region exists in the
on the area
between the source diffusion and the body.,The capacítance depends
source diffusion region.
AS and sidewall perimeter PSof the

Gate
Drain Source

-D
3.12 ohTt: VLSland Chip Desien

Area AS = W.D

Perimeter PS = 2W + 2D

Then, the total source parasitic capacitance is expressed as,

... (8)
Cu = ASx Ch + PSx Cjisw

Cjbe Area junction capacitance between the body and the bottom of the source
which has units of capacitance / area and it can expressed as,
-M,
Cjbs ... (9)
Vo

where,

-C, Junction capacitance at zero bias,

M, - Junction grading coefficient, typically
in the range of 0.5 to 0.33
depending on the abruptness
of the diffusion junction, and
V,- Built-in potential that depends on
doping levels.
Cbsy -Junction capacitance
between the body and the sidewalls of
which has units of capacitance/
4

the source
length and this sidewall
capacitance is expressed

Cibssw =
-MJsW
Cysy
1+ ... (10)
SW - Side Walls
of the Source.
MOS transistor can
be
viewed as a four-terminal
between each device with capacitances
terminal pair as
shown in Fig 3.11.

Gate

Ogd

Source
Cgb o Drain
Cab

Body
Fig 3.11Capacitances
ofofoan MOS transistor
MOSFET Transistor Characteristics 3.13|
The gate capacitance includes an intrinsic component (to the body, source and
drain, or source alone, depending on operating regime) and an overlap terms with
the source and drain.

3.3TECHNOLOGY SCALING

3.3.1 Introduction.
a Dennard's Scaling Law
Dennard's Scaling Law predicts that the basic operational characteristics of a
MOS transistor can be preserved and the performance is improved if the critical
parameters of a device are scaled by adimensionless factor a. These parameters
include the following:
- All dimensions (in the x, y and z directions).
Device voltages, and
elahoi ar:lc2
Doping concentration densities.

a Definition of Scaling
The reduction of the size that is, the dimensions of MOSFETs, is commonly
size of MOSFET leads to an improved
referred to as scaling. The scaling down
of

performance of VLSI design and higher packing density circuit

of ona chip.
VLSI fabrication technology should also be evaluated to an increase packing
terms of several
density. VLSI fabrication technology may be characterized in
figures of merit which are given below:
(i) Minimum size of device.
(i) Number of gates on one chip.A eil tgte)

(iii) Power dissipation.

(iv) Die size.

(v) Production cost.
(i) Maximum operating requency. u
 and Chip Design
314| t3VLSI
can improved.by. shrinking the
HThe.all above-mentioned figures of merit b
itt dimensions of trnsistors, interconnections between them, adjusting
the doping

levels and the supply voltages.

a Objectives of Scaling
Scaling technology has the following three objectives:
Increase the transistor density.
Reduce the gate delay.
Reduce the power consumption.

Over the past many years to till date, much effort has been
focused towards the
evolution of fabrication process technology and scaling down of the devices and
a VLSI
feature size. So, scaling is an important factor and it is essential for
designer to know the scaling of MOS devices.1 B

3.3.2 Scaling Models

4 There are three different models available for scaling.
) Constant electric field (or) full scaling model,
(i) Constant (or) fixed voltage scaling model, and
so n
(ii)General (or) lateral scaling model.

4 In full scaling model, all the dimensions of the MOS devices are scaled by the
same factors, keeping the electric
field as constant.
4 In constant voltage scalng, the voltage VDD
is keptconstant and the process is
scaled. When the device is scaled down
by a dimension 1/X its current density
increases by X, whereas gate shrink
increases the urrent density by X*.
In lateral scaling, only gate length is
scaled down called gate shrink and it is
easy to implement.

a How isScaling Achieved?

- Allthe device dinmensions (lateral
and vertical) are reduced by
1/a.
-Concentration densities are increased by
.fh )
.MOSFET Transistor Characteristics 3.15
- Device voltages reduced by
l/a (not in all scaling methods).,A} 91A si50 ()
- Typically l/a = 0.7(30% reduction in the dimensions).

3.3.3 Scaling Factors

Wla DIß

Polysilicon

n+ n+

p
-type

fie Doping Ng

Fig 3.12 Scaled nMOS transistor

# Fig 3.12 shows the device dimensions and substrate doping level which are
associated with a scaling of the MOSFET transistors.
Here, two scaling factors 1/a and 1/ß are used, The 1/ß is used as a scaling

factor for supply voltage VpD and gate oxide thickness D.

4 l/a is the scaling factor for all the remaining linear dimensions, both vertical and
horizontal to the chip surface.
For the constant field model = a.
ß
For the constant voltage model
ß=1.
3.3.4 Scaling Factors for Device Parameters
The following are the scaling factors of device parameters which reveals the
effects of scaling:
 VLSI and Chip Design

where, Lis the channel length, scaled by l/a.

Wis the channel width, scaled by l/a.,
So, An is scaled by l/a
(2) Gate Capacitance (Ca)

CG is scaled by

(3) Gate Capacitance Per Unit Area (Co)

ox D
where,
E is the permittivity of the gate oxide.
Disthe gate oxide thickness,
scaled by 1/ß.
Thus, Co
is scaled by
1.ßi.
(4) Parasitic Capacitance (C.)' at obirit t u

d
where, dis the depletion
widthwhich
is scaled by 1la..
A, is the area of
the depletion region, o1ot
scaled by
Then, 1 l/a.
C, is scaled by

(5) Carrier Density

in Channel (Qon)

Lon
where, Co is scaled
by B and V, is scaled by 1/B.2e
Oon is the average charge per
unit area in the
and it is scaled by channel in ON state
 MOSFET Transistor Characteristics
|3.17|
1
Pon = 1
nilha BP
(6) Current Density (0)
Ipss
J= A

where, Ipss is saturation current, scaled

by 1/ß.

Then, Jis scaled by 1/8

1/
(7) Power DissipationPer Unit Area (P.)

P
Ag
where, Pg is power dissipation per gate, scaled by 1/B².

Then, Pa is scaled by
1/a? B

3.3.5 Summary of Scaling Effect for Different Devices

Constant Lateral
Parameter Symbol|Constant field
voltage scaling

Supply voltage VpD 1 1

1 1 1
Channel width W

1 1 1
Channel length L

Gate oxide thickness D 1 1

1

1 1

Gate area Ag
a2
 VLSI and Chip Design

3.18
Constant Lateral
Symbol Constant field scaling
Parameter voltage
1
1
Parasitic capacitance C,

1 1
C
Gate capacitance

Gate capacitance per 1 B

Cox
unit area
1
1
Saturation current ds B

Conductor cross-section Ac
1
1

Carrier density Qon 1 1 1

Channel resistance Ron 1 1

Current density
B

1
Switching energy E,

1
Logic 1 leyel V,
1

Power dissipation per

1
1
gate
B2
Power dissipation per

unit area P, 11

Gates per unit area N

Power speed product 1

1 1

Table 3.4
 MOSFET Transistor Characteristics
3.19
3.3.6 Merits and Demerits of Scaling
JMerits
The merits of scaling are
) Increased chip density i.e., more number
of gate counts on single chip.
(ii) Improved chip performance i.e., increased speed
and reduced power
consumption.
(iii) Improved device characteristics.
(iv) Reduced parasitic capacitance effects.

() Reduced interconnect delays between devices.

(vi) Chip cost reduces considerably.

E Demerits
The demerits of scaling are
(1) Even though overall power consumption reduces, but the power
consumption per unit area increases due to scaling. Hence, device gets
heated up during its operation.
(i1) Because of scaling down, carrier mnobility reduces which inturn reduces
the gain of device.
(iii) Reduced conductor size decreases the current carrying capacity.
to be
(iv) High package density increases the heat generated which is
dissipated by the forced cooling.

3.4 POWER CONSUMPTION (OR) POWER DISSIPATION

a
There are two components that can establish the amount of power dissipated in
CMOS circuit. These are,

(1) Static Power Dissipation

current drawn from the power
Static power dissipation is due to the leakage
power is due to:
supply, normally through the OFF transistor. Static
 VLSI and Chip Design
3.20
transistor.nQ b5 23isf
- Subthreshold leakage through OFF

- Gate leakage through gate dielectric.

source/drain diffusions.
-Junction leakage from
- Contention current in ratioed circuits.

expressed as,
Then, the total static power dissipation is
Pstatie Junctt contention)
VDD *.. (1)

(2) Dynamic Power Dissipation t

Power dissipation is due to the circuit switching to charge and discharge an
output load capacitance at a particular node at an operating frequency is called
Dynamic power dissipation. It is mainly due to the following:
Charging and discharging of load capacitances as gates switch.s0
Short-circuit" current when both pMOS and nMOS are
partially 'ON.
Then, the total dynamic power
dissipation can be expressed as,
Pamamie
dynamic= Paviching + P hort ...
circuit (2)
(3) Total power Dissipation

Based on equations
(1) and (2), the total power
dissipation is expressed as,
Piotal = P dynamic
Piestatic
t
... (3)
3.5 TWNO MARKS QUESTIONS
AND ANSWERS
1. Mention
thedifferent types
ofMOS capacitance
The different models.
MOS capacitance
models are:
(i) Simple MOS
capacitance
(ii) Detailed model.
MOS gate
capacitance
(iii) Detailed model..
MOS diffusion
capacitance
model.
 12LTanistor. Charactristics
321
Define parasitic capacitances of CMOS.
2
The capacitances of source and drain that does not
affect an operationof the
Äevices but they normally affects the circuit performance and are called as
parasitic capacitances.

2 What is the diffusioncapacitance in CMOs?

The source and drain capacitances arise from p-n junctions between
the source
(or) drain diffusion and the body. So it is also called as
diffusion capacitance Csb
and Cdb.

4. List the different types of diffusion regions.

There are three types of diffusion regions are: eatt e

() Isolated Contact Diffusion

Transistors are connected in series. Each source and drain has its own isolated
region of contacted diffusion.

(i) Shared Contact Diffusion

The drain of bottom transistor and source of the top transistor are connected to
form the shared contacted diffusion region.

(ti) Merged Uncontacted Diffusion

The source and drain are merged into an uncontacted region.

s/ What is scaling?
The reduction is, the dimensions of MOSFETs, is commonly
of the size that
an
referred to as scaling. The scaling down of size of MOSFET leads to
on a
improved performance of VLSI design and higher packing density of circuit
chip.

O. e s 3
Mention the need of scaling technology. jiaih
Scaling technology has the following three objectives:

Increase the transistor density.

 VLSI and Chip Design
3.22
Reduce the gate delay.

Reduce the power consumption.

7. Nane the different types

of
scaling methods.
scaling.
There are three different models available for

i). Constant electric field (or) fullscaling model,

(ii) Constant (or) fixed voltage scaling model, and

(iii) General (or) lateral scaling model.

8. Define fullscaling and constant scaling methods.

are scaled by the
In full scaling model, all the dimensions of the MOS devices
same factors, keeping the electric field as constant.

In constant voltage scaling, the voltage VpD is kept constant and the process is
scaled. When the device is scaled down by a dimension 1/X its current density
increases byX', whereas gate shrink increases the current density by X".

9. Give the nerits of scaling.

The merits of scaling are

() Increased chip density i.e., more number of gate counts on singlechip.

(i) Improved chip performance i.., increased speed and reduced power
consumption.

(iii) Improved device characteristics.

(iv) Reduced parasitic capacitance effects.

(v) Reduced interconnect delays betvween devices.

(vi) Chip cost reduces considerably.

10. List the types of power dissipation.NOVDEC 2017, APRIMAY-2018/

(or)
State the various types of power dissipation. APR/MAY- 2017|
MOSFET Transistor Characteristics
3.23
There are tw0 Components that can establish the amount of power
dissipated in a
CMOS circuit. These are,
) Static power dissipation, and
(i) Dynamic power dissipation.
11. What do youmean by static power
dissipation?isto
Static power dissipation is due to the leakage current drawn
from the power
supply, normally through an OFF transistor. Static power
is due to: i
Subthresholdleakage through OFF transistor.

Gate leakage through gate dielectric.

Junction leakage from source/drain diffusions.
Contention current in ratioed circuits.

12. State the reasons for dynamic power dissipation.

Power dissipation is due to the circuit switching to charge and discharge an
output load capacitance at a particular node at an operating frequency is called
Dynamic power dissipation. It is mainly due to the following:
Charging and discharging of load capacitances as gates switch.
Short-circui" current when both pMOS and nMOS are partially ON.

3.6 REVIEW QUESTIONS

I. Draw and explain the DC and transfer characteristics of a CMOS inverter with
necessary conditions for the different regions of operation.
[APRMAY-2017]
2. Explain the DC transfer characteristics of a CMOS Inverter with necessary
conditions for the different regions of operation. [MAYIJUNE -2016]
3. Explain the DC transfer characteristics of CMOS inverter. [NOVDEC-2021|
 orVLS and Chip Desig
3.24|
suitable
4. Explain in detail about C-V
characteristics of MOS transistor with
equations and diagrams.
APRMAY-2017)
S. Explain the need of scaling and its principles.

6. Highlight the need for scaling. Enumerate in detail constant

co electric field,
different
constant voltage and combined electric field and voltage scaling for
parameters of
MOSFET. jt dt NOVIDEC-2019].
7. Write note on power consumption.
 UNIT COMBINATIONAL
LOGIC CIRCUITS

Chapter4
COMBINATIONAL LOGIC CIRCUITS
4.1 PROPAGATION DELAYS

4.1.1 Introduction
instantaneously. This is
When gate inputs change, the output doesn't change
known as "gate" (or) "propagation" delay.
a gate (e.g. inverter) is the difference in time
* The propagation delay of logic
(calculated at
50% input-output transition) at output switches, after
of
application of input.

a Definition output to.:

The propagation delay is simply deftned as the time required for the
to 50% of its maximum
reach 50% of its final output when the input changes
input and it is denoted by tpd.
The propagation delay increases with increase in
operating temperatüre, supply

voltage and load capacitance.

Fig 4.1 CMOS inverter

 VLSI and Chip Design
4.2|

AEstimation of Propagation Delay ?

() To reduce gate delays
(iü) To increase operating speed

(iii)To improve overall device performance

(iv) To eliminate glitching.

4.1.2 Delay Estimation

Before calculating the propagation delay of CMOS Inverter, we will define some
basic terms:
(0) Switching Speed - Depends on time taken to charge
and ischarge load
capacitance, Ct
(iüi)
Rise Time (t) - Time taken by the output waveform to rise from 10% to
90% of
its steady state value.

(ii) FallTime (t) - Time taken by the output waveform

to fall from 90% to
steady state value. 10% of its
(iv) Edge rate
(tr)-t is the average of rise time and falltime
and it is expressed as,

(v) Contamination
2
Delay Time -
It is the minimum
the output crossing time from input
50%. crossing 50% to
The tpLH
defines the response
output transition, time of the gate
while tpHL refers for a low-to-high
propagation to a high-to-low (or) posittve
delay, t, is defined (or) negative
as average
the transition. Tne
of the two.
I ptlL.
pLH
Combinational Logic Circuits
4.3
Vin

50%

t
tpHL pLH
Vout

90%

50%

Fig 4.2 Definition of propagation delays

The propagation delay t, of a gate defines howquickly itresponds to a change at
its inputs, it expresses the delay experienced by a signal when it is passing
through a gate.

The maximum propagation delay is the longest delay between an input changing
value and an output changing value

4.1.3Critical Path
The path that causes propagationdelay is called the critical path, which imposes
a limit on the maximum speed of the current.

To estimate the delay, we have to find the various critical paths, which is
affected by the following four levels:

) Architectural level
is used in CMOS design. The number of gate delays, time taken
Microarchitecture
memory are considered
0 propagate, number of pipeline stages, execution units and
Into account during the design.
(i) Logical level
Atthe logic level, the timing should be optimized. The functional blocks, number
Of stages in a gate. fan-in and fan-out should be considered for design.
 VLSI and Chip Design
44
(ii) Circuit level
After selecting the logic, the transistor size should be chosen, at the circuit level.

(iv) Layout level

The delay depends on the layout which determines the lengths of the wire.

4.1.4 RCDelay Model

Consider a four-input NAND gate in Fig 4.3 which shows the equivalent RC

model of the gate, including the internal node capacitances.

The internal capacitances consist of the junction capacitances of the transistors,
as well as the gate-to-source and gate -to-drain capacitances. The latter are tuned
into capacitances to ground using the Miller equivalence.

VpD VDD

Rs Rs Rg

B
HHF
Ao M4 RA

A
HHHH
R3
Bo M3
B\

R2
Co M2

R1
Do M

Fig 4.3 Four-input NANDgate

and its RC
If the transistors is
ON' it can be viewed as a
modeato2
capacitor. In this, combination of resistor anu
RC ladder network
the propagation delay
Elmore delay model as: is estimated usins
Lal
IpHL =0.69 (RC, +(R + R,)C, +(R,+ R, +
R,)C, + (R, + R, + R, + R,)C)
Combinational Logic Circuits
4.5
Assuming that, all nMOS devices haye an
equal size, the above equation
simplifies as,

pHL
=0.69R(C +2.C, +3.C, +4.C,)

4.2 STICK DIAGRAM

4.2.1 Introduction
4 VLSI design aims to translate circuit concepts onto silicon. The stick diagrams
are a means
of capturing topography and 1ayer information using simple
diagrams.

a Definition for Stick Diagram

Stick diagram are used to convey the layer information through the use
of colour
code and it resembles the actual layout.

Stick diagrams uses 'sticks' or 'lines' to represent the devices and conductors. t
acts as an interface between the symbolic circuit and actual layout.

a Need of Stick Diagram

The need of stick diagram are,

) To minimize the time required for layout,

(i) To estimate an area before committing to a full layout,

(ii) It is used to find out whether there is any problem in the layout and we can
resolve the problem if any and can save time,
(iv) This is thebasic building block for designing complex circuits, and
() Easy to draw because they do not need to be drawn to scale.
Stick diagram are useful in planning the layout and routing of integrated circuits.
In a stick diagram, every line of a conducting material layer is represented by a
line of a distinct colour.
4.6| VLSI and Chip Design

Layer Colour Stick Diagram

n-diffusion Green

p-diffusion Yellow

Polysilicon Red

Contact Black

Metal-1 Blue

Metal-2 Dark Blue (or) Purple

Demarcation line Brown (p-welledge is shown as

a
demarcation line)

Table 4.1 Encoding of stick diagram for CMOS

In a stick diagram, nMOS transistor is formed whenever poly crosses n

diffusion and pMOS transistor is formed whenever poy crosses p- diffusion.

Polysilicon (red) Polysilicon (red)

p-diffusion (yellow) n-diffusion (green)

(a) pMOS (b) nMOS

Fig 4.4 Transistors in stick diagram

 Combinational Logic Circuits
4.7
4.2.2 Example
Vop

pMOS
Vin O Vout

nMOS

GND

Fig 4.5 CMOS inverter

Step 1

Draw the power supply rails both Vpp and Vss (or) GND are drawn horizontally
using blue colour (metal-1). Then an imaginary lin called demarcation line is drawn
horizontally between Vpp and Vss.

Metal (Blue)

VpD

Demarcation line
(Brown)

GND

Metal (Blue)

Fig 4.6 (a)

Step 2

Draw the transistors (pMOS and nMOS) in such a way that nMOS transistors
are

Placed below demarcation line close to Vss and pMOS transistors are placed above
demarcation line below VpD
 VISI and Chip Design
4.8

Metal (Blue)

VoD

p-diffusion
Polysilicon (Red) Yellow)

pMOS

Demarcation line
(Brown)
n-diffusion
(Yellow)

nMOS

t GND

Metal (Blue)

Fig 4.6 (b)

Step 3
The nMOS and pMOS transistors are interconnected by metall (blue). Only metal

and polysilicon can cross the demarcation line.

Vp

GND

Fig 4.6(c)
Combinational Logic Circuits
4.9
Step 4
Perform the remaining interconnections
and add the data output path.
Metal-1

VoD

p-diffusion
Contact Metal-1

Polysilicon

n-diffusion
GND

Metal-1

Fig 4.6 (a)

4.2.3 Gate Area Estimation
a Routing Track
The routing track has enough space to place a wire and the required spacing to
the next wire.
If wires have a width of 4h and a spacing of 42 to the next wire, then the
track pitchis 82, which is shown in Fig 4.7(a).
This pitch also leaves room for a transistor to be placed between the wires,
which is shown in Fig 4.7(b).
It is reasonable to estimate the height and width of a cell by counting the
number of metal tracks and multiply it by 8.

A Spacing Between nMOS and pMOSTransistors

The required spacing of 122.between nMOS and pMOS transistors set by the
wall, as shown in Fig 4.8(a). This space can be occupied by an additional track
of wire, shown in Fig 4.8 (b).
 t1 VLSI and Chip Desip
410
Polysilicon
Metal-1

|42

(b)
J42

|42

Metal-2
(a)

Fig 4.7 Pitch of routing tracks

n-well

p-diffusion

122itt t 122
Polysilicon 4

n-diffusion Contact

Fig 4.8 Spacing between nMOS and pMOS

Combinational Logic Circuits 4.11|
NAND Gate Area Estimation
(1) 3-Input
Fig 4.10 shows how to count tracks to estimate the size
of a 3-input NAND.
There are four vertical wire tracks, multiplied by 82 per
track to give a cell
width of 322..
There are five horizontal tracks that gives a cell height of
40.. Even though
the horizontal tracksare not drawn to scale, they are still easy to count.
VoD

Y
=A+ B +C

GND

Fig 4.9 3- input NOR gate schematic diagram

Metal-1

82
B
p-diffusion
82

82
40 Metal-1
n-diffusion

Contact|
82
Metal-1
Polysilicon
82

32
diagram
Fig 4.10 3- input NOR gate schematic
 NLSI and Chip Design
|4.12

4.3 LAYOUT DIAGRAMS

4.3.1 Layout Design Rules
a Definition of Layout Design Rules a ready translation
of
set of layout rules
are required for
The design rules (or)
on
i symbolic form into
diagram (or)
concepts which is usually in stick
circuit
actual mask layout in silicon. can how closely they
how small features be and
Layout design rules describes
manufacturingprocess.
can be reliably packed in a particular
are determined by process-line equipment and process
Design-rule definitions
layouts.
The design rules usually provide workable and reliable
design.

(1) Two Main Purpose of Design Rules

are,
The two main purposes of design rules
a conmunication link between circuit/systems designers and the
) Provide
process ngineers responsible for fabrication.
(i1) Optimize yield while keeping the
geometry as small as possible withou
an end product.
compromising upon the reliability
of

Layout Design
exac
the
Layout design is a schematic of Integrated Circuit (1C), which describes
placement of the components for fabrication.
The design rules basically addresses two issues:

() The interactions between different layers, and

the
(ii) The geometrical representation featurs that can be reproduced by
of

mask-making and lithographical proess.

a Design Rule Check (DRC)

layol
Design Rule Check(DRC) program
looks for design rule violations in the phe
It checks for minimum spacing and minimum size which ensures
combinations of layersfrom legal components.
 Combinational Logic Circuits
|4.13|
(2) Two types of Design Rules
Two types of des1gn ruleS are,
tstsMa k

isirMicron
designrule, and 0
ies
(ii) Lambda design
rule.tsska
The industrial design rules are usually
specified in microns. This makes the
tha design migrating fromn one process to a more advanced process
(or) a difficult
foundry's process difficult because not all rules
scale in the same way.
Micron rules specify the layout constraints such as minimum
feature sizes and
minimum allowable feature separations are stated in terms absolute
tht of
dimensions in micrometers.

(3) Lambda Based Design Rules

The MOSIS service is a low-cost prototyping service that collects the designs
from academic, commercial, and government customers and agggregates
them onto one mask set to share overhead costs and generate the production
volumes sufficient to fabrication companies.

MOSIS has developed a set of scalable lambda-based design rules that covers
a wide range of manufacturing processes.

The lambda based design rule species an every dimension of a system in terms
of a parameter , that characterizes the resolution of the process. 2. is generally
half of the minimum transistor channel length.

a Feature Size
Designer often describes a process by its feature size which refers to minimum
transistor lengtlt, so A is half the feature size. The transistor dimensions always
eified by Widtlh /Length rat

This length (i.e. transistor channel length) is the distance between the source
and drain ofa transistor and it is set by the minimum width of a polysilicon
wire.
 VLSI and Chip Desion
4.14|

E Advantages breaks in line

describe the minimum width to avoid
The design rules t
shorts between the lines, and minimum overla
minimum spacing to avoid
Overlap.
ensure that two layers are completely

a Short Channel Transistors lengi

system, the transistors are chosen to hve minimum possible
In a digital consumes les
channel transistors are faster, smaller and
because these short
power.

(4) CMOS Layout Rules (or) Design

Rules

(i) n-well Layer

(a) n - wells at same
potentaiacn3r53
-10 2 -10 A

62
(Spacing)

, n - wells at different potential

s (b)

10
A
-10

82
(Spacing)

Fig 4.1ln-well design rules

Minimum size(or) width -10 2
Minimum spacing (wells at same potential)-6
e, iti
Minimum spacing (wells at differential
potential)-82
(ii) Active Area

Minimum size (or) width

-32
Minimum spacing
-32
Combinational Logic Circuits |4.15

32 -3

3 2. (Green)
(Spacing)

Fig 4.12 Active area desig rules

(ii) Polysilicon

-22 -22
(Green).

Active
area 12 32 Polysilicon (red)

Fig 4.13 Polysilicon design rules

Minimum size (or) width -2 2

- 3
Minimum spacing between polysilicons 2
-
Spacing between polysilicon to an active area
1

(iv) p* (or) n Diffusion

7
72

n p+

-2

Active
layer 1siks
Fig 4.14 p and n
diffusion design rulesnit
 VISI and Chip Design
4.16|
diffusion -7A
Minimum size ofp* (or) n

an active area from diffusion wall- 22

Minimum spacing of

42

(v) Metal 1
Metal 1 (Blue) 42
Minimum size (or) width 42

Minimum spacing - 44

Fig 4.15 Metal -1 design rules

(vi) Metal 2

42 Minimum size

Metal 2 (Purple) 42 Minimum spacing

Fig 4.16 Metal -2 design rules

Minimum size (or) width –42
Minimum spacing
-42
(vii) Contact

Minimum size (or) width

of contacts - 22
Contact minimum spacing
(poly) - 22.
Contact minimum
overlap of poly - 22.
Minimum overlap
of metal
Combinational Logic Circuits |4.17

(i) (i)
! 22 22 22.

Contact (black)

Polysilicon (red)

Metal 1
(blue)

Fig 4.17 Contacts design rules

(vii) Diffusion

42

Fig 4.18 Contacts design rules

Minimum size (or) width - 42

Minimum spacing - 42

4.3/2 Gate Layouts

(1)Introduction

Drawbacks
A
vast amount time gets wasted by exploring layout topologies to minimize the
of

Size of a gate or other cell such as an adder or a memory element.

 VLSI and Chip Design
4.18
can he
For many applications,
a straightforward layout is good enough and it

automatically generated or rapidly built by hand.

Layout can be very time consuming when,

- Design gates to ft together nicely, and

Build a library of standard cells.

a Standard Cell Library

A standard cell library is a collection of well-defined and appropriately
characterized logic gates thatcan be used to implement a digital design.
Standard cells are like process and parameters qualified bricks tocreate a wall
where you can save time to create a brick.
A standard cell 1s a
80up of transistor, and. interconnect structures that
provides a boolean logic function (e.g., AND, OR, inverters ) or a storage
function (flip-flop or latch).

The simplest cells which are direct representations of an elemental NAND,

NOR, and XOR boolean function, although
cells of much greater complexity
are commonly used (such as a
2-bit adder or muxed D-input flip-flop).
Standard cell design methodology defines,

Vppand GND should have

standard height,
Adjacent gates should satisfy the design
rules,
nMOS transistor at the bottom
and pMOS transistor at the top,
and
All gates includes well
and substrate contacts.
a Line of Diffusion
A simple layout style based ona
"line of diffusion"rule that is commonly use
for standard cells
in automated layout
strips: Systems which consists of four horizontal

Metal ground at
the bottom of the cell, n- diffusion, p metal
power (VDD) at the top. -diffusion, and
Combinational Logic Circuits
4.19
The power and ground lines are often called as supply
rails. Polysilicon lines
run vertically to form a transistor gates.
Metal wires within the cellconnects
the transistors appropriately.

(2) Examples
(i) CMOS Inverter

Metal-1 n-well Well Tap

Vop

pMOS
Polysilicon

nMOS Contact

GND

Substrate Tap

(a) CMOS Inverter (6) (c)

Fig 4.19 Inverter cell layout

Fig 4.19 (b) shows a layout of a CMOS inverter. The input A can be
connected from the top, bottom, or left in polysilicon.
The output Y is available at the right side of the cellin metal.The p-substrate
and n -well must be tied to ground and power, respectively.
Fig 4.19(c) shows the same inverter with well and substrate taps placed under
the power and ground rails respectively.

i) 3Input NAND
are connected
Fig4.20 shows a 3-input NAND gate. Here, nMOs transistors
are connected in parallel.
in series while the pMOS transistors
 so if two gates were abutted the
Power and ground extend 22 on each side
design rules.
contents would be separated by 42 which satisfies the
or you coúnt 4h space between the cell and an
The height of the cell is 362., if
another wire above it then it would be 40.

40 2

32 2

Fig 4.20 3- input NAND standard cell gate layouts

a Considerations
are,
Some of the important consideration in an example Fig 4.20

Horizontaln-diffusion andp - diffiusionstrips, b

Vertical polysilicon gates,

Metall Vpprail at top, : 1

hg E u :

Metal2 GND rail at bottom, and

Layout size is 322 by 40. Ci

made
Generálly, these cells were designed such that the gate connections are
from the top or bottom in polysilicon.
Combinational Logic Circuits
|4.21|
In contemporary standard cells, polysilicon
is generally not used as a routing
laver so the cell must allow metal to
2 metal 1.and metal 1 to, polysilicon can
contacts to each gate.
This increases the size of the cell and allows free access to all terminals on
metal routing layers.

A.4 EXAMPLES OF COMBINATIONAL

LOGIC DESIGN
1
Example
VpD
Sketch a static ChMOS gate computing
A
Y= (4+B+ C) ·D
B
The above figure shows such an OR
AND-INVERT -3-1 (0AI31) gate. The OR
gate have 3 Y
inputs that is A, B and C, along
with this AND gate has additional input of 1.

VGND

Example-2
Draw the symbol and schematic diagram of CMOS inverter.
VoD

A - Y=
Ao -Y

GND
(a) Symbol (b) Schematic
Etample -3|
Draw the symbol and schematic diagram of two input NAND gate.

JAPRMAY-2017

VpD

Y=A•B

GND
(a) Symbol (b) Schematic

Example- 4

Draw the symbol and schematic diagram of two input NOR gate.

[APRMAY-2017|
VoD

Y=A+B = Y=À+
B

(a) Schematic
(b) Symbol
Combinational Logic Circuits 4.23
Example 5

Draw the schematic diagram of three- input NOR gateils)

Voo

Y=A+ B
+C

Gnd

Example
8ketch a 4-input CMOS NOR gate layout.
NOV/DEC -2017 & APRMAY-2018]
VoD

y=A+ B
+C+D
 VLSI and Chip Design
4.24)

rExample-7
Sketch a 4-input CMOS NAND gate layout
INOVDEC-2017 & APRMAY-201
-2018]
Vop

- -y=A• B•C•D
A

445 EXAMPLES
1
Example
Draw the layout and stick diagram fortwo input CMOS NAND gate.
NOVDEC-2018]
Vop

y=A•B

(a) 2-input NAND gate

Layout diagram
Cambinationai Logic Circuits
4.25

Metal 1

VoD

Yellow (p-difusion)

Polysilicon
(Red)
Blue (Metal 1)

Demarcation
line
A

Green (n-difusion)

Vss

Metal 1

(b) Stick diagram

Example- 2
Draw the layout and stick diagram for two input CMOS NOR gate.
Vbo

B
Vout =A + B

HE

Vss

(a) 2-input NOR gate

 s VLSI and Chip Design
|4.26

Metal 1 (Blue)

VoD

p-diffusion (Yellow)

Polysilicon

Vout

Demarcation line

Metal 1
/
(Blue)
n-diffusion (Green)

Vss

Metal 1 (Blue)

Example 3

Sketch a stick. diagram for a CMOS gate

conputing Y= (4+B +C) •D and
estimate the cell width and height.

VoD

VGND

(a) Layout diagram

for Y=(4
+B+C)-D
 Combinational Logic Circuits
4.27
Metal-1(Blue)

VpD
B

p-diffusion.
(Yellow) Metal-1 =
(Blue) 6 tracks 48
Polysilicon
(Red)
n-diffusion
(Green)

o GND

Metal-1
(Blue)
5 trackS = 40 A

(b) CMOS compound gate for function Y= (4 +B+) ·D

4.6 TWO MARKS QUESTIONS AND ANSWERS
1.
What is propagation delay?

When gate inputs change, the output don't change instantaneously.This is known
as "gate" (or) "propagation" delay.
The propagation delay is simply defined as the time required for the output to
reach 50% of its final output when the input changes to 50% of its maximum
input and it is denoted by tpd.

2. Give the reason for estimation of

propagation delay.
reasons:
The estimation of propagation delay because of following
(i) To reduce gate delays
(ii) To increase operating speed

(i1) To improve overall device performance

(iv) To eliminate glitching.

 5VLSIand Chip Design
|4.28

CMOS inverter.
3. Define rise time and fall tme of
output waveform to rise from 10% to 90% of
Rise Time (t)-Time taken by the

its steady state value.

the output waveform to fall from 90% to 10% of
Fall Time (t)- Time taken by

its steady state value.

4. Define critical path.

which imp0ses
The path that causes propagation delay is called the critical path,
a limit on the maximum speed of the current..

5. What do you mean by stick diagram?

Stick diagram are used toconvey. the layer information through the use of colour
code and it resembles the actual layout.

Stick diagrams uses ´sticks' or 'lines' to represent the devices and conductors. It
acts as an interface between the symbolic circuit and actual Javout 2s3 k

6. What are the needs of stick diagram?

The needs of stick diagram are,

) To minimize the time required for layout,

(ii) To estimate an area before committing to a

full 1layout, bas l4i
(iii) It is used to find out.whether
there is any problem in
can resolve the layout and we
the problem if any and can save
time,
(iv) This is the
basic building block for designing complex
circuits, and
(v) Easy to draw because
they do not need to be
drawn to scale.
7. Define CMOS layout
design rules.
The design rules (or) set
of layout rules are of
circuit concepts which required for a ready translation
is usually in stick diagram
actual mask layout (or) symbolic form
in silicon. into
Combinational Logic
Logic Circuits 4.29
Lavout design rules descrmbes how small features can
be and how closely they
oan be reliably
packed in a particular manufacturing process.

Mentionthe purpose of design rules.

8.

The two main purposes of design rules are,

() Provide a communication link between circuit/systems designers

and the
process Engineers responsible for fabrication.

(i1)Optimize yield while keeping the geometry as small as possible without

compromising upon the reliability of an end product.

9. Define layout design (or) layout diagrams.

Layout design is a schematic of Integrated Circuit(IC), which describes the exact
placement of the components for fabrication.

10. List out the issues addressed by the design rules.

The design rules basically addresses two issues:

() The interactions between different layers, and

(i) The geometrical representation of features that can be reproduced by the

mask-making and lithographical process.

I1. Name the types of design rules.

Two types of design rules are,
() Micron design rule, and
1(ii) Lambda design rule.

12. What is micron rules?

as minimum feature sizes and
Micron rules specify the layout constraints such
minimum allowable feature separations that are stated in terms of absolute
dimensions in micrometers.
 VISI and Chip Design
|4.30

13. Define lambda based design rule.

an every dimension of a system in temms of
The lambda based design rule species
process. is generally hale
a parameter 2, that characterizes the resolution of the
of the minimum transistor channel length.

14. Mention the advantages of design rules.

rules describe the minimum width to avoid breaks in a line, minimum

The design
minimum overlap to ensure that
spacing to avoid shorts between the lines, and
two layers are completely overlap.

15. Define standard cell library.

A standard cell library is a collection of well-defined and appropriately

characterized logic gates that can be used to implement a digital design.

Braw the layout of CMOS inverter. [NOVDEC-2016]

VDD

pMOS

Vin
O þVout
nMOS

GND

17. What is the needof demarcation line? [NOVDEC-2017]

In CMOS circuits, two types of transistors are used that is, 'n' and p' are
separated in the stick layout by the demarcation line (representing the p-well
boundary) wire
above which all p-type devices are placed (transistors and
(yellow).
The n-devices (green) are and
consequently placed below the demarcation line
are located in the
p-well.
Combinational Logic Circuits
4.31|
oraw the stick aiagram o
CMOS inverter.iJ ho waRonAPRMAY-Z019)
Metal-1

VDD

p-diffusion

Contact
Metal-1

Polysilicon

n-diffusion
GND

Metal-1

19. Draw the stick diagram of

NMOS NAND gate.
Metal-1

n-diffusion (green)

Polysilicon
(red)

Polysilicon

170; 7GND
Metal-1
 VLSI and Chip Desig,
4.32|

20. Draw the stick diagram ofNMOS NOR gate. (NOVDEC -2019]

Metal-1

VoD

Polysilicon
(red)
n-diffusion (green)

Polysilicon (red) Polysilicon (red)

GND

Metal-1

4.7 REVIEW QUESTIONS

1. Discuss in detail about the CMOS
inverter propagation delay with nead
sketches.

2. Draw the stick diagram and layout

for CMOS inverter. [NOVDEC-2018]
3. Explain in detailabout the
stick diagram with an example.
4. Write
the layout design rules and draw
NOR gate. diagram for four input NAND
annd

NOVDEC- 2017 & APRMAY-2013)

S. State the minimum
width and minimum spacing
draw the layout. lambda based design rules to
[APRIMAY-2019)
Discuss
in detail with a neat layout,
the design rules fora CMOS inverter.
NOVDEC- 2016/
 UNIT -II
Chapter 5
CMOS DESIGN

5.1 ELMORE'S DELAY (OR) ELMORE'S

CONSTANT
5.1.1 Introduction
Most of the circuits are generally represented as a
RC tree, because it has no
loops. The root of the tree is the voltage source and the leaves are the capacitors
at the end of the branches.

A Definition of Elmore Delay (or) Elmore Constant

The Elmore delay (time-constant) is equivalent to the first-order time costant
of the network (or) the first moment of the impulse response. This time
constant represents asimple approximation of the actual delay between source
node and node i.

The Elmore delay model estimates the delay from a source switching to one of
the leaf nodes as the sum over each node i of the capacitance C; on the node,
multiplied by the effective resistance R on the shared path from the source to
the node and the leaf. Then, the Elmore delay at node i is expressed as,

... (1)
i=l

where, R,, isthe shared path resistance (or) effective resistance, and
C; is the capacitor of a particular node.
 VLSI and Chip Design
5.2

5.1.2 Example
Compute the Elmore delay for Vot in the 2 order
RC system.

R1 ng R2
Vout

VoD C1

Fig 5.1 Second-order RC system

The above circuit has a source and two nodes. At node
n, the capacitance is C

and the resistance to the source is

R.
o At node Vout, the capacitance is C2 and
the resistance to the source is
(R, + R). Hence, the Elmore delay is

= RC
pd +(R+ R,)Cio aoi(2)
5.1.3 Normalized Delay
It is often helpful to express
delay in a process-independent
circuits can be compared form so that the
based on topology
manufacturing process. rather than the speed
of the
The normalized delay
d' relative to the inverter delay w.r.t Elmore delay 15
expressed as, '
d
=pd
... (3)
tpd

Fig 5.2 Fanout-of-4(F

CMOSDesign
S.3
In the above Fig S2, the
delay of a fanout of h inverter can be expressed
in
as =
normalized form d h+1.

A Fan-out
Ean-out is a term
that defines the maximum number of logic inputs
output ofa logic gate can drive reliably.
that a single

s1.4 Delay Components ut

& Generally, the delay might consists oftwo
components:ielbnitS
(i) Parasitic delay, and

(ii) Effort delay.

The parasitic delay is the time for a gate to drive on its own internal difusion
capacitance, which is independent of the gate size.
The effort delay depends on the ratio h of an external load capacitance to an
input capacitance and thus changes with transistor widths.

5.1.5 Elmore Delay of a CMOS Inverter

# A static CMOS inverter driving a load capacitance consisting of an intrinsic (Cu)
and an extrinsic component (Cexi).

+
C=Cext SCint

Fig 5.3 CMOS inverter with load capacitance

The load capacitance is expressed as,
...
C, = Cint t Cet =Cint (I + S) (4)

Where, S= Cort /Cint is a the ratio between extrinsic and intrinsic capacitance.
 VLSI and Chip Desipn
5.4
of a CMOS inverter
ie
propagation delay
Then the Elmore delay expression for
given as,
0.69 Re, (Cin t+ Cext) (5)
I,=
where, Rey is the equivalent path resistance.

5.2 CIRCUIT FAMILIES

circuits, Ih
Digital logic is divided into combinational and sequential
combinational circuits, the outputs depend only on the present inputs, whereas,
in

sequential circuits memory.

Generally, the building blocks for combinational circuits are logic gates,while
the building blocks for sequential circuits are registers and latches.

Out
Combinational, Combinational
In Logic Circuit Out Logic Circuit

State
(a) Combinational
(b) Sequential

Fig5.4 High-level classification

of logic circuits
The CMOS circuit families
includes the following logics
(i) Static CMOS Design

Complementary CMCOS
Ratioed Logic Circuits.
Pass- Transistor Logic.
(i) Dynamic CMOS.
Domino Logic.
Dual-Rail Domino
Logic.
NP Domino Logic.
(ii)Cascode Voltage Switch
Logic (CVSL).
 y
Destgn s
CMOS 5.5
The most widely used logic style
is static complementary CMOS. It is really an

extension of the static CMOS inverter to have multiple inputs.

Static CMOS circuits with complementary nMOS
pulldown and pMOS pullup
networks to drive 0
and I which are used for
the vast majority of logic gates in
an integrated circuits,

5.3 STATIC CMOS DESIGN: STATIC LOGIC GATES

5.3.1 Introduction
4A static CMOS gate is a combination of two networks, called Pull-Up Network
PUN) and Pull-Down Network (PDN).
In static CMOS, at every point in time (except during the switching transients),
eachgate output is connected to either Vop (or) Vss via a low-resistance path. An
output of the gate depends on the Boolean function implemented by the circuit.
# In dynamic CMOs, the output of the gate depends on temporary storage f

signal values on the capacitance of high impedance circuit nodes. The resulting
gate is simpler and faster. It is a design methodology in an integrated circuit
design in it uses a clock signal its implemeniation of comnbinational logic
that in
circuits.

5.3.2 Complementary CMOS

A static CMOS gate is the combination of twO networks

() Pull- Up Network (PUN)

to the high supply
A device connected so as topull the output voltage
up network.
voltage usually Vpp is called pull
(ii) Pul- Down Network (PDN)
an output voltage to the lower supply
device connected so as topull
A

network.
voltage usually 0V is called pull down
 VLSI and Chip Design
56
VoD

Ing o from Vop to F when

PUN F(In,Inz, ..In)=1
Pull-up: make a connection

Inyo
o F(In,Ing,... In,)

Ing o
Ing o Pull-up: make a connection from
Vpp to Vss when
PDN F(InIn2,. In,) 0=

In
Vss
gate
Fig 5.5 Complementary CMOS logic
to
The Fig 5.5 shows a generic N-input logic gate where all inputs is distributed

both the PUN and PDN.

an output and Vpp anytime when an output
PUN provides a connection between
an output to
of the logic gate is
1 (based on the inputs). Similarly, PDN connects

Vsg when an output of the logic gate is '0°.

(1) Working Principle

VoD

PUN
S

DD
0- VoD

VDD
PDN -0
D

Voo

Fig 5.6Pulling up and pulling down of anode using pMOS and nMOS
CMOSDesign
5.7
Consider, the PDN in above Fig 5.6
the load capacitor (C) is initially charged
to VpD- An nMOS device pulls an output
down to ground. The pMOS
decreases an output below the threshold yoltage
and turns OFF and as an
outputof PDN, we get 0.
In a PUN the output initially at ground. A
pMOS switch succeeds in charging
the outputall the way to Vpp.

(2) Construction of PUN and PDN

The PUN network consists of pMOS transistors and the PDN consists
of
nMOS transistors. The main reason is nMOS transistors which produces
"strong zeros and pMOS transistors generates "strong one".
A transistor can then be assumed as a switch which is controlled by its gate
signal. A nMOS switch is ON when the controlling signal is HIGH and is
OFF when the controlling signal is LOW.
A pMOS is an inverse switch ON when the controlling signal is LOW and is
OFF when the controlling signal is HIGH.

5.3.3 Bubble Pushing

Bubble pushing is the method of
representing the Boolean functions of
AND and
using NAND and NOR gates.
OR gates
CMOS acts as an inverter, hence NAND and NOR gates are used to construct
AND and OR operations. Non-inverting Boolean function needs
an inverter. In

the manual circuit design, this is done through bubble pushing.

A NAND gate is equivalent to an OR ofinverted inputs. A NOR gate is
equivalent to an.AND of inverted inputs. The conversion between these
Tepresentations is easily understood by using the DeMorgan's law.
* The steps in bubble pushing include
Start with network of AND/OR gates.
Convert to NAND/NOR + Inverters.
Push bubbles around these is used to simplijy the logic using DeMorgan's
Law.
 VLSI and Chip Design
|5.8

A.B Ä+B DeMorgan's law

A A

B B
=
A-B A+B
NAND Inverted OR

A+B A AB
= B
A+B =
A-B)(01
NOR Inverted AND

Fig 5.7 Bubble pushing with DeMorgan's law

x AND = NAND + INV

ii

OR = NOR + INV

Fig 5.8 AND and OR gates using bubble

pushing
5.3.4 Compound Gates
The static CMOS also have
better efficiency to handle
the compound gates. In
static CMOS, various functions can
be computed in single stage
compound gates (AND-OR-INVERT),which by using the
a
has lowerdolou than a
implementation. than logic gate
o The logical effort of compound
gates can be different
transistor widths are same as for different inputs.
an inverter. The
of an
input capacitance logic effort of an input is the ratio
of that input tothe input
capacitance ofthe inverter.
The parasitic delays are
computed from the
output node by total -diffusion capacitance
summing the sizes o
of the transistors attached
to the output.
CMOS Design 5.9

Unit Inverter = 3/3

9A
Y= 2
p=3/3
A -

AOI21
y=A-B+c -Y
A4B-4 9A =6/3
gB = 6/3
gc = 5/3
Y p=7/3
c
A2

A
AO122 gA =6/3
B gg 6/3
y= AB + CD
9c = 6/3
4 gp = 6/3
-Y p= 12/3
A B

6
Complex AOI
6 3 9A =
A

y=A(B+ C) + DE 5/3
A gB 8/3
gc = 8/3
-Y 9p = 8/3
= 8/3
9
p= 16/3

Fig 5.9 Logical efforts and parasitic delays of 0I gates

A
 VLSI and Chip Desip
5.10|
AO122, and,
how logical efforts can be estimated for the AO121,
Fig 5.9 shows are chosen to give the
transistors widths
more complex compound'AOIgate. The particula
Where 'g,'represents logical effort of the
same drive as a unit inverter.

minal x and 'p' represents the

parasitic delay.

5.3.5-Skewed Gates
phase i
same arriving at diferent parts of the design with diferent
The signal
a circuit for the speed, we
may want the falling
known as skew. When optimizing
to voltage to be faster than the rising
high low
transition of a signal from
or versa.
transition from low to high voltage vice
gates whose critical transition is faster than the
In this topic, we discuss skewed
HI-skew gates and LO-skew gates. In a
non-critical transition. We distinguish
in
is the faster critical transition, and
HI-skew gate, the rising output transition
is critical.
LO-skew gates the falling output transition

Vop. Vpp VoD

2 2
A A
Y=A
1/2 1/2

(a) HI-skew Inverter (b) Unskewed inverterwith (c) Unskewed inverter wvith

equal rise resistance equal fall resistance

Fig 5.10 Logical effort calculation for HI-skew inverter

5qX
Skewed gates are used when one input transition is more important than
other.

(i) HI-skew gates :

Used to favour the rising output transition.

(i) LO-skew gates: Used to favour the falling output transition.

* By decreasing the size of
achieved
the non-critical transistor, the skewing can be
CMOSDesign
S.11
Let 8, = Logical effort of rising (up) transition.
g = Logical effort of falling (down) transition.

Logical Effort of Skewed Gates

The logical effort of skewed gates is the ratio of the input capacitance
of the
skewed gate to the input capacitance of an unskewed
inverter with equal drive
for that transition.
Fig 5.10 (a) shows the HI-skew inverter which is constructed
by reducing the size
1
of nMOS. i.e., nMOS with size (r 1) which is reduced to
2

This maintains the same effective resistance for the critical transition while
reducing the input capacitance when compared to unskewed inverter which has
nMOS size as 1. This is shown in Fig 5.10 (b).

4 Thus, reducing the logical effort on that critical transition is, gu = 2.5/3 = 5/6.
Then, the logical effort for the falling transition is computed by comparing the
inverter to a small unskewed inverter with an equal pull down currents shown in
Fig 5.10(c).
=
The logical effort is gu = 2.5/ 1.5 5/3.

5.3.6 Asymmetric Gates

We
4 Logic gates sometimes have different logical eforts for the different inputs.
up the critical paths in a network by
call such gates as asymmetric. It can speed
reducing logical effort along the critical paths.
the
gate is said to be
When one input is far less critical than the other, then the
expense of early one. Consider,
asymmetric, which favours the late input at the
the resettable buffer as shown in Fig 5.11.

A
-Y
Reset
optimized fordata input.
Fig 5.11 Resettable buffer
 VLSI and Chip Design
5.12

as a buffer between A and Y. When reset ic

acts
In a normal condition, the path
asserted the path forces thé output LOW.

A 4/3

reset 4

2E
lon Fig 5.12 Resettable buffer using asymmetric NAND gate
So, reset should occur only during an exceptional conditions and the circuit
0 should be optimized for input-output delay at the expense of reset. This can be
arlt achieved by the use of asymmetric NAND gate as shown in Fig 5.12. ttori
The pulldown resistance is RJ4 +R/ (4/3) = R, so
the gate still offers the same
driver as a unit inverter. The capacitance on
input A is only 10/3, So the logical
effort is 10/9.This is better than 4/3,
which is normally associated with a NAND
gate.

The logical effort

of this circuit is nearly 1 which is
similar to an inverter. An
improvement in logical effort occurs
at the cost of higher effort on
An effort of pMOS is reset inpu.
also reduced to 1 in order
to minimize the diffusiot
capacitance and the parasitic
delay.
5.3.7 P/N Ratio
In the MOS technology, the
delay can be controlled
transistors in
the circuit. Here, by varying the sizes of
channel width. the size of a transistor
is measured in terms of its
CMOSDesign 5.13|

The ratio of pMOS to nMOS width is called P/N

ratio for logic gate. The P/N
a
ratio of library of cells should be chosen on the basis of area, power and
reliability but. not on the average delay.

VoD

B
1.414 2
A.

A
Y 2.:3 Y
A
2
9,=1.15 gu =2
ga
9a = 0.81 B = 4/3 =1
2 9u = 9avg =3/2
Javg = 0.98s g 4/3
1 9avg = 4/3

(a) Inverter (b) NAND (c) NOR

Fig 5.13 Gates with PN ratios giving least delay

The pMOS transistors are larger than nMOS transistors due to the smaller
mobility of holes, when compared to electrous. This relation is expressed in
design by the P/N ratio that is pMOS channel width is divided by nMOS channel
width.
= 2 is considered as the best ratio
For processes with a mobility ratio of ,/u,
giving the least delay. Fig 5.13 shows the gate with P/N ratios.
Reducing the pMOS size from 2 to 2 1.4 for an inverter gives the theoretical

fastest average delay, but this delay improvement is only 3%.

area which in turn reduces an
This will significantly reduce the pMOS transistor
input capacitance and also reduces
power consumption.

5.4 RATIOED CIRCUITS

5.4.1 Introduction
to implement an N-input
The static CMOS logic style requires 2N transistors
llogic gate. is an alternative method to reduce the. number of
Ratioed logic
the, cost of reduced
Iransistors reguired to implement a given logic function at
robustness and an extra power dissipation.
5.14 VLSI and Chip Design

th
Ratioed circuits depend on the proper size (or) resistances of devices for
correct operation.
to
The main purpose of a pull-up network (PUN) in complementary CMOS is
provide a conditional path between Vpp and an output when the pull-down
network (PDN) is turned OFF.

a Definition
to
In ratioed logic, a gate consists of a nMOS pull down network in order
implement the logie function and the entire Pull Up Network (PUN) is replaced
with a single unconditional load device that pulls up the outpuu for a HIGH
value, which is shown in Fig5.14(a).

VoD VpD

Resistive PMOS
R

load load

oF F

In2
PDN PDN

(a) Generic
(b)Pseudo - NMOS

Fig 5.14 Ratioed logic gate

When the PDN is OFF, the static
load pulls the output to 1(HIGH) the
PDN turns ON the and when
load must be weak enough
acceptable value 0 that the output pulls dow
(LOW). Here, there
is a ratio constraint between the Static
load and PDN.
CMOSDesign 5.15

5.4.2 Pseudo- nMOS Logic Gate Mo abae4

2tot
Definition
A
h Pseudo-nMOS logic gate, the pull-down network is like that of an ordinary
ratioed logic gate, but the pull-up network has been replaced with a single pMOS
transistor which is grounded so that it always ON, which is shown in Fig
5.15(b).
The main advantage of a pseudo-NMOS gate is, for N inputs it reduces the
number of required transistor as (N+1), which is 2N for complementary CMOS.
& A
Pseudo-nMOS gate is a logic gate, which is built using CMOSprocess that is
using both nMOS and pMOS transistors, but where the pMOS transistor is not
used in the computation of the result.
Since the pMOS here is always ON in order for this circuit to work, the

characteristics of the pMOS must be selected so that it is weaker than the nMOS
that will pull it down.

The nominal high output voltage (VoH) for this gate is VDD, since the pull-down
assume that low
devices are turned OFF, when an output is pulled HIGH and
LOW
output voltage (VoL) is below the threshold voltage (VT), then the nominal
on the output.
output voltage is not 0V that is, the voltage gets swing

Output Input voltage

VoD voltage
VpD

•F
A

Time
(b) Voltage characteristics
(a) Pseudo - nMOSinverter

Fig 5.15
5.16|
VLSI and Chip Design

Fig5.15 shows the Pseudo-nMOS inverter 'and its input-output voltage

characteristics. The low output voltage can then be expressed as,

2 Bn (Vop-Vr)
VoL

+ Fig 5.16 shows the schematics of four input Pseudo-nMOS NOR and NAND
operations. The pMOS transistor widths are selected to be about 1/4 of the
strength (i.e., 1/2 the effective width) of the nMOS pull-dovwn network which as
a compromise between noise margin and speed; this best
size is process
depéndent, but usually in the range of 1/3 tò 1/6.

VoD

VoD

Y=ABCD

QNi

QN2
QN4

QN3

Pseudo nMOS QN4

NOR operation
Y=(A+B+C+D)
Pseudo nMOS
NAND
operation
Fig 5.16 Pseudo-nMOS Y=ABCD
logic gates
CMOSDesign
5.17|

Ratioed Vs Ratioless

When the overall functionality

of the gate depends on the ratio of the nMOS
and pMOS sizes that is then the logic is calledratioed logic.
B,
Incomplementary CMOS, low and high.of an output
levels do not depend on
the transistor sizes. Hence, it is
called ratioless logic.
Advantages
Themerits of Pseudo-nMOS are listed as
follows:
i) Allows large fan-in.
(ii) Compact and simple.
(ii) High speed.
(iv) Low transistor count.

E Drawbacks of Ratioed Circuits

The main drawbacksof ratioed logic are

() Slow rising transitions.

(ii) High static power dissipation.
(iii) To ensure functionality certain ratio of sizes has to be maintained.
(iv) High propagation delay compare to complementary CMOS.
(v) Contention on the falling transitions.
(vi) Non-zero output low voltage (Vo).

5.5 DYNAMIc CIRCUITS: DYNAMICCMOS DESIGN: DYNAMIC

LOGIC GATES
5.5.1 Introduction

à Why Dynamic Circuits is Needed?

an
Static CMOS logic with a fan-in of N generaly requires 2N devices for
are used but
implementation. order to reduce this, a variety of approaches
n
it leads to the static power dissipation.
 VLSI and Chip Design
5.18

this static power dissipation, an alternate logic stvle

Hence, to eliminate
called dynamic(or) clocked logic is used.

a Definition
an integrated circuit design in
Dynamic circuit is a design methodology in
uses a sequence of precharge and
that it adds a clock input signal, which
conditional evaluation in its implementation
of
combinational logic circuits.

In dynanmic CMOS, an output Storage

on node
of the gate depends
In Out
temporary storage of signal
values on the capacitance of
C

high impedance circuit nodes.

The resulting gate is simpler
andfaster.

Fig 5.17 Dynamic circuit with

Storage capacitance

VoD

s0 Storage
node

-Vout

Inputs NMOS
network
Evaluate

CLK Precharge
CLK

Fig 5.18 Dynamic

CMOSblock
diagram
CMOS Design
5.19|
Dynamic (or) clocked
logic. gates are used to decrease
the complexity,
increase is speed, and lower power
dissipation. The basic concept
used in
dynamic logic is the capacitive
input of the MOSFET to store a charge
and
thus remember a logic level use
for later.

5.5.2. Basic Principles

The basic n-type CMOS dynamic logic gate
is shown in Fig 4.18, which consists
a
of pull-down network (PDN) as similar to
complementary CMOS.
4 The operation of this circuit is divided
into two major phases (modes):
() Precharge.
(ii) Evaluation.

The mode of operation is determined by the clock signal.

VpD

CLK M,

Out

In
In2 PDN
In3

CLK Me

Fig 5.19 n-type dynamicgate structure

 VLSI and Chip Dešign
5.20

(1) Precharge Mode

= output node Out is precharged to
VDD by the pMOS
When CLK 0, the
down path is disabled.
transistor M,and nMOS transistor M, is OFF and pull

eliminates any static power consumed during

The evaluation FET M,

precharge mode.

(2) Evaluation Mode

When CLK =1, precharge transistor M, is OFF and

the evaluation transistor

ON. The Out may remain HIGH (or) may be discharged

to LOW
M, is
through the PDN.

The pull down path is enabled such that the output is conditionally discharged

based on the input values: i

) F PDN conducts (or) in ON' condition depending upon the input, then a
low resistance path exists between Out and GND and the output 1s
discharged to GND. Once discharged, it cannot be charged
again until next
precharge operation (LOW).

(ii) If PDN does not conduct (OFF), the precharged value

remains stored on
the output capacitance CL. Then,the output can
be in high impedance state
during the evaluation period
(HIGH).
Cik

Precharge
Evaluate
Precharge
0

Out

Fig 5.20 Precharge

and evaluation
ofdynamic gates
CMOS Design 5.21|

5.5.3 Properties of Dynamic Logic Gate

Some important properties of dynamic logic gate are:
() Logic function can be implemented only by the nMOS pul-down
network (PDN).

(i) I is non-ratioed circuits that is sizing 'ofthe devices is not important for
realizing proper functionality of the gate.

(ii) For N inputs, dynamic logic requires N+2 transistors which is lower
when compared to 2N transistors for static CMOS.
(iv) It only consumes dynamic power, Ideally, no static curent path ever
exists between VpDand GND. The overall power dissipation, however,
canbe significantly higher when compared with a staticlogic gate.
(o) Faster switching speeds due to reduced load capacitance.

5.5.4 Examples of Dynamic Logic

Example I
VpD

CLKL
+
-Z= (A B)·C

CLK
 VISI and Chip Desion
5.22

Example-2
Three -input NAND

Vpp

Z= ABC
A

CLK –

Example3
VoD

CLK
Mp

Out = A
•B+C
A

CLK -
Me
CMOSDesign
5.23
Example- 4
-
Four input NAND

Voo

CLK
- Y= ABCD

Out
A

CLK

5.6DOMINO LOGIC

5.6.1 Introduction
A Monotonicity Problem in Dynamic Gates
In dynanic logic, a problem arises when cascading one gate to the next. The
precharge "1" state af the first gate may cause the second gate to discharge
state.
prematurely, before the first gate has reached its correct
I his uses up the "precharge" of the second gate, which cannot be restored until
Ine next clock cycle, so there is no
recovery fromthis error.

a Why Domino Gates Needed?

CMOS dynamic
The problems of faulty discharge of precharged nodes in
can not be cascaded.
circuits and simple single-phase dynamic logic which
These both can be solved using Domino logic.
 VLSI and Chip Design
S.24
best solution is
cascade dynamic logic gates, one the Domino
of
to
In order
logic, which inserts an ordinary static inverter
between the stages..

5.6.2 Working Principle

DD
VDD

CLK M,

Out 1
Out 2

PDN PDN
'n4
'n3

CLK Me CLK

1
Stage Inverter Stage 2 Inverter
dynamic CMOS dynamic CMOS

Fig 5.21 Domino CMOS logic

a Fig 5.21 shows the cascade of dynamic n-type
blocks in which during precharg®
phase of the clock, the output
stageof each is logic HIGH. This high-level outpu
is connected to the input
of the next stage.
A
Domino logic nodule consists of a n-type dynamic
followed by a static logic block whiCh
inverter, as shown in
Fig 5.21.
During precharge,
the ououtput of n-type dynamic gate
output of the is charged upto Vpp SO the
inverter becomes zero.
During evaluation
mode, the gate
inverter makes a conditionally discharges,
and the output ofthe
conditional transition
from 0 1.
CMOSDesign 5.25

Static Inverter (buffer)

Static inverter has an aditional
advantage that the fan-out of the gate is
a
riven by static inverter with a low-impedance output, which increases
the
noise immunity.
The buffer also reduces the capacitance of the dynamic output node by
separating internal and load capacitances.
The inverter can also be used to drive a bleeder device to conbat leakage and
charge redistribution,
During precharge, all inputs are set to 0. During evaluation, an output of the first
a0
omino block either stays at 0 (or) makes 1
transition, that affects the
second gate. This effect might ripple through the whole chain one after the other.

AA single clock can be used to precharge and evaluate all the logic gates within
the chain.

a Properties of Domino CMOS are

The properties of Domino CMOS
dynamic gate has a static inverter. Thus, only noninverting logic
() Each
pure domino design and
of

can be implemented. This is major limitation

a

it is used very rarely.

can be achieved. Becäuse only less number of
(i1) Very high speeds
are than the complementary static CMOS.
transistors used

(1) Effect of Ripple Precharge

gate are low during precharge and it eliminates the
The inputs to a domino increases the
because this reduces the clock load and
evaluation of transistor
the precharge cycle.
pull-down drive and also extends
through the logic network as well. Consider,
has to ripple devices are
O. Now, the precharge where the evalation
Fig 5.22,
logic network shown in
the
eliminated.
 VLSI and Chip Design
26

1 during eyaluation, then the output of each

dynamie
If the primary input In, is
1.

gate evaluates to 0, and an output of static inverter is

clock, the precharge operation is started. Assume, that

On the falling edge of the
In,makes a HIGH-t0- LOW transition.
VpD
VoD VoD

CLK Mp CLK
CLKd| Mp

Quti Oute Outn

01 01 0--1
Ing Ing Ing Inn
1-0 10 1-0 10

Fig 5.22 Efect of ripple precharge in dominoCMOS logc

The input to the second gate is initially HIGH and it takes two gate delays before
Inz is driven to.LOW. During that time, the second gate, can't precharge its
output.

Similarly, the third gate has to

wait until the second gate precharges and these
delay also exhibits extra power
dissipation.

5.7DUAL-RAIL DOMINO
LOGIC
Drawback
A
major limitation
in domino
logic is that only
implemented while some noninverting logic can be
The main
functions like XOR
approach to solve gates necessarily
this problem is dual require inversion.
In dual-rail domino
gates, each
rail (diferential) domino logic.
and output signal signal
pairs are is encoded with a input
pair of wires. The
denoted with
h and lrespectively.
CMOSDesign 5.27|

The h wire is
asserted to indicate that an output of the gate is “HIGH " or 1.

The Iwire is asserted to indicate that an output of the gate is LOW " or 0.

When the gate is precharged, neither nor

is asserted. The pair of lines
h l
should never be both asserted simultaneously during the correct operation.

sig h sig_l Meaning

no c
Precharged
1 0

1 0 1?

1 1 Invalid

Table 5.l Dual-raildomino signal encoding

compute
4 Dual-rail domino gates accept both true and complementary inputs and
both true and complementary outputs.
VDD

Y CLK

F
Inputs

CLK F&F-Pull down networks

Gate
Fig 5.23 Dual Rail Domino
can be viewed as,a Dynamic Cascade Voltage Switch Logic
* Dualrail domino implemented
All inverting and non-inverting logic functions can be
(DCVS).
 VLSI and Chip Design
|5.28|
of dual-rail dominologic is
diagram
using Dual-Raildomino. Thc general logic
shown in Fig 5.23.
onc PDN will be ON and other will be OFF, Tha
Atany given instance, of the
turns ON the pMOS transistor to
output LOW, which
"ON' PDN will pull the usino
output HIGH. The dual-rail logic can be implemented
pull the opposite
ANDNAND gate as shown in Fig 5.24.

VoD

CLK

Yh=A•B

Ay

-
B, Bn

CLK

Fig 5.24 AND/NAND

&
implementation
Dual-rail
domino requires more
area, wiring high
perfornance,
this differential approach and power. Due to its
becomes very in
several commercial
microprocessors. popular, and it
is used
 Design
CMOS
|5.29|
DOMINO LOGIC (NORA LOGIC):
5,8 NP NP-CMOS
To eliminate the need for extra static inverter
an alternative (buffer) in the critical path in
domino logic, approach to cascading
dynamic logic blocks which
n-tree and p- tree of
Uses dynamic logic called as NP- CMOS
is
domino logic.
MPCMOS uses
two types ot dynamic logic namely.

(i) n-tree logic gate.

il () p-treee logic gate.

That is: alternate logic blocks of n' and 'p'

in cascaded structure.
A
In a p-tree logic, pMOS transistors are used to build a pull-up logic
network
PUN), including a pMOS evaluation transistor.
A The nMOS predischarge transistor makes the output LOW during precharge,
thus the output after evaluation becomes 1 due to 0
shows the NP-CMOS
1
-
transition. Fig 5.25
logic circuit.
VoD VoD

CLK Mp CLK - Mp
J Out,

PUN
In
Ing
In2 PDN
In3 Oute

CLK CLK Me
Me
To other
N-blocks
To other
P-blocks

Fig 5.25 NP- CMOS logic circuit

 VLSIand Chip Design
|5.30

n-tree and p-tree logic gates to

NP- CMOS logic exploits the duality between
eliminate the cascading problem.
are controlled by CLK
n-tree gates are controlled by CLK, then p-tree gates
If outputs
n-tree gates can directly drive p-tree gates, and vice-versa. n- tree
Thus,
to another n-tree gate.
must go through an inverter when connecting
() During Precharge
precharge phase (CLK = 0), the output of the n-tree gate, Out, is
During
the output of the p-tree gate, Out, is pre-discharged to
charged to Vpp, while
OV.
devices, PUN of the p-tree is turned
As n-tree gate connects pMOS pull-up
OFF.

(ii) During Evaluation

n-tree gate can only make a 10 transition,
During evaluation, the output of
cannot be discharged
turning ON some transistors in p-tree. Thus, Out,
accidentally.

Disadvantages
The disadvantages of np-CM0S logic are.
n- tree blocks modules, due to the lower
() p-tree blocks are slower than the
currentdrive of the pMOS transistors in the logicnetwork.
(ii) It requires more time to equalize propagation delay.

5.9 SOLVED EXAMPLES

Problen -1
Design a
circuit using NAND and NOR gates for the following expression.

AB + CD
=
F
Solution:
Step l: Represent the logical expression in the form of basic gates using two
ANDs and an OR.
CMOSDesign
5.31
AB

-F

F= AB + CD

Step 2: Now the AND and OR gates are

converted to basic CMOS stages.

AB
AB+ CD

F=AB + CD

CD

Step 3: Now the bubble pushing technique is used to convert the AND and OR
gate into NAND and NOR gates.

Step 4: Now the circuit is further reduced to two NAND and one NOR gates
by using bubble pushing.

F=AB + CD

CD
 VLSI and Chip Design
5.32

Problem- 2|

Draw the static CMOS logic circuit for the following expressions.
(or)

Sketch the complementary CMOS gate computing the following expressions:

fy F-4.B) +(C.D) INOVDEC-2020 &APR/MAY-2021|

(i) F=(A+ B+C)D

(ii) F= D(4+ BC) [APRMAY-2016]

(y F=A(B +C)+DE| NOVDEC-2017 & APRIMAY-2018]

Solution:

()
VoD

A -B

F=(A• B)+ (C• D)

B
CMOSDesign
|5.33
(i)

Voo

B D4C
A

-F=(A+ B +
C)•D

DL

(tüi)

Vpp

D
B C

oF=D (A+ BC)

B
A
5.34| VLSI and
Chip Design

Voo
(v)
B

Z= [A(B +C) + DE]

Problem3
How to implement F= ab + be + ca using static CMOS logic.
Solution:

F= ab + bc + ca F = ab + bc + ca

VoD

C
a

GND
CMOSDesign |5.35

Problem4|
Realize the following function Y= (4 + B) D +E using static CMOs logic.
APR/MAY- 2019)
Solution:

Voo.

VDD

EL Y=(A+ BC) D +E

GND
B
EE
AHL

5.10 TWo MARKS QUESTIONS AND ANSWERS

I. What is meant by Elmore delay (or) Elmore constant?

INOVDEC-2017, APRMAY-2017 & APRMAY-2018]

The Elmore delay (or) time constant represents a simple approximation of the

actual delay between source node and nodei.

The Elmore delay model estimates the delay from a source switching to one of
the leaf nodes as the sum over each node i of the capacitance C; on the node.
 VLSI and Chip Design
|5.36|

resistance Rk on the shared path from the Sourc to

multiplied by the effective
Then, the Elmore delay at node i is
expressed as,
the node and the leaf.
N

i=l

where, R,, is the shared path resistance (or) effective resistance,

and

C,is the capacitor of a particular node.

2. What is normalized delay?

Normalized delay is often helpful to express delay in a process-independent form

so that the circuits can be compared based on topology rather than the speed of
the manufacturing process.

The normalized delay d'relative to the inverter delay '.w.r.t Elmore delay is
expressed as,

d
T

3. What do you mean by parasitic delay?

The parasitic delay is the time for a gate

to drive on its own internal
diffusion
capacitance, which is independent
of the gate size.
4. Give Elmore delay
expression for propagation
delay of an inverter.

[MAYIJUNE -2016]
Elmore delay expression
for propagation delay
of a CMOS inverter is given as,
t, = 0.69 R
where, Req
Rea (Cm
t Ce)
i the equivalent path resistance.
C;jnt
is the intrinsic capacitance,
and
Co
is the extrinsic capacitance.
 CMOS Design

5. Define static CMOS.

537
A
static CMOS gate is a
combination of two networks,
(PUN) and Pull-Down Network called Pull-Up Network
(PDN),.
In static CMOS, at every
point in time (except during
the switching transients),
each gate output is connected
to either Vpp (or)Vss via a
low-resistance path. An
outputof the gate depends on
the Boolean function implemented
by the circuit.
6. List the advantages of staticCMOS
design.
The main advantages
of static CMOS structures are
Low sensitivity to noise (robustness)
(ii) Low power consumption.
(ii) No static power dissipation.
(iv) Good performance.
(v) Easy to design.
(vi) Widely supported by CAD tools.
(vii) Readily available in standard cell libraries.

7. Differentiate between static CMOS and dynamic CMOS.

In static CMOS, at every point in time (except during the switching transients),
each gate output is connected to either VDD (or) Vss via a low-resistance path. An
output of the gate depends on the Boolean function implemented by the circuit.

Indynamic CMOS, the output of the gate depends on temporary storage of signal
values on the capacitance of high impedance circuit nodes..The resulting gate is
simpler and faster. It is a design methodology in an integrated circuit design in
0
that it uses a clock signal in its implementation of combinational logic circuits.

8 What is PUN?
A device connected so as to pull the output voltage to the high supply voltage
usually Vpp is calledPull Up Network (PUN).
 VLSI and Chip Design
5.38|

9. Define PDN.
A
device connected so as to pull an output voltage to the lower supply voltage
usually 0V is called Pull Down Network (PDN).

10. State bubble pushing with examples. isiy ny

batb2tttd et ugaogieg o

Bubble pushing is the method of representing the Boolean functions of AND and
OR gates using NAND and NOR gates.

A NAND gate is equivalent to an OR of inverted inputs. A NOR gate is

equivalent to an AND of inverted inputs. The conversion these between
representations is easily understood by using the DeMorgan's law.

A A·B A A+B DeMorgan's law

B
B
=
NAND
A-B +B
Inverted OR

A#B –
A A-B
B
=
A+B A.B
NOR
Inverted AND

11. Define logical

effort.
Logical effort is defined as
the ratio of the input
capacitance of an capacitance of a gate to
inverter delivering the same the inpu
number of times worse
output curent, It is defined as the
it is at delivering output
with identical input current than
capacitance. would be an inverte
12. What do you
nean by PN ratio
The ratio of forlogic gate?
pMOS tonMOS
width iscalled
channel width P/N
ratio for logic pMOS
is divided by nMOS gate that is
channel width.
 CMOSDesign
|5.39
13, Define Rationed circuit.

Ratioed logic is an alternative

method to reduce the number
required to implement a given
of transistors
logic function at the cost of reduced
robustness
and an extra power dissipation.

In ratioed logic, a gate consists a nMOS pull down network

of in order to
implement the logic function and
the entire Pull Up Network(PUN) is replaced
with a single unconditional load
device that pulls up the output
foraHIGH value.
14. What do you mean by pseudo-nMOS logic?

In Pseudo- nMOS logic gate,

the pull-down network is like that of an ordinary
ratioed logic gate, but the pull-up network
has been replaced with a single pMOs
transistor which is grounded so that it always ON.

15. Draw 4-input NAND and NOR gates using Pseudo -nMOS logic.
VDD

VpD

Y=ABCD

-o Y A QN1

B QN2

QN3

D QN4

Pseudo nMOS NOR operation

Y= (A+ B+C+ D) Pseudo nMOS NAND operation
Y=ABCD
 VLSI and Chip Design
5.40

16. Why Pseudo-nMOS logic is called as ratioed logic?

on the ratio of the
The overall functionality of the Pseudo-nMOS gate depends

nMOS and pMOS sizes that is 2 then the logic is called ratioed logic.
B,

17. Listthe merits of Pseudo-nMOS logic gates (or) ratioed circuit.

The merits of Pseudo-nMOS are listed as follows:

() Allows large fan-in.

(ii) Compact and simple.
(iii) High speed.e
(iv) Low transistor count.
18. List the drawbacks of ratioedcircuits

The main drawbacks of ratioed logic are

() Slow rising transitions.

(ii) High static power dissipation.
(iii) To.ensure functionality certain ratio of sizes has to be maintained.
(iv) High propagation delay compare to
complementary CMOS.
(v) Contention on the falling transitions.
(vi) Non-zero output low voltage
(Vo.).
19. What do you neanby
Dynamic circuit?
Dynamic circuit
is a design methodology in an integrated
adds a clock input signal, circuit design in that it
which uses a sequence
evaluation in its implementation of precharge and condition
of combinational logic circuits.
In dynamic CMOS,
an output of
values on the gate depends on
the capacitance of temporary storage of signal
simpler and faster. high impedance
circuit nodes. The resulting gate is
20. Listout
the properties
of dynamiclogic gate.
Some important
properties
of dynamic logic
gate are:
CMOSDesign
5.41
() Logic function can be implemented
only by the nMOS pull-down
network (PDN).
i) It is non-ratioed circuits that sizing
is of the devices is not important
for realizing proper functionality
of the gate.
(ii) For N inputs, dynamic logic requires N+2 transistors
which is lower
when compared to 2N transistors for static CMOS.
(iv) It only consumes dynamic power. Ideally, no
static current path ever
exists between VDD and GND. The overall power dissipation,
however,
can be significantly higher when compared
with a static logic gate.
(v) Faster switching speeds due to reduced load capacitance.
21. Why single phase dynamic logic structure cannot be cascaded? Justify.
[APR/MAY- 2016/
In dynamic logic, a problem arises when cascading one gate to the next. The
precharge"1" state of the first gate may cause the second gate to discharge
prematurely, before the first gate has reached its correct state.
This uses up the precharge" of the second gate, which cannot be restored until
the next clock cycle, so there is no recovery from this error.

22. Write the properties of

Domino logic.

The properties of Domino CMOS are:

Each dynamic gate has a static inverter. Thus, only noninverting logic
can be implemented. This is a major limitation of pure domino design
and it is used very rarely.
(ii) Very high speeds can be achieved. Because only less number of
transistors are used than the complementary static CMOS.t
23, State the drawback of dominologic.
logic can be
A major limitation in domino logic is that only non-inverting
inversion.
Implemented while some functions like XOR gates necessarily require
The main approach to solve this problem is dual rail
(differential) domino logic.
 VLSI and Chip Design
5.42

24. Define dual-rail logic.

both true and
Dual-rail is also called differential logic because it handles
types of dual-rail logic circuite
complementary signals at any time. The major
includes the following:

() Cascode Voltage Switch Logic(CVSL),

(ii) Complementary Pass-transistor Logic (CPL),

(iii) Double Pass-transistor Logic (DPL), and

(iv) Differential Cascode Voltage Switch with Pass-Gate (DCVSPG) logic.

5.11 REVIEW QUESTIONS

1.
Brief about Elmore's constant.
2. Explain the operation of
static CMOS logic with neat sketches.

3. Brief about Bubble pushing with an example.

4. Writeshort note on Ratioed circuits. NOVDEC-2016]
$. Explain in detail about Pseudo -nMOS gates with neat circuit diagram.
6. Discuss in detail about PN ratioof logic gate.
7. Brief about Dynamic circuit logic with examples.
8. Explain the domino logic with neat diagram. [NOVDECC 20177
9. With neat diagrams, discuss in detail about the dual-rail Dominologic witlh
example.
10. Write short notes
on:
() Ratioed circuits.
(tt) Dynamic CMOS
circuits.
NOV/DEC- 2016|
11. Describe
the basic principle of and
NP domino logic operation of dynamic CMOS, domino
with neat diagrams.
 UNIT -II

Chapter6o
PASS-TRANSISTORS LOGICn 65

6.1 PASS-TRANSISTORS LOGIC (PTL)

6.1.1 Introduction
* Pass -Transistor Logic (PTL) describes several logic families used
in the design
of an integrated circuits. It is a popular and widely used alternative for the
complementary CMOS.
PTL are generally superior to CMOS circuits in terms
of delay and power
consumption.

a Definition
In PTL, the transistors are used as switches to pass logic levels between the
nodes ofa circuit, instead of those switches connected directly to supplyvoltages.
This reduces the umber of transistors which is used to make differet logic gates
byeliminating the redundant transistors.

Switching
Network

B
A
f
B

AND NAND

Fig 6.1 Pass-transistor logic

 VLSI and Chip Design
6.2
state
and goes to High impedance
o It passes logic to output when device is ON
transistors
element of pass networks is MOS
when it is in OFF state. The basic
as variable' and source as a pass variable'
with signals provided to gate 'gate
multiplexers
circuits are widely used in design of ROMs, PLAs,
Pass transistor
etc.
Strong Zero and Weak One
(1) nMOS Pass Transistor: we
an almost perfect swicth when passing á 0 and thus
o A nMOS transistor is
0 but acts as an imperfect swicth
at a passing 1.
say paSses a strong
it threshold
voltage level is somewhat less than Vpp because of
o Because high
or
we say it passes a degraded weak l.
effect (V, =Vpp-VTH) and
weak 1 we may get 4.4 V
Example: when VpD is 5V, but in
turns ON when a is
1
acts as a Switch that
o Fig .2 (b) shows that nMOS
Fig 6.2 (c) show the symbol of nMOS pass transitor.
applied to gate (g =1).
0 and
when g =1 for an input 0, it produces strong
o Fig 6.3 (d) shows that
degraded '1'.
for the input '1' it produces
g=0

2
g=1

(a) Symbol (6) Act as Switch

Input |Output
Gate (control)
g=1
Strong 0

g=1
Pass o o Out Degraded1
(In)

(c) As pass transistor (d)

PAs-17ansistors Logic
6.3
Gate Pass
Out
0
hi-z
1
hi-z
0
1 1
Degraded 1

(e) Truth table

hi-z High
impedancenaAA)
Fig 6.2 nMOS as pass transistor
sin )
12) DMOS Pass Transistor: Strong One and Weak
Zeroa3
o
An pMOS transistor is an almost perfect swicth when passing a l and thus we
say passes a strong 1 but act as an imperfect switch at passing a 0. L.a
it
o Fig 6.3 (6) shows that pMOS act as a swicth that turns ON when a 0 is applied
to gate(g). Fig 6.3 (c) shows that when g =0 for the input 0, it produces
degraded '0° and for the input 1' it produces strong 1'.
g=0
S

g=1
d

(b) Act as switch

(a) Symbol

Input
g=0
Degraded 0
ti

1
g=0 Strong 1
r:
(e)

as pass transistor
Fig 6.3 pMOS
 VLSI and Chip Design
6.4
an even simpler structures, but miok,
nMOS-only pass- transistor logic produces
noise margins. This problem
suffer from static power consumption and reduced
can be addressed by adding a level-restoring transistor.

a PTL Families:

The Pass Transistor Logic (PTL) families are,

i) Complementary Pass-transistor Logic (CPL).

(i) Swing Restored Pass-transistor Logic (SRPL).

(ii) Double Pass-transistor Logic (DPL).
(iv) Differential Cascode Switch with Pass Gate
Logic (DCVSPG).
6.1.2 Basics of Pass-Transistor
It reduces the number of transistors required to
implement logic by allowing the
primary inputs to drive gate terminals as
well as source-drain terminals.
B

-F=AB

Fig6.4 Pass
transistor implementation
The Fig 6.4 shows
an implementation ofan AND gate
transistors.
In this gate, of an AND.function
and copies the
if the B input using only nMO
input A to the is HIGH, the top transistor
output F. is turned
ONO

When B
is LOW, the
bottom
transistors require pass-transistor
lower switching isturned ON
reduced voltage swing. energy and passes a 0.
Pass-
to charge up a
node, due to the
Pass -Transistors Logic 6.5|

The switch driven by B. seems to be redundant at first glance. Its presence

is
Pssential to ensure that the gate is static that is a low-impedance
path must exist
to the supply rails under all circumstances.

A The implementation of the AND gate in Fig 6.4 requires 4 transistors including
the inverter required to invert B, whilea complementary CMOS implementation
would require 6 transistors. The reduced number of devices has the additional
advantage of lower capacitance.
Pass-transistor gates cannot be cascaded by connecting the output
of a pass gate
to the gate input of another pass-transistor.

6.1,3 Complementary Pass- Transistor (CPL) Logic

E Drawback of CVSL:

CVSL uses a pMOS cross-coupled latch as the load, it cannot work as fast as
expected because it cannot be easily inverted due to the regenerative property
of the latch.
drawback can be overcome by the Complementary Pass-transistor
This
Logic(CPL).which resolves this problem by making one halfof the gate pulls
up while the other half pulls down.

For an high performance design, a differentialpass-transistor logic family, called

Complementary Pass-transistor Logie (CPL) is used. It is otherwise called as
Diferent Pass-transistor Logic.
In CPL, bothtrue and complementary inputs are given as inputs which produce
uue and complemnentary outputs that mean, it is dual-rail.- ) T:

A Definition of CPL
The tern "Complementary Pass-transistor Logic" (CPL) is used to indicate a
Sple of implementing logic gates where each gate consists of a nMOS-only pass
Iransistor network. followed by a CMOS output inverter. Hence, the pMOS cross
Coupled latch can be removed.
 VLSI and Chip Design
6.6

Dual-rail
function
variables
Dual-rail
outputs

Dual-rail
function fnetwork
Optional
variables
.0 Output buffers
(output stage)

(Dual-rail) control
variables

Fig 6.5 The general block diagram of CPL

The basic. structure of CPL is shown in Fig 6.5, which consists of the
complementary inputs and outputs, two nMOS networks for realizing both truth

and complementary functions f and f, and pair of the output buffers.

The two nMOS networks function as pull-up and pull-down devices; hence, the
pMOS cross-coupled latch can be removed.

The output buffers are used to restore the signals to the desired voltage levels in
order to compensate for the VT, loss due tothe pass transistors.

A pMOS latch can also be added to CPL, as indicated in Fig 6.5

with the lighter
lines, to reduce static power dissipation caused by
the output buffer when
receiving a high-level voltages.

6.1.4 Examples
Example 1

Two- Input CPL NAND/AND Gate

Using CPL style, realize a
two-input ANDINAND logic
function.
Solution:

(1) NAND Logic:

Based on the general block diagram

of CPL,
gate is expressed as,
the f network fortwo-input NAND
 s Logic
Pass.-Transistors
6.7

f= xy
This can be expanded with respect to variable 'y' into
the following:
Digital logics:
Demorgan's law

A+B = A+AB i223

ytyx
A= A
y1+y x

A = A-A =A.1
f= yy +y •x
(2) AND Logic:
Similarly, the
f network for two-input AND gate is expressed as

This also expanded with respect to variable “y' into

the following:
f=xy = 0+yx
yy =
y•0=0y=0
= y0tyx

f=xy
=
yy+ x

f=xy

f=xy
 VLSI and Chip Design
6.8
2
FEXample

Two- Input CPL XOR/XNOR Gate

a two-input XORXNOR logic function
Using CPL style, realize

O Solution:
network for
Based on the general block diagram of
CPL, the f
() XNOR Logic:
expressed as,
two-input XNOR gate is

f= xy
|7-tyx
gate is
thef network of CPL for two-input XOR
(i) XOR logic: Similarly,
expressed as,
x y
f=

f=x*y

6.1.5 Properties
The properties of CPL are:
(0) Differential

Complementary data inputs and outputs are always available (so no exu
inverters are required).
slgn Logic
Pass -Transistors

6.9
) Static Gate
opI. belongs to
the class or static gates,
because the output defining
ars tiedto VpD (or) GND through a
low resistance path. This
nodes are
is advantageous
for the noise resilience.

(i) Modular Design

tk for
The design is very modular; all gates use
the same topology, only the inputs are
permutated (varied). This
makes the design of a library
of gates very simple.
More complex gates can
be built by cascading the standard pass-transistor
modules.

(iv) Simple Logic

ate is Style
CPL is a conceptually simple and modular logic style. It depends strongly on
the
logic function to be implemented. Simple XOR
makes it attractive for structures
like adders and multipliers.

6.1.6 Advantages of PTL

The advantages
ofPTL are:
1) Fast switching speed.

(i) Reduced number of required transistors.

(iii) Lower capacitance.

(iv) AlBoolean functions can be implemented.
(V) Simple design.
(vi) Less static power dissipation problems.

POWER DISSIPATION
power dissipated in
a
CMOS
extra components that can establish the amount of

circuitare,
 VLSI and Chip Design

6.10

Dissipation current drawn from the power

(1) Static Power leakage
dissipation is due to -the
O Static
power power is due to:urie
OFF transistor. Static
through the
supply, normally ort o
through OFF transistor. orajen
- Subthreshold leakage

leakage through gate dielectric.

-Gate snT
-Junction leakage from
source/drain ditfusions. q9v 2 Esh
current ratioed circuits. i,25 (osne) bo5iri3
-Contention in
as,
dissipation is expressed
Then, the total static power
Vpp
Pstatic sub t gate t junct +Icontention)

Dissipation
(2) Dynamic Power discharge an
circuit switching to charge and
Power dissipation is due to the
at a particular node at an operating
frequency is called
output load capacitance

Dynamic power dissipation. It is mainly due to the following:

as gates switch.
Charging and discharging of load capacitances
are partially ON:
" Short-circuit" current when both pMOS and nMOS
as,
Then, the total dynamic power dissipation can be expressed

P dynamic
= P Switching short circuit
...(2)

(3) Total power Dissipation

Based on equations (1) and (2), the total power dissipation is expressed as,

P total. = Pdynamic +P.static ...(3)

6.3 DYNAMIC POWER DISSIPATION

6.3.1 Dynamic Power Dissipation Due to Switching: Charging/
Discharging
COnsumed
In practice, the dynamic power dissipation power
is dominated by the
by both charging and discharging
of the load capacitor.
 Logic
Pass -Transistors
6.11

VoD

Vin Oo Vout /

Fig 6.6 Power dissipation due to charging/discharging

of load capacitor in CMOS inverter

& During switching to 0) state, both nMOS and pMOS transistors are
(0 tö 1 (or) l
ON for a short period of time. This causes a short current pulse from Vpp to
.
Vs In order to charge and discharge an output capacitive load, the current is
also required.

Vpp -Vout Rp
i(t)

Vout
+

in(t) Vout
Vout Rn
dVout
iG(t) = CL
dt

Fig 6.7 Circuit model for Fig 6.6

Fig 6.7 shows the circuit model used for CMOS inverter which is used to
calculate the dynamic power dissipation during charging and discharging a load
capacitor. The related timing diagram is shown in Fig 6.6.
 VLSI and Chip Design
6.12
Vin

TI2 T
0

Vout A

estimating the dynamic

Fig 6.8 Timing diagram for
power dissipation of a CMOS inverter
a
Assume that an input signal is
a square wave with voltage V,, and has repetition
an average dynamic power
frequency off, = 1/T, as shown in Fig 6.6. Then,
at both nMOS and pMOS transistors
dissipation Patcla) [charge and discharge]
can be calculated as follows:

TI2 T

Pacl)
0 TI2

VpD
dV out
dt + i,() =
=
T out
dt -C dt

VpD
d(Vpp-Vou) d(Vpp-Vou
T
(Vop-V out) dt i,() = CL
0
dt dt

YDD Vpp
| Vout dVout t (Vpp-Vout) d(Vpp-V ou)
T
 Logic
Pas -Transistors 6.13|

Palcld) T •.. (1)

where, average gate switching frequency =

f =fw af and f is called as an
operating frequency.

4 Equation (1) represents that the dynamic power dissipation is due to the charging
and discharging which is proportional
to the square of supply voltage and
linearly proportional to both loading capacitance and an operating frequency.

For a repetitive step input the average power that is dissipated is proportional to
an energy required to charge as well as discharge the circuit capacitance.

Energy =
C, V ... (2a)
DD

* Theaverage power is proportional to the switching frequency. It is more

convenient to express switching frequency fou as an a times the clock
frequency f.

P = Vpp ... (26)

afC
2 Reductions of Dynamic Power Dissipation:
Dynamic power dissipation due to charging/ discharging of loadcapacitance can
be reduced by decreasing the activity factor (a), switching capacitance (C), the
power supply (Vpp) and an operating frequency (1).

O.3.2 Dynamic Power Dissipation Due to Short Circuit Current

Uuring switching, both nMOS and pMOS transistors will conduct simultaneously
and provide a direct path between VpD and the ground rail resulting in short
circuit power dissipation.
current inan
S simply the power dissipation which is due toshort circuit
as,
unloaded inverter is called as short circuit dissipation and it is denoted
 VLSI and Chip Design
6.14|

K (Vam-2 V,)
.. (3)
Posog

where, , is period of input

waveform, and

K isa constant.
to the
short-circuit power dissipation is linearly proportional
Consequently, the
times of
an input signal. To reduce this, both rise and fall
rise and fall times of
as
an input signal should be made as small possible.
DynamicVoltage/
6.3.3 Dynamic Voltage Scaling (DVS) [OR]
DFrequency Scaling (DVES)ik
a Definition of DVS
Dynamic Voltage Scaling (DVS) is a power management technique in computer
or
architecture, where the voltage used in a component is either increased
decreased, depending upon circumstances.
DVS is used to increase voltage is known as overvolting whereas DVS is used to
decrease voltage is known as undervolting.

Undervolting is done in order to conserve power, particularly in laptops and

other mobile devices, where energy comes from a battery and
thus is limited.
The term "overvolting" is used to refer to an
increasing static operating voltag"
of computer components to allow operation at higher
speed.uot Ay

Switching
SV Voltage
2197 ,2 orie Voltage Control Regulator

VoD

Freg Control
DVS
Work load
Controller Core Logic
Temperature

Fig 6.9 DVS system

Pass -Iransistors Logic
6.15
Bioure 6.9 shows a bl0Ck diagram for a basic DVS system. The DVS
controller
takes an information from the system about
theworkload and/or the die
temperature.

It determines the supply voltage and clock frequency

which are sufficient to
complete the workload on schedule (or) to maximize
performance without
overheating.
& A switching voltage regulator efficiently steps down V, from a high value to the
necessary VDD. The core logic contains a
phase-locked loop (or) other clock
synthesizer to generate the specified clock frequency.

4 The DVS controller determines an operating frequency, then chooses the lowest
supply voltage which is suitable for that frequency. One method of choosing the
voltage is with a precharacterized table of voltage vs frequency.

6.4 STATIC POWER DISSIPATION

6.4.1 Introduction
Vop VoD

pMOS pMOS

Vn=0 Vin=1

NMOS nMOS

Fig 6.ioCMOS Inverter mode for static power consumption

Consider the CMOS inverter shown in Fig 6.10.

) When input V,, =0, nMOS -OFF and.pMOS ON.

-
voltage, Voutlogic 1' (or) Vpp.
Then, an output voltage,
 VLSI and Chip Design
6.16|
=
1, nMOS -ON and pMOS -OFF.
(ii) When input V,
(or) Vss(GND)
Then, an output voltage,
Vout
0V
logic gates. One of the transistors is alwavs
these
o When the gate is in either of zero.
no current path from Vpp to Vss, the power is
"OFF, since there
Vin

Vout
o
VpD
(GND) |G

D s
nt

p - WELL n -WELL
D4

n -
SUBSTRATE

Fig 6.11 CMOS inverter model for describing

prasitic diodes
Due to the reverse bias leakage
between diffusion regions and the substrate,
there
is some static power dissipation.
The sub threshold conduction is also contribute
to the static dissipation.

In the above model,

the diode D, is a parasitic
These parasitic diode between p-well to
diodes are reverse biased subsue
and only
contributes to
static power dissipation. their leakage Crent
This leakage current
diode equation as, is described by the

... (1)
where, I, - Reverse saturation
current.
V- Diode voltage.
 Pass IranSistors
Logic
6.17
q - Charge of an electron.
k - Boltzmann'sconstant.
T - Temperature.
The static power dissipation is the product
of device leakage current and the
supply voltage.
-M:
P.
static leakage current x supply voltage (Vpp)
1

... (2)
Pstatic L,ub
t gate + ;punct t contention VDD

where, n - Number of devices.

(1) Reduction of Static Power Dissipation:
The static power dissipation can be reduced in the following ways:
) By selecting multi threshold voltages on circuit paths with low-V,.
transistors while leakage on other paths with high-V transistors.
(ü) By using two operating modes, active and standby for each function blocks.
(i) By adjusting the body bias that is adjusting FBB (Forward Body Bias) in
active mode to an increase performance and RBB (Reverse Body Bias) in
standby mode toreduce the leakage.
:
S Variable Threshold CMOS (VTCMOS)
To achieve high active mode and low ofr in sleep mode is to dynamically
Iin
adjust the threshold voltage of the transistor by applying a body bias. This
echnique is sometimes called variable threshold CMOS (VTCMOS).
) By using sleep transistors to isolate the supply from the block to achieve
significant leakage power savings.
6.4.2
Power Gating
Definition of Power Gating:

to turn off the

e
easiest way to reduce static current during sleep mode is
power gating.
ower
supply to the sleeping blocks. This technique is called
 VLSI and Chip Design
6.18

Header switch
VDD transistors

Sleep
Sleep
Vppv
Outputs

Inputs
Power
o00
Gated
Block

Output
isolation

Fig 6.12 Power gating

power from a virtual VDD rail, Vppy.
h In Fig 6.12, the logic block receives its
When the block is active, the header switch transistors are ON, connecting Vppy

to VoD.

When the block goes to sleep, the header switch turns OFF and allowing Vppy to
float and gradually sink towards 0. As this occurs, the outputs of the block may
take the voltage levels in the forbidden zone.

# The output isolation gates force the outputs to a valid level during
sleep so that
they do not cause problems in the downstream logic.

Power gating introduces a number of

design issues. The header switch requires
careful sizing and it should add
minimal delay to the circuit
during actve
operation, and should have
low leakage during sleep.
The transition between
active and sleep modes
takes some time and energy,
the power gating is only
effective when a block is turned
off for long time.
6.5 LOW POWER DESIGN
PRINCIPLES (OR)
TECHNIQUES
Low power design
becomes an important
improvement in semiconductor design constraint the
technology. The dynamic due t0
proportional to,
power dissipation is

() Activity factor a.

(i) Switching capacitance

C.
 s-Transistors Logic
Pass
6.19|

(i) Operating frequency f.

(iv) Supply voltage Vpp,

Step-by-Step Design Procedure is

The
# given as follows:

1) Transistor Size:
Thetransistor size should be reduced so
that the number of transistors that can
fit on a chip can be increased. process
The manufacturing should be first
selected to minimize the size of transistor to
provide narrow channel width.
This inturn lowers the capacitance the channel,
of then
Static power increases as threshold voltage decreases.

Expensive.

It isnecessary to provide tradeoff between power and cost.

(2) Reduce the Supply Voltage:

Voltage has a quadratic effect on dynamic power. Therefore, choosing a lower

power supply significantly reduces the power dissipation.

For example, reducing Vpp from 2.5 V to 1.25 the power dissipation
V, then

drops from 5W to 1.25 W. This is assume that the same clock rate can be
sustained.

This further reduces the speed for advanced processes. The voltage and clock
frequency can also be adjusted to save power.
(3) Higher and Lower Power Groups:

O Divide the logic into higher speed and low power groups and operating from
can also be embedded in each logic
Separate power supply. Dual supply rails
cell.

ast logic is connected to high supply and slow logic is connected to the low
two logics.
Supply. Level conyerters can also be inserted between these
 VLSI and Chip Design
6.20|

power and area. The low Vpn celle

These level converters increase the delay,
the level converted to
are grouped at the end of each cycle of logic and

This is called Clustered Voltage Scaling.

(4) Reducing the Switching Capacitance

switching capacitance. The
Low power operation aims at reducing the
diffusion capacitance and
Switching capacitance consists of gate capacitance,

wire capacitance.
which minimizes the
Gate capacitance can be reduced by good floorplanning

number of
long wires in a system.

turn
Diffusion capacitance can be reduced by providing good buyout which in
minimizes the size of
the diffusion regions.

Custom layout of data paths and arrays provides shorter wires and lower
capacitance.

(5) Reducing Power Dissipation

o The activity factor (c:) is used for reducing the power dissipation. The high

activity factor indicates more power dissipation.

Logie Activity factor

Complementary CMOS 0.1

Dynamic Logic
0.5

Clock 1

Table 6.1 Activity factor for various logic

circuit
The clock signal is gated to the registers in unusedunits.
This saves power
the entire device.

Dynamic and pseudo-nMOS gates have low power dissipation because they
eliminates the bulky pMOS
in complementary CMOS and pass transistor
circuits are also efficient due to their low power consumption.
 Pass
Iransistors Logic

6.21|
TWO MARKS QUESTIONS
6.6 AND ANSWERS
1. What is PTL?
T. Dass
Transistor Logic (PTL),
the transistors are used as
switches to pass logic
levels between the nodes of a circuit,
instead of those switches
to supply voltages. connected directly
This reduces the number of transistors
which is used to make
different logic gates
by eliminating the redundant transistors.
2hy nMOS device conducts strong zero
and weak one? [NOVDEC-2018)
A nMOS transistor is an almost perfect swicth when
passing a 0 and thus we say
it passes a strong0 but acts as an imperfect
swicth at a passing 1. Because high
voltage level is somewhat less than Vpp
because of threshold effect
(Vo=Vpp– VTH) and we say it passes a degraded or weak 1.
Example: when Vpp is 5V,but in weak 1 we may get 4.4 V
3../ Why nMOS transistor is selected as pull down
transistor? [NOVDEC-2017|
In CMOS pull up is nMOS transistor and pull down is pMOS transistor. When
logic 1 is applied as input, nMOS transistor turns ON and pMOStransistor turns
OFF. Hence, the output should get charged to VpD.

But due to threshold voltage effect, nMOS is not capable of passing VDD for good
logical 1 at the output that is Vo = VpD - VTH(degraded 1). Hence, the output
should get discharged to ground level.

4 Name some of the PTL families.

The Pass Transistor Logic (PTL) families are,

i) .Complementary Pass-transistor Logic (CPL).

Logic(SRPL).
(1) Swing Restored Pass-transistor
(iii) Double Pass-transistor Logic (DPL).
Gate Logic(DCVSPG).
(iv) Differential Cascode Switch with Pass
 VLSI and Chip Design
6.22
overcome CUSL drawback?
5. How CPL as the
Logic(CVSL) uses a pMOS cross-coupled latch
Cascode Voltage Switch due
as fast as expected because it cannot be easily inverted
load, it cannot work
to the regenerative property of the latch.
overcome by the Complementary Pass-transistor
This drawback can be
one half of the gate pulls up
Logic(CPL) which resolves this problem by making
while the other half pulls down.

6. Define CPL.

The term "Complementary Pass-transistor Logic" (CPL) is used to indicate a

style of implementing logic gates where each gate consists
of a nMOS-only pass
transistor network, followed by a CMOS output
inverter. Hence, the pMOS
cross-coupled latch can be removed.

7. Write the
properties of CPL.
The properties of CPL are:

() Diferential
Complementary
data inputs and outputs
inverters are required). are always
available (so no extra
(ii) Static Gate
CPL belongsto
the class of
always tied static gates,
to VDo (or) because
GND through the output defining
for the noise
resilience.
a low resistance nodes are
path. This
(ii) Modular is advantageou
Design
The design
isvery modular,
permutated all gates use
(varied). the same
More This makes topology,
complex the design
gates can only the
modules. be built of a
library inpuls
by cascading of gates very simple.
the standard
pass-transistor
 Pass -Transistors Logic
6.23
(iy) Simple Logic Style

CPL s a conceptually simple and modular logic style. It depends strongly on the
logic function to be implemented. SimpleXOR
makes it attractive for structures
like adders and multipliers.

8.
List the types of power dissipation.
NOVDEC- 2017, APRMAY-2018]
(or)

State the various types of power dissipation.

APR/MAY- 2017]
There are two components that can establish the amount of power dissipated in a
CMOS circuit. These are,

(1) Static power dissipation, and

(ii) Dynamic power dissipation.

9. What do you mean by static power dissipation?

power
Static power dissipation is due to the leakage current drawn from the
power is due to:
supply, normally through an OFF transistor. Static
Subthreshold leakage through OFF transistor.
dielectric.
Gate leakage through gate
diffusions.
Junction leakage from source/drain
circuits.
Contention current in ratioed
power dissipation.
10. State the reasons for dynamic an
to the circuit switching to charge and discharge
Power dissipation is due called
capacitance at a particular node at an operating frequency is
output load
power dissipation. It ismainly due to the following:
Dynamic
discharging of load capacitances as gates switch.
Charging and
nMOS are partially ON.
Short-circuit" current when bothpMOS and
 VLSI and Chip Design
|6.24|
power dissipation?
11. How to reduce the dynamic
is expressed as,
The dynamic power dissipation
V
Pa afC,
can
to charging discharging of load capacitance
Dynamic power dissipation due
activity factor (a), switching capacitance (C), the
the
be reduced by decreasing
frequency ().
power supply (Vpp) and an operating

12. Define DVS.

management technique in computer
Dynamic Voltage Scaling (DVS) isa power or
a component is either increased
architecture, where the voltage used in
decreased, depending upon circumstances.

DVS isused to increase voltage is known

as overvolting whereas DVS is used to.
decrease voltage is known as undervolting.

13. List the way toreduce the static power dissipation.

The static power dissipation can be reduced in the following

ways:

(i) By selecting multi threshold voltages on circuit paths with low-VT

transistors while leakage on other paths with high-V, transistors.
(i1) By using two operating modes, active and standby for each function
blocks.

(ii) By adjusting the body bias that is adjusting FBB (Forward Body Bias)
in active mode to an increase performance and RBB (Reverse Boay
Bias) in standby mode toreduce the leakage.

H Compare static and dynamic power dissipation. [ NOVDEC -2019)

Sr. No Static power dissipation Dynamic power dissipation
1. It is due to the leakage. current
It is due to the circuit switching
o
drawn from the power
supply, charge and discharge an output
normally through the OFF load particula
capacitance at a
transistor.
node at an operating frequency.
 Pass--Transistors
Logic
6.25|
It is reduced by
2. using two It can be
reduced by decreasing
operating modes, active
and the activity factor
standby for each function blocks. (.), switching
capacitance (CL), the power
supply (VDD) and an operating
frequency (f).

5. What is power gating?

The easiest way to reduce static current during sleep mode is to

power supply to
tun off the
the sleeping blocks. This technique is called power gating.

6.7 REVIEW QUESTIONs

. Explain
the Pass- Transistor Logic (PTL).
[NOVDEC-2020 &APRMAY-2021
2 Brief about Complementary Pass-transistor Logic (CPL) with examples and
also discuss its properties.

3. Discuss the low power design principles in detail. NOVDEC- 2017]

4 Derive anexpression for dynamic power dissipation.
APR/MAY- 2018, APR /MAY- 20191

J. Write note on DVS.

O
DiscuSs about static power dissipation in detail.
Explain the static and dynamic power dissipation in CMOS circuits with
hecessary diagrams and expressions. [APR/MAY- 2017]
8, CMOS? Discuss various
What are the sources of power dissipation in
techniques to reduce power dissipationin CMOS. [APR/MAY- 2016]
9. CMOS. Derive an
State
the diferentcomponents of power dissipation in
expression for the dynamic power dissipation. [NOV/DEC- 2019]
10. Write a
note on power gating.
11.
Brief about
low power design principles.
 SEQUENTIAL LOGIC
UNIT
CIRCUITS AND
CLOCKING STRATEGIES

Chapter 7
SEQUENTIAL LOGICCIRCUIT DESIGN

7.1 INTRODUCTION

In combinational logic circuits, an output is a function of the current inputs,

whereas, in sequential logic circuits an output depends upon both the current
inputs as well as previous inputs.

*lt requires memory to store the previous input values, called states. In this
circuit, an output is given as feedback to the input. So, these circuits are called
regenerative circuits. Example: Registers, Oscillators, Counters etc.

Inputs Outputs
Combinational
circuit

Memory

Fig 7.1 Sequential Circuit

7.2 VLSI and Chip Design

as a
Fig 7.1 shows the block diagram of sequential circuits. It can be treated
Finite State Machine (FSM) that consists of combinational logic and registers.
which stores the system state information.
a outputs of
Here all registers are under the control of single global clock. The
state.
the FSM are a function of the current inputs and the çurrent
current inputs and
The next state is determined based the current state and the
on

it is fed in to the inputs of the registers.

Combinational Outputs
Inputs
logic
circuit

Current Next
state state

Registers

CLK

Fig 72 Block diagram

of
FSM

a Comparisons between Combinational and Sequential LogicCircuits:

S.No Combinational Circuits Sequential Circuits

The output depends on the The output depends on the current
1. input and previous input values.
current input values.

2. Non-Regenerative circuits. Regenerative circuits.

3. Nomemory unit required. Has memory unit.

Used to construct a Finite State
For designing logie, basic gates Machine (FSM) that consists of
4 (AND, OR, NOT) or universal combinational logic and registers,
gates (NAND, NOR) are used. which stores the system state
information.
Examples: Half adder, Full Examples: Registrs, Oscillators,
5.
adder, Encoder, Decoder. Counters.
 Seguential. Logic Circuit Design

|7.3|
rising edge of the clock, the next
On the
state bits are
registers (after some propagation copied to the outputs of the
delay), and a new
cycle begins. The register
then ignores the changes in the input
signals until
the next rising edge.
Deoisters can be
the rising edge of
posiive edge triggered registers the - input data is copied on
the clock (or) negative edge
triggered registers - theinput
is copied on the falling edge data
of the clock.
1.1Classification of Memory Elements
The memory elements can be classified as follows:

(1) Foreground and Background Memory

At ahigh level, memory is classified into background and foreground
memory. Memory embedded into logic is called foreground memory. It is

organized as individual register (or) register bainks.

o
Large .amounts of centralized memory core are referred to as background
memory. It achieves higher area densities through efficient use of array
structures.

(2) Static and Dynamic Memory

or memories will preserve the
Memories can be either static dynamic. Static
OM. It can be built using positive
(or)
state as long as power is turned updated for
feedback. It is used when the register need not be
regenerative
extended periods of time.
to store data for a short period of time (order
O Dynamic memories are used storage on parasitic
on the temporary charge
are based
of ms). These capacitors have to be refreshed
periodically,.
The
capacitance MOS devices.
of
B) Latches and Registers used sequencing elements. Both
are two commonly data
The latches and flip-flops input (D), clock (CLK) and
terminal device i.e. data
have three
output (Q).
 VLSIand Chip Design
|7.4)
component in the construction of an edge-triggerod
A latch is an essential
bistable circuit that passes the D input to
register. Latches is a level sensitive
(CLK) signal is HIGH.
the output when the clock
transfers the input value to output when the clock is HGH
Positive latch
holds the previous state. Similarly, a negative latch
When the clock is LOW, it
clock signal is LOW.
passes the D input to the Q output when the

Ir D Out
In D -Out

JcK CLK

(a) Positive Latch (b) Negative Lateh

Fig 7.3
a Register:
a register. i.e., the input is
An edge triggered storage element is called
transferred to the output at the edge
of
clock signal.
1 transition
Positive edge triggered register: 0
Negative edge triggered register:
1 0 transition
The word “ register" often means memory elements in digital systems. A

master - slave structure combines both positive and negative latch.

a Flip-flop
A latch or flip-flop is a device that is capable of storing -bit information. A

register is a device that consists of a specific number of flip-flops.

To be more specific, an n -bit register contains n flip-flops. Hence,a flip-ilop
isa single bit register.
7.2 STATIC LATCHES AND REGISTERS
7.2.1 Bistability Principle
Static latches use positive feedbackso that bistable
circuit can be formed. I
two stable states that represent
0 and 1.
 Syential Logic: Circuit Design

Two inverters are connected

in cascade
75
to form a
basic bistable circuit
in Fig 7.4. as shown

Vo2

Vo2 = Vi1

Fig 7.4 Two cascaded inverters

4) Voltage-Transfer Characteristics (VTC):
The VTCof the first inverter
.i.e. Vol versus V is given in Fig
7.5 (a) and the
second inverter i.e. Vo2 Versus V2 is
given in Fig 7.5 (b). This is plotted by
considering that Vi2 =Vol

Vot

=
Vi2

Vi1 (b) Voz

(a)

JA
Vo1

=
Vi2

Vi1 = Vo2

(c)

of twocascaded inverter
Fig 7.5 VTC
 VLSIand Chip Design
|7.6|
to the
assume that the output of the second inverter Vo2 is Connected
Now,
inverter Vi., as shown by the dotted lines in Fig 7.4.
input the
of first
showe
two cascaded inverter (basic bistable element)
The resulting VTC of
is shown in Fig 7.5 (c).
three pössible operating points
curves intersects at three points(A, B, and C)
.Ifthe
The two voltage transfer
will remain in its state unless forced
operating at any stable point, it
Circuit is
externally to change its operating point.
required
operating point a sufficiently large external voltage is
To change its
greater than unity.
to make voltage gain of inverter loop
small
cross- coupled inverter pair is biased at point C. A
Suppose, this
from this bias point is caused by noise. It is amplified and
deviation
the circuit loop. As a results, the gain around the loop
regenerated around
being larger than 1.
a metastable
the only stable operation points, and is
C
Now, A and B are
every deviation (even the smallest one)
operating point. Metastable means
causes the operation point to run away fromits original point.
a
The cross coupling of two inverters results in bistable circuit that
is a circuit
serves
with two stable states, each corresponding to a logic state. The circuit
as a memory, storing either
al (or) a 0.

7.2.2.Multiplexer-Based Latches
-The feedback is removed in the bistable circuit and a new input value can be

easily written into output (Q). Such a latch is called multiplexer based latch,
it realizes that the logic expression for a synchronous latch is identical to
multiplexer expression. The logical expression
is written as,
Q = CLK
0+CLK. In
Thetransmission gate multiplexers are used the
to build a latch. Fig 7.6 shows
implementation of positive and negative
static latches based on multiplexXeI
 Seguential1Logic Circuit Design

7.7

D
0 D

CLK
CLK
(a) Negative latch
(b) Positive latch

Fig 7.6 Latches based on multiplexers

() Negative Latch
For a negative latch

(a) When clock (CLK) =

LOW, input 0 is selected and the D input is passed to the
output.

(6) When clock = HIGH, nput 1 is connected to the output of the latch., Then the
feedback ensures a stable output as long as the clock is HIGH.
(ü) Positive Latch

(a) When clock = LOW, the output signal is feedbackto the input.
and passed to the output.
(b) When clock = HIGH, the D input is selected

4) Transistor- Level Implementation

implementation of a positive latch based on multiplexers
A transistor -level
using transmission gates is
shown in Fig 7.7.
latch is
bottom transmission gate M, is ON and
When CLK = HIGH. the since
to the output. There is no feedback
ansparent that is, D input is copied
OFF
top transmissión gate M, is
considering the power.
not very efficient while
This latch implementation is
transistors to the CLK signal,
equivalent of four
provides a load
 VLSI and Chip Design
|7.8

CLK

M1

CLK

D
M2

T
CLK

Transistor-level implementation ofa positive latch based on multiplexer

Fig 7.7
Latch
(2) Multiplexer based NMOS pass
implementing multiplexer-based NMOS latch by using NMOS-only
By
transistors is shown in Fig 7.8 which reduces the
clock load as two
transistors.
CLK

QM

D QM

CLK

Fig 7.8Schematic multiplexer based on NMOS latch

When CLK is HIGH, D input is sampled and passed to the output. w

hold
CLK is LOW, feedback loop is enabled and the latch will be in the
mode.
in
This simple circuit but the use of NMOS-only pass transistors results
is a
the passing of a degraded high voltage of Vpp the first
-V, to the input ofSwitching
inverter. This will affects both
the noise margn and the
performance.
Seguential Logic Circuit Design

79

CLK

CLK

Fig 7.9Non overlapping clocks

7.2.3 Master-Slave Edge- Triggered Register

4 The most common approach for constructing an edge-triggered register is to use
a master- slaveconfiguration as shown in Fig 7.10.

Slave
Master

aM
D

CLK

CLK

on a Master- slave configuration

edge-triggered register based
r'g 7.10 Positive with a positive latch
of cascading a
negative latch (master)
Ihe register consists in this particular
implementation,
multiplexer -based latch is used
(Slave). A
used.
although any latch could be D input
is passed
conducts and the
master latch
the mode
When clock signal is LOW, period, the slave is in
hold
QM. Duringthis
to the output of master,
the feedback.
holds the previous value through sanplingthe input, and the
master slave stops
clock, the
On the rising edge of the
Slave stage starts sampling.
 VLSI and Chip Design
7.10
to
When the clock signal is HIGH, the master stage is OFF and the slave begins
conduct. The slave follows the output of master, QM and the master stage will be
in hold mode.
slave
The output of master QM is constant during HIGH' value of clock and the
produces output at Q only one transition per cycle.
which
The value of Q is the value of right before the rising edge of the clock,
D

is achieving the positiveedge- triggered effect.

as slave, then we
If the positive latch is used as master and negative latch is used
can construct a negative edge-triggered register.

CLK

Fig 7.11Output waveforms of

master-slave configuration

(1) Master-slave Positive Edge -Triggered Register Using Multiplexer

1

|QM

CLK

Fig 7.12 Master-slave positive edge-triggered register, using multiplexers

Sequential. Logic Circuit Design
|7.11
A
Complete transistor-level
implementation of the master-slave
triggered register is shown in Fig 7.12. positive edge

(1) When the clock is LOW

CLK =1), T, is ON and T; is
OFF, and the D
input is sampled onto a node OM.
During this period, T3 and T4 are OFF
and ON, respectively. The cross-coupled
inverters (Is, I6) hold the state
of the slave latch.
Gi) When the clock is HIGH CLK =
0), the master stage stops sampling
the input and goes into a hold mode. Ti is
OFF and T is ON, and the
cross-coupled inverters I, and I; hold the state .
of OM Also T3 and T4
are ON and OFF, respectively
and QM is copied to the output Q.
7.2.4 Low -Voltage Static Latches
The supply voltages are scaled to operate in low-power mode. But some
latches
will not function at reduced supply voltages.

At very low power supply voltages, the input to the inverter cannot raised above
the switching threshold, it will result in an incorrect output. Thus the threshold
voltage should be scaled properly.

Multiple threshold devices can be used to eliminate high leakage during idle
periods.
(1) Multiple -Threshold CMOS
A multiple threshold device of negative latch is shown in Fig 7.13. Here.
as
shaded inverters and the transmission gates are implemented low-threshold
devices. Then, the low-threshold inverters are gated by using high-threshold
devices in order to eliminate leakage.
are turned ON. When
During the normal mode of operation, the sleep devices
the clock is LOW, the D input is sampled and
propagates to the output. The
clock is HIGH.
latch is will be in the hold mode when the
crosS-coupled feedback is
The feedback transmission gate conducts and the
extra inverter, in parallel with the low- threshold is added to store
enable. An
sleep (idle) mode.
the state when the latch is the
in
 VLSI and Chip Design
|7.12|

VpD

VoD VpD

sLEEPHigh Vr
SLEEP High V CLK

D Q

SLEEP
HighV
SLEEP High V
CLK CLK

VDD

Fig 7.13 Multiple-threshold CMOS

Now, the high-threshold devices in series with the low-threshold inverters are
turned OFF, when the SLEEP signal is HIGH and eliminating leakage.

It is assumed that CLK is held HIGH when the latch is in the sleep state.
Thus, the feedback in low-threshold transmission gate is turned ON and the

cross-coupled high-threshold devices maintain the state of the latch.

7.2.5 Static SR Flip-Flops

(1) NOR Based SR Flip- Flops
a
The simplest SR (or) Set -Reset flip-flop can be implemented by using
cross-coupled NOR gates and it is shown in Fig 7.14.
outputs
When both are 0,
state and both
S
and R
the flip-flop is a
in quiescent
Q
retain their value. If a positive pulse (or) 1 is applied to the S input, the
output is forced into the 1 state with going to 0 and vice versa.
 Circuit Design
Sequentia! Logic
|7.13

Inputs Outputs
R

1 1

RQ
1 0
R Forbidden
41 1
state

(a) Schematic Diagram b) Logic Symbol (c) Characteristic Table

Fig 7.14 NOR-based SR flip-flop

o A l-pulse is applied on R and Q output goes to 0. When both S and R are
HIGH, both Q and O are forced to zero, that is Q and are complementary
and this input mode is considered forbidden.

A Characteristics Table:

The characteristics table is the truth table of the gate and lists the output states
as the functions
of all possible input conditions.
2) NAND Based SR Flip- Flops

R Q

(b) Logic Symbol

(a) Schematic Diagram

SR flip-flop
Fig 7.15 NAND-based
The circuit S and R
inputs:
responds to active low

goes to 0 (while R
=1), Q goes HIGH, pulling LOW and the
IS
lip-flop enters the Set state.
goes HIGH, pulling Q
LOW and the flip-
goes to 0 (while S
=1),0
Ilop enters the Reset state.
 VLSI and Chip Design
7.14

IfS= R= 0, this
ie
same states willbe hold.
When both S and R to be HIGH.
an state.
not allowed, it would result in indeterminate
Q
R
1 1 No change

1
1 0

1
1

Invalid

Fig 7.16 Truth table of NANDbased SR flip flop

7.3 DYNAMICLATCHES AND REGISTERS

7.3.1 Introduction
Drawbacks of Static Latches:
The stored value remains valid as the supply voltage is applied to the circuit
in static latches. But the main drawbacks are:

() Its complexity.

(i) When registers are used in computational structures that are constatly
clocked.
(i). fthe memory requires holding state
for extended period of time, then
static latches cannot be used.
Dynamic gates are used
to decrease complexity, increase speed and low power
dissipation.
In dynamic latches, the charge is stored on
parasitic capacitors temporarily•
the charge is present it represents
represent 0.
1' and if charge is absent, u
A Dynamic Register

Due to charge
leakage in capacitor, amount
the charge is stored a limited
of time
(order of ms). The
capacitor should be
for
obtain
signal integrity. periodically refreshedto
Soit is called as
dynamic storage.
 Saguenitial'ILogic
L Circuit. Design

7.15
There are three types of dynamic registers.
Dynamic Transmission-Gate
Edge- Triggered
Register.
(i1) Clocked CMOS(CMOS)
Register.

(i)
. True Single- Phase Clocked Register
(TSP CR).

73.2 Dynamic Transmission-Gate

Edge-Triggered
Registers
A dynamic transmission gate positive
# edge-triggered register based on
master-slave concept is shown Fig 7.17. the
in
.In the Fig 7.17 l and l2 are transmission gates
and I, and I, are inverters,
C and C2 are equivalent capacitances at node-I and
node-2.
(i) CLK= 0

Transmission gate T, is ON and T, is OFF.

Input data D is sampled on storage node 1, which has the equivalent
capacitance C, consisting the combination of gate capacitance of Ij, junctión
capacitance of T; and the overlap gate capacitance of T,.
During this period, the slave is in a hold mode and node 2 is in high
impedance (floating) state.

CLK CLK

A
B
<HH
D : T;
HH

CLK
CLK
Slave
Master
positiveedge- triggered register
Fig 7.17 Dynamic
i) CLK=1
gate T, is ON and T, is OFF.
On the Tising edge of clock, transmission
1 at CLK = 0
is propagated to the
Hence, on node
the value sampled
output Q.
node-1.
Thus, node -2 stores the inverted value of
 VLSI and Chip Design
7.16

A Setup Time
this circuit is simply the delay of the transmission gate and it
The setup time of
to sample the D input.
corresponds to the time taken by node -l

A Propagation Delay
the
equal to two inverter delays plus the delay of
The propagation delay is
transmission gate T;.
Advantages
transistors. E
implementation is achieved due to the use of only eight
() efficient
An

implementation is
pass transistos are used, then six-transistor
NMOS-only
achieved.
low power systems.
(i) Used in high performance and

7.3.3 Clocked CMOS (CMOS) Register

size
to reduce power dissipation and layout
Clocked CMOS (CMOS) is used
and to increase speed.
VpD
VpD

M2 M6

CLK CLK
M4 Mg
X Q
D
CLK
M3 M7 HH CL2
CLK

M, M5

Master Slave

Fig 7.18CMOS master-slave positive edge-triggered register

 Circuit Design
SequentialLogic 7.17
7.18 shows a positive edge-triggered register based on
Fig the master-slave
concept which is insensitive to clock overlap. This also circuit is called C'MOS
register.

CLK=0 (CLK =1):

0
Master stage is ON and acts as an inverter.
i.e., it samples the inverted input
D on
the internal node X. This is called evaluation mode.
whereas the slave is
in a bold mode (or) high impedance mode.

o In Slave stage, M, and M, transistors are OFF,

decoupling the output from the
input. The output Q retains its previous value
stored on the output capacitor
CL2.

(ü) CLK = 1

o
The transistors M, and M, are OFF and the master is in the
hold mode. The
transistors M, and M, are ON and the slave is said to be in evaluation mode.

The value stored on capacitor C, is transmitted to the output node through the

slave stage, which acts as an inverter. The output on Q

is actually an inverted
form of input.

o A C'MOS register with CLK & CLK clocking

is insensitive to overlap, as
long as the rise and fall times of the clock edges are sufficiently small.
7.3.4 True
Single - Phase Clocked Register (TSPCR)
To avoid
the overlap of two-phase clocking schemes, a single clock is
used in the
true single
phase clocked register. There are two types of latches.

) Single phase positive latches.

1) Single phase negative latches.

) Single Phase
Positive Latch
o
Figure
7.19 shows the single phase positive clocked register which uses a
single CLK
signal.
 VLSI and Chip Design
7.18
(0) CLK = 1
VpD
When CLK is HIGH, the VpD

latch is in the transparent

mode and it is cquivalent OIP
CLK
to two cascaded inverters.
WP
CLKI|
no
So, thc output is
inverter formof input.

(iü) CLK= 0
Both inverters are in OFF
condition and the latch is in positivelatch
Fig 7.19 Single phase
hold mode. Only the pull-up
networks are still active, while
are deactivated. As a result of the dual-stage approach,
the pull-down circuits
input of. the latch to the output in this
from the
no signal can ever propagate
mode.

(2) Single Phase Negative Latch

VDD VpD

UP CLK

O/P

Fig 7.20 Single Phase Negative Latch signal

CLK
use a
single
Fig 7.20 shows the single phase negative latch which
Signalis
clock
It is similar to the single phase positive latch except that logic
TPSCR has possibility of embeddíng
applied to pMOS transistor.
functionality into the latches.
Sequential Logic Circuit Design 7.19

Cascading Positive and Negative Latches

A register can be constructed by cascading positive and negative latches.
(3) Adding Logicto the TSPC Approach
Fig 7.21 outlines the basic approach for embedding logic with a latch.
Fig 7.22 shows the positive latch which implements AND logic.

VpD VpD

PUN

In CLK

PDN

Fig 7.21 Including logic into the latclh

Vop
Vop

Qut
CLK
CLK

Positive latch

ANDgate

Fig 7.22 AND logic using apositive latch

 VLSI and Chip Design
|7.20|

Advantages
are,
The advantages of TSPCR
clock phase to avoid overlap.
) Using single
latches.
embedding logic functions into the
(i) Possibility of with thè latches is
reduced.
overhead associated
(ii) Delay
3 Disadvantages
TSPCR are,
The disadvantages of
increase.
Number of required transistors will
(i)
by isolating dynamic nodes
occurs. This can be avoided
(ii) Charge sharing
with static inverters.
circuit.
(iii) Complex

APPROACH TO OPTIMIZE SEQUENTIAL

AN
7.4 PIPELINING:
CIRCUITS

7.4.1 Introduction continue sending water

the ideaof a water pipe:
Pipelining comes basically from
to be out.
without waiting water in the pipe
often used to accelerate the operation of
a popular design technique
* Pipelining is
datapaths in digital processors.

Water Water
Water Pipe
in out

Fig 7.23 ldea of

Pipeline

a Definition of Pipelining:
where the
A
pipeline is a set of data processing elements connected in series,
Can be
output of one element is the input of the next one. Here, a data stream resulls
continuously applied to a computational circuit in a regular way to yield

ina sequence.
Sequential Logic Circuit Design
7.21
The pipeline design technique decomposes a sequential process
into several sub
process, called stages (or) segments.
A stage performs a particular function and
produces an intermediate result.

The pipeline consists of an input latch, also

calleda register (or) buffer, followed
a
by processing circuit, which can be a combinational (or) sequential
circuit and
it is connected to an input of the next stage latch.

Input Processing Output

Latch Latch Processing Processing
Circuit Latch
Circuit Circuit

Clock

Fig 7.24 Basic structure of a pipeline

o A clock signal is connected to each latch and at each clock
pulse, every stage
transfers its intermediate result to the next stage latch.

7.4.2 Pipeline Concept

Processing circuits
REG|

CLK --Out

b
CLK

CLK

(a) Reference circuit

REG
Log -Out
CLK
b
CLK CLK CLK

CLK
(b) Pipelined version

Fig 7.25 Datapath for the computation of

pipeline
 VLSI and Chip Design
7.22
compute logla + b|), where both a and
b
pipeline circuit is to
The aim of the
the computation must be performed on a
n streams
'represents numbers, that is
of
large set of input values.
Tmin which is necessary to ensurethe correct
The minimum clock period
evaluation is given as,
pd,log ic
i.(1)
+1,
register,
delay and setup time of the
where, fog and tu are the propagation
respectively.
are edge-triggered D registers and the term på.logie
Consider the registers which
worst case delay through the combinational network, which
stands for the.
as shown in
consists of the adder absolute value, and logarithm functions

Fig 7.25(a).

Pipelining is a technique which is mainly used

to improve the resource
we introduce
utilization and increase the functional through-put. Assume that,
registers between the logic blocks, as shown in Fig 7.25(b).

- adder
Absolute
value
Logrithm

log
(a + b) I(a + b)| log l(a + b)l
|(a + b)|

Fig 7.26 Example of

pipelining process
Assume that each logic module has an equal propagation delay. Then each log
module is active for only 1/3 of the-clock period and if any delay of the registe
which can be found is ignored.
The computation for one set of input data to spread over a
number of clock-

periods, as shown in Table7.1.

cclock
The result for the data set (a1,b) only appears at
the output after three
periods. At that time, the circuit has already performed parts of computations
the
for the next data sets (a2,b2) and (a3, b;).
Seuemial Logic Circuit Design

7.23|
Clock Period Adder Absolute
1 Value Logarithm
a+b
2 +b
3
+b
la,t b log la,+b;)
4 +ba
la,+ b log (a, + b,)
5
+bs la, + bal log (a, + bD
Table 7.I Example of
pipelinedcomputations

(a + b) HI(a + b)l| log Iog |(a + b)|

b
|a + b)|

Clock

Fig 7.27 Datapath forthe computation of log (la + b|)

Ihe combinational circuit block is partitioned
into three sections, each has a
Ohaler propagation delay than the original function. This effectively
reduces the
value of
the minimum allowable clock period and it is expressed as,

Tmin, pipe =o-p maxlr,

4 The
t ..2)
inoreased
performance of pipelining comes atthe relatively small cost of two
additional
registers and an increased latency.
14,3Latch-Versus
Register Based Pipelines
ipelined circuits
can be constructed by using level-sensitive latches instead of
edge-triggered more flexibility and
registers. Latches -based pipeline system has
offer
high performance.
7.24 VLSI and Chip Design

CLK sloent)
CLK

In G
F
C3

CLK

CLK

Compute F Compute G

Operation of tw0-phase pipelined circuit using dynamic registers

Fig 7.28 pass-transistor
7.28 shows the pipeline system which is implemented using
Fig
edge-triggered registers.
based positive and negative latches instead of
master and slave latches of a master
Here, the logic is introduced between the
signals
slave system and it is a two-phase clock system using CLK & CLK

without loss of generality.

When the CLK and CLK clocks

are nonoverlapping, then the correct pipelne

operation is obtained.

C at the negative edge of CLK and t

The input data is sampled on
computation of logic blockF starts and the result of
F
block is stored on C2 0

o
the falling edge of CLK and the computation of logic block G starts. The
overlapping of the clocks ensures correct operation.
being
When overlap exists between CLK and CLK, the next input is already
That is,
applied to F, and its effect might propagate to Cz
before CLK goes low.
the
a race develops between the previous input and the current one. Based on
logic and a function of the applied inputs, one input will be processed.
Seguential Logic Crcuit Design
7.25
7.4.4 NORA-CMOS Latches
The latch-based pipeline circuit is implemented by using
C²MOS latches is called
as NORA-CMOS latches which is shown in Fig 7.29.
C'MOS-based pipelined circuit is race free as long as all the logic
A

functions
between the latches are noninverting.
VoD VpD V

CLK

In Out
G

CLK

Fig 7.29 Pipelined datapath using C'MOS latches

During a (0 – 0) overlap between CLK and CLK, all C²MOS 1atches
forms the
*
can race
simple pull-up networks. When logic function F is inverting, the signal
7.30.
from one stage to an other which is shown in Fig

A single state CMOS inverter is placed between the

C2MOS latches and the
*
– combines
similar considerations are valid for the (1-1) overlap. NORA CMOS
function blocks.
C'MOS pipeline registers and NORA dynamic logic
can be a mixture of
Each module consists of a block of combinational logic that
a logic.
static and dynamic logic, followed by C'MOS

Logic and latches are clocked in such

a way that both are simultaneously in either

evaluation (or) hold (precharge) mode.s teiitat) sióst

 VLSI and Chip Design
7.26
VpD
VDD
VpD

enCLKJ

CLK

CLK|

CMOS inverter

race condition during (0-0)overlap

Fig 7.30 Potential
CMOS based design.
in
CLK=1 is called a CLK module, while the
during
A block that is in evaluation

inverse is called a CLK module.

a chain of alternating CLK and CLK modules.

NORA data path consists of
the
one module pre-charge with its output latch in hold mode, preserving
When
is in the evaluating mode. Data
is
previous output value and the other module
one module to the other module.
passed in a pipelined fashion from

CLK block CLK block

Logic Latch Logic Latch

CLK= 0 Precharge Hold Evaluate Evaluate

CLK =1 Evaluate Evaluate Precharge Hold

Table 7.2 Operation nodes for NORA logic modules.

Segiemtial. Logic Circuit. Design
7.27|

Advantages

The advantages of pipeline process are as follows:

G).Reduction in the critical path.
(ii) Higher throughput (number of computed results in a given time)
(iii) Increases the clock speed (or sampling speed)

(iv) Reduced the power consumption.

7.5 NONBISTABLE SEQUENTIAL CIRCUITSi

7.5.1 Schmitt Trigger

a Definition
use of positive feedback
Schmitt trigger is comparator circuit that makes
a
A
in the input lead to large changes in the output in the same
(small changes
phase) to implement hysteresis and is used
to remove noise from an analog
one.
signal while converting it to a digital
displays hysteresis in their dc characteristic and fast transitions in their
It suppress noise.
transient response. They are mainly used to

A Properties of Schmitt Trigger

properties:
A Schmitttrigger isa device with two important
(1) It responds to a slowly changing input waveform with a fast transition
timeat the
output. he0
the device displays different
(i) The yoltage-transfer characteristics of
signals.
switching thresholds for positive- and negative going input
:
(1) Voltage-Transfer (V-T) Characteristics
Schmitt trigger is shown in
A typical voltage transfer characteristics of the
Fig 7.31.The switching thresholds for the
low-to-high and high-to-lovw

transitions are called V+ and V- respectively.

 VLSI and Chip Design
7.28
Vout VoH

in out

VoL

VM- VM+ Vin

characteristic (b) Scheatic symbol

(a) Voltage-transfer
noin-invertingSchmitt trigger
Fig 7.31 V-T characteristics of
as the difference between the two.
The hysteresis voltage is defined

(2)) Noise Suppression

is to turn noisy or slowly
varying
The main advantage of the Schmitt trigger
a clean digital output signal, which is illustrated in Fig 7.32.
input signal into

Vout
Vint

VM+

VM

to +tp t
t

Fig 7.32 Noise suppression using a Schmitt trigger

steep
will get
Schmitt trigger uses positive feedback, soin the output we
direct-path
signals which reducing power consumption by suppressing
currents.

(3) CMOS Implementation

shown in
One of the possible CMOSimplementation of the Schmitt trigger is
a
determined by
Fig 7.33. Here, the switching threshold of CMOS inverter is
the (k/k, )ratio between the pMOS and nMOS transistors.
Seguential. Logic Circuit Design
|7.29
Increasing the ratio raises
O the threshold, but it is decreasing
VoD
by lowers VM.

M2 M4

Vin
Vout

M4

Fig 7.33 CMOS Schmitttrigger

If V, is initially equal to 0 and V, =0.
Out
The feedback loop biases the pMOS
transistor M4 and operates in the conductive mode, while M; is OFF.
The input signal effectively connects to an inverter consisting
of two pMOS
transistors in parallel (M2 and M4) as a pull-up network and a single nMOS
transistor (Mi) in the pul-downchain.
This modifies the effective transistor ratio of the inverter to kn/ku +kya)
which moves the switching threshold upwards.
Once the inverter switches, the feedback loop turns off M4, and the nMOS
device is activated. This extra pull-down device speeds up the transition
M

and produces a clean output signal with steep slopes.

In the high-to-low transition, the pull-down network originally consists of M,
and Ma in parallel, while the pull-up network is formed by M. This reduces
the switching threshold to
V
the value of

Advantages:
The main advantages of Schmitt trigger are,
() It turn noisy or slowly varying input signal into a clean digital output
signal.
(ii) It reduces power consumption by suppressing the direct-path currents.
 VLSI and Chip Design
7.30

7.5.2 Monostable Sequential Circuits

a Definition
a that generates a pulse of a predetermined
A
monostable element is circuit or transition event
circuit is triggered by a pulse
width every time the quiescet one),
has only one stable state (the quiescent
Itis called monostable because it
or a pulse that causes the circuit to go
a signal transition
A trigger event is either eventually returns to its original
quasi-stable state. It
temporarily into another
a period determined by the circuit parameters.
state after time
useful in generating pulses of a known
This circuit is called
as one-shot which is
length.
to implementation of one-shots is using a simple
the
The most common approach 7.34.
duration of the pulse which is illustrated in Fig
delay element to control the

DELAY
Qut

one slhot
Fig 7.34 Transition- triggered
are identical and the output goes to
In the quiescent state, both inputs tothe XOR
on causes the XOR inputs to differ temporarily anu
LOW. A transition the input

After a delay
,
the output goes to HIGH.
of
the delay element, this disruption is removed
and again

output goes LOW. A pulse of length is created. or a

network
The delay circuit can be realized in many ways, such as an RC

chain of basic gates.

7.5.3 Astable Sequential Circuits

a Definition
states.
The
An astable circuit (or) multivibrator (or) oscillator has no Stable period
with a
output oscillates back and forth between two quasistable states,
 Sequential. Logic Circuit Design 7.31

determined by the circuit topology and parameters

such as delay, power supply,
etc.

Example: ring oscillator

(1) Ring Oscillator

The ring oscillator is a simple example of an astable circuit which consists of
an odd number of inverters connected in a circular
chain.
Due to the odd number of inversions, no stable operation point exists and the
circuit oscillates with a period equal to 2xt, x N
where, N–Number of inverters, and

t,- Propagation delay of each inverter.

The ring oscillator conmposed of cascaded inverters produces a waveform with

an inveter in the
a
fixed oscillating frequency determined by the delay of
CMOS process. In many applications, it is necessary to control the frequency
of the oscillator.

(2) Voltage- Controlled Oscillator (VCO)

a circuit, whose oscillation
A Voltage-Controlled Oscillator (VCO) is
oscillator can be
frequency is a function of control voltage. The standard ring
with a current-starved
modified into a VCOby replacing the standard inverter
inverter which is shown in Fig 7.35.
inverter is to limit the curent
The mechanism for conrolling the delay of each
the gate.
available to discharge and load capaciatnce of
discharge current of the inverter
In this modified inverter circuit, the maximal
an extra series device.
is limited by adding
on invetrer can also be controlled by adding a
The low-to-high transistion the
M2.
pMOS device in series with
 VLSI and Chip Design
7.32

VDD

M2

In

M4

Ventl M3

on current-starved inverters
Fig 7.35 Voltage-controlled oscillator based

5.0

4.0

(nsec)

3.0

tpHL
2.0

1.0

0.0
0.5 1.0 1.5 2.0 2.5
Vctri (V)

Fig 7.36 pL Of Current-starved inverter as a function of the control voltage

The added nMOS transistor M3
ccontrol
which is controlled by an analog
volatge Vmd reduces the discharge current
and increases t,pHL
Sequential Logic Circuit Design 7.33

The ability to alter the propagation delay per stage allows us to control the
frequency of the ring structure. The control volatge is generally set by using
feedback techniques.

Under low-operating current levels, the current-starved inverter suffers from

slow fall times at its output and results in significant short-circuit current.

This solve this problem by feeding its output into a CMOS inverter or a
Schmitt trigger. The later is the better one. Anextra inverter is needed at the
end to ensure that the struture oscillates.
(3) Differential Delay Element

Vo
Vo

in +
- in

Vctrl

Fig 7.37 Dijferential delay elenent

Another approach to implement the delay cell is to use a differential element
which is shown in Fig 7.37. The delay cell provides both inverting and
noninverting outputs and an oscillator with an even number of stages can be
implemented.
Fig 7.38 shows a two-stage differential VCO, where the feedback loop
provides 180º phase shift through two gate delays, one noninverting and the
other inverting and thus forming an oscillation.
The simulated waveforms of this two-stage VCO are shown in Fig 7.39. The
in-phase and quadrature phase outputs are available simultaneously.
 VLSI and Chip Design
7.34

V3
V1 i+ 0+ 0+
T
V2

Fig 7.38 Two-stage differential VCO

3.0

2.5

2.0

Volts
1.5

1.0

0.5

0.0

-0.5
0.5 1.5 2.5 3.5
Time (ns)

Fig 7.39 Simulated waveforms of two-stage VCO

MAdvantage
The differential-type VCOhas better immunity to common
mode noise compared
with the common ring oscillator.
Disadvantage
It consumes more power due to 1IS nCreased complexity and its static current.

7.6 TIMING CLASSIFICATION OF DIGITAL SYSTEMS

7.6.1 Introduction
In digital systems, the signals can be classified depending on how they are related
to a.local clock.
Sequential Logic Circuit Design |7.35|

Signals that transition only at predetermined periods in time

with respect to a
system clock an
be classified as,

) Synchronous,
(ii) Mesochronous,
(iii) Plesiochronous, and
(iv) Asynchronous

7.6.2 Synchronous Interconnect

a Definition of SynchronousSignal

A synchronous signal is one that has the exact same frequency as the local
clock and maintains a known fixed phase offset to that clock. In such a timing
framework, the signal is * synchronized" with the clcok, and the data can be
sampled directly without any uncertainty.
In digiatl logic design, synchronous systems are the most straightforward type of
interconnect. The flow of data in such a circuit proceeds in lockstep with the
sysetm clock, which is shown in Fig 7.40.

CLK

t In Combinational 37Out
R1 R2
Cin Logic Cout

a
Fig 7.40 Synchronous interconnect methodologY otin
In the Fig 7.40, the input data signal ln is sampled with register.Ry to produce
to
signal Cin that is synchronous with the system clock, and then it is passed the
combinational logic block.

After a suitable setting period, the output Cout becomes valid and its value is
sampled by which synchronizes the output with the clcok.
R
 VLSI and Chip Design
7.36
7.6.3 Mesochronous Interconnect
a Definition of Mesochronous Signal
as
mesochronous signal is a signal that not only has the same frequency
A the

local clock, but also has an unknown phase offset with respect that
to clock.

domains, then
For e mple,if data are being passed between two different clcok
signal transmitted from the first module can have
an unknown phase
the d
relationship to the clock of
the receiving module.
the
A mesochronous synchronizer can be used to synchronize the data signal with
serves to
receiving clock, which is shown in Fig 7.41. Here, the synchronizer
adjust the phase of the received signal toensure proper sampling.
Variable
Delay Line
, D3
R1
Interconnect R2 Block
Block A
Delay Dz D4

ClkA
Clkg

Control

Fig 741 Mesochronous communication approach using varaible delay line.

o. In the Fig 7.41, the signal D, is synchronous with respect to Clk,, but D and D
are mesochronous with Clk, because of the unknown phase difference between
Clk, and Clk, and the unknown interconnect delay in the path between Block A
and Block B.

The role of data

the synchronizer is to adjustthe variable delay line such that the
signal D, (a delayed version of clock of
D) is aligned properly with the System
Block B.
The variable delay element difference
is adjusted by measuring the phase
between the received signal
and the local clock.
 Sequential. Logic Circuit Design

R,
7.37
4 Register samples the incoming
data during the
signal D4 becomes synchronous certainty period, after the
with Clk,.

7.6.4 Plesiochronous Interconnect

Definition of Plesiochronous Signal
A
plesiochronous signal
is one that has a frequency
that of the local clcok, that is normally the same as
yet is slightly different.
This causes the phase
drift in time. differnce to
# This scenario can easily
arise when two. interacting
modules have independent
clcoks generated
from separte crystal oscillators.
& The transmitted signal can
arrive at the receiving module at a
the local clock and we
different rate than
need a buffering scheme to ensure
that all data are
received.

Typically, this type of interconnect occurs

only in distributed systems that
contain long-distance communications,
since chip or even board-level circuits
typically utilize a common oscillator to derive local
clocks.

Clock C1 Timing Clock C2

Recovery

Originating Receiving
Module FIFO Module

Fig 7.42 Plesiochronousconmunications by using a FIFO

In Fig 7.42 digital plesiochronous communication framework, the originating
module issues data at some unknown rate Ci, which is plesiochronous
with
respect to C2.

ne timing recovery unit is responsible for deriving clock C; from the data
Sequence and buffering the data in a FIFO.
 VLSI and Chip Design
|7.38
he
synchronous with the data at the input of the. FIFO andit will
Then C3 will be
Since the clock frequncies from the originating and
mesochronous with C. transmit
modules are mismatched, data might have to dropped if the
receiving
or can duplicated if the transmit frequency is slower
frequency is faster, data be

than the receive frequency.

enough, as well as periodically resetting the system
By making the FIFOlarge
an condition occurs, then strong communication can be
whenever overflow
achieved.

7.6.5 Asynchronous Interconnect

a Definition of Asynchronous Signal

Asynchronous signals can transition arbitrarily at

any time, and they are not
to map these
slaved to any local clock. As result, it is not straighforward
a

arbitrary transitions into synchronized data stream.

a

It is possible to synchronize asynchronous signals by detecting events and

by

introducing latencies into the data stream synchronized to a local clock.

To handle asynchronous signals, simply to eliminate the use of local clocks and
utilize a self-timed asynchironous design approach.
a
In such an approach, communication between modules is controlled through
handshaking protocol that ensures the proper ordering of operations.

Data Self-Timed Self-Timed

Reg Reg
Logic Logic

Req DV 1
DV
Interconnect Circuit Interconnect Circuit
Ack

Handshaking
signals
Fig 7.43 Asynchronous
design methodology for
sinple pipeline interconnect
 Sequential Logic Circuit Design
7.39
InFig 7.43, when a logic block completes an
operation, then it will generate
completion signalDV to a
indicate that output data are valid.
The handshaking signals
then initiate a data transfer to
the next block, which
Jatches in the new
data and begins a new computation
by asserting the
initialization signal I.
Advantages
The advanatges of asynchronous designs

() Computations are performed at the native speed of the logic.

i(i) Block computations occur whenever data become available.

(iii) No need to manage clock skew.

(iv) The design methodology leads to a very modular approach in which

interaction between blocks simply occurs through a handshaking
procedure.

E Disadvantages
Increased complexity and overhead in communication, which impacts in
performance.

7.7SYNCHRONOUS DESIGN

7.7.1 Synchronous Timing Issues (or) Timing Basics

(1) Introduction
use a periodic synchronization signal
All the systems virtually designed today
a a significant impact
(or) clock. The generation and distribution of clock has
system.
on the performance and power dissipation of the

In a positive edge-triggered system, the rising

edge of the clock denotes the
a cycle.
beginning and the completion of clock
 VLSI and Chip Design
7.40

R1 R2
Combinational
In - D Logic

CLK tcLk, |tcLK,

to-q togic
tç-q, cd togic, cd
tsu thold

Fig 743 Pipelined datapath circuit and tining parameters

an
o Fig 7.43 shows the basic structure of a synchronous pipeline datapath. In
ideal case, the clocks at registers 1 and 2 have the same period and transition

at the exact same time.

A Timing Parameters Available in Sequential Circuits:

are
Assume that the following timing parameters of the sequential circuit
available:

() The contamination (or) minimum delay ) and the maximum

propagation delay of the register(t.

(ii) The setup ) and hold times (hol) for the registers.
(ii) The contamination delay (tor e cd ) and the maximum delayelog ic of ti
combinational logic.
(iv) The positions of the rising edges of the clocks CLK,
and CLK2 cLk,
respectively), relative to a global reference.
In an ideal condition period is
that is tcLk, =lcLk, : the minimum clock
required for this sequential circuit to
determine the worst case propagatior
delays.

The time period (T) must be long for the

the data to propagate through
registers and logic and to be set up at the destination
register before the
rising edge of the clock.
 Sequential Logic Circuit Design
|7.41
This constraint is given
by the following expression as:

...(1)
At the same time, the hold time of the destination
register must be shorter
than the minimum propagation delay through
the logic network:
thold Io-q,cd tlogic,cd (2)
The clock signal is never be ideal, As a result
of process and environmental
variations,the clock signal can have both spatial and temporal variations,
that
lead to the perfornmance degradation and circuit malfunction.

(2) Clock Skew

a Definition

The spatial variation in arrival time ofa clock transition on an integrated circuit
is commonly referred as clock skew.

The clock skew between two points i andj on an IC is expressed as,

... (3)
si,j) =1,-1,
where t, and t; are the positions of the rising edge of the clock with respect to
the reference.
Consider the data transfer between registers RI and R2 in Fig 7.43. The clock
skew can be positive (or) negative depending upon the routing direction and

position of the clock source.

a S at the
Fig 7.44 shows that the rising clock edge is delayed by positive
second register.

The clock-skew is caused by static mismatches in the clock paths and

differences in the clock load.

The clock-skew has strong implications for both the performance

and the

functionality of sequential systems.

 VLSI and Chip
Desio
742

TCLK +8

TcLK
1) 3
CLK4

CLK2 4
+tn
on
Fig 7.44 Timing diagram of clock skew performance
and functionalitywhen 8 >0

Impact of Clock Skewon Performance:

In Fig 7.44, the new input In is sampled by RI at edge
through the combinational logic and be sampled by R2 on edge .
will propagate

positive(8> 0), then the time available for a signal to

Ifthe clock skew is
propagate from R1 to R2 is increased by the skew 8.
The output of the combinational logic must be valid one setup time before te
rising edge of CLK2(point ).
The constraint on the minimum clock period can then be derived as:

T+82tt'ogic +t, (or)

T (4)
The potential
above equation represents that
the clock skew actually has the
to improve the performance of period
the circuit. That is, the minimum clock,
required to operate the circuit reliably
reduces with clockskew.
increasing
Unfortunately, an increasing race
skew makes the circuit more susceptibleto
conditions, which may affect
the correct operation
of sequential syste
Sequential Logic Circuit Design
7.43|
Assume again that the input In
is sampled on the rising edge
of CLK at edge
O into R1. The new value at
the output of R1 propagates through
the
combinational logic and should
be valid before edge at CLK).
If the minimum delay of the combinational logic
R2 may change before the clock edge
To avoid races, we must ensure. that
,
block is small, the inputs to
resulting in an incorrect evaluation.

the minimum propagation delay through

the register and logic is long enough that the inputs to
R2are valid for a hold
time after edge (2). This constraint can be formally
stated as,
S+thold
< t(e-g,cd)
t'log ie,cd) (or)

< -4,. cd) + (og ic,cd)hold ...(5)

TCLK + 8

TcLK
3)
CLK4

CLK2

Fig 7.45 Timing diagram of 8 < 0

Fig 7.45 shows the timing diagram for the Here, the rising edge of
8<0.
CLK; 0ccurs before the rising edge of CLK,. On the rising edge of CLKI, a
new input is sampled by RI. The new data propagate through the

which coresponds toedge .

combinational logic, and they aresampled by R2 on the rising edge of CLK,

Figure 7.45 and equation (4) clearly represents that a negative skew impacts
the performance ofa sequential system.
7.44 VISI and Chip Desien

R1 R2 R3
a Combinational Combinational D
In D

Logic
Ho
a Logic

tcLK3
CLK tcLK1 tcLK2

delay delay
(a) Positive skew

R1 R2 R3
Combinational Combinational
In D

Logic D
Logic
LA
CLK tcLK1 tcLK2 tcLK3

delay delay
(b) Negative skew

Fig 7.46 Positive and negative clock skew

(i) Positive Skew (8>0)
This corresponds to a clock routed in the same
direction as the flow of the
data through pipeline (Fig 7.46a). The
skew satisfy the equation (5). 1lhe
circuit malfunctions are not depends on
the clock period.
Reducing the clock frequency
of an edge-triggered circuit does not help
solve skew problems. Hold
time constraints are satisfied at the design time.
The clock period can be
shortened by S
and the large value
the improvement limitations.
of this results in

(ii) Negative Skew

(S <0)
When
the clock is routed in
the opposite direction
skew is negative of the data (Fig 7.46 b), the
and provides
significant inmunity hold
time iszero (or) to races; when the
negative.
The skew reduces
the time available for clock
period has to be actual computation SO that the
increased by .
 Sequential Logic Circuit Design
|7.45

Fig 7.47 represents the positive

skew with feedback that is this logic
can have data flowing circuit
in both directions.It will get both
positive and negative
values, depending on the direction
of data transfer and requires low-skew
clock network.

Negative skew

CLK Logic Logic Out

Logic
(
In
CLK CLK

Positive skew
CLK

Clock distribution

Fig 747 Datapath structure with feedback

If data flow in one direction, route the data and clock in opposite directions.
This eliminates races at the cost of performance.

(3) Clock Jitter

Definition
Clock jitter refers to the temporal variation of the clock period at a given point
on the chip tht is the clock period can be reduced (or expand on a cycle-by
cycle basis. It is strictly a temporal uncertainty measure and it is specified at a
given point.
Jitter can be measured and characterized in a number of ways and it is
5 zero-mnean random variable.

A Definition of Absolute itter

The absolute jitter (time) refers to the worst case variation (absolute value) afa
clock edge at agiven location with respect to an ideally periodiç reference clock
edge.
 VLSI and Chip Design
7.46|

Definition of Cycle-to-cycle Jitter

typically refers to the time-varying deviations of
The cycle -to-cycle jiter (Titer)
reference clock.
asingleclock period relative to an ideal
as,
For a given spatial location ' and it is expressed
T
(n)=rkn-a-Tax ...6)
n
represents the arrival time of the
n+1n and clock
where, telk n+l and tk
TcLx is the nominal clock period.
edges at node i respectively and
magnitude of the cycle -to-cycle jitter
Under the worst case conditions, the
).
equals twice the absolute jiter (2

TcuK

CLK
4 Gitter

-Gitter
6

Combinational
In Logic

CLK tiogic
togic, cd
tç-q,lo-qcd
tsu, thold
Giter

Fig 7.48 Impact ofjitter on performance

Jitter can directly impact the performance of a sequential system. Fig 745
shows the nominal clock period as well as the variation in period.

o
Ideally, the clock period starts nominal
and ends at edge5), with a
at
edge
clock period the
of TCLK. In the worst case scenario, the leading edge of
current clock is delayed by jitter (edge
), while jitter causes the leading
edge of the next clock period to occur
early (edge 0).
As a
result, the total time available to complete reduced by
the operation is
2titor in the worst case and it is given as,
Sequential Logic Circuit Design
7.47
lcLk -2t jitter 2e-g t+ Iogie tgu (or)
Tox 2, tioge tm+2 jumer
jitter .(7)
Equation (7) represents that jitter
directly reduces the performance
of a
sequential circuit.

7.7.2Clock-Distribution Technigues
The clock skew and jitter are the major
issues in digital circuits, and can
fundamentally limit the performance. It is therefore necessary to
design a clock
network that minimizes both,

While designing the clock network, major consideration should be taken on

associated power dissipation.

* In most high-speed digital processors, a majority of the power is dissipated in the

clock network, to reduce this clock networks must support clock conditioning
that is, the ability to shut down parts of the clock network.

Unfortunately,clock gating results in additional clock uncertainty.

(1) Fabrics for Clocking

Clock networks include a network that is used to distribute a global reference
to various parts of the chip, and a final stage that is responsible for local
distribution of the clock while considering the local load variations.
a to use balanced
The one of the common approach to distributing clock is
paths (called trees), here the relative phase between two clocking points
is

important.
is H-tree network for a
The most common type of clock distribution scheme
4x4 processor array, which is shown in Fig 7.49.
on the chip. Balanced paths that
The clock is first routed to a central point
distribute the reference to
include both matched interconnect and buffers then
the various leaf nodes.
 VLSI and Chip Design
|7.48

datapath
en-bit
>n-bit datapath
datapath
on-bit
->n- bit datapath
n- bit datapath

>n- bit datapath

Clock-ooo >n-bit datapath

>n-bit datapath
Delays have to match
between stages
>n-bit datapath

n- bit datapath

>n- bit datapath

>n- bit datapath

Fig7.49A distributed -clock tree approacl

CLK

Fig 7.50 H-treeclock distribution network for 16 leaf nodes

 7.49|
Sequential Logic Circuit Design

If each path is perfectly balanced, the clock skew will be zero. The H-tree
configuration is particularly useful for regular array networks in which all the
elements are identical and the clock can be distributed as a binary tree.

An alternative clock distribution approach is the grid structure as shown in

Fig 7.51. Grids typically are used in the final stage of a clock network in order
todistribute the clock across the clocking,element loads.
Here, the delay from the final driver to each load is not matched. A main
advantage of a grid structure isthat it allows for late design changes, since the
clock is easily accessible at various points on the die.

GCLK

Driver

Driver
GCLK GCLK

Driveris
|GCLK

Fig 7.51 Grid structures clock distribution

8
SELF-TIMED CIRCUIT DESIGN
7.8.1 Self- Timed Logic - An Asynchronous Technique
In an
asynchronous design approach, eliminate all
the clocks which are used in
Synchronous approach.
ITensures a correct circuit operation
that avoids all potential race
under any operation condition conditions
and input sequence requires a
analysis of the network. careful timing
|7.50 VLSI and ChipDesign

A more reliable and robust technique in an asynchronous approach, is the self.

timed approach, which presents a local solution to the timing problem.
Req Req Req Req
Ack HS Ack HS Ack HS Ack

Start Done Start Done |Start Done

In R1 F1 R2 F2 R3 F3 Out

tpF1 tpF2 tpF3

Fig 7.52 Self-timed, pipelined datapath

Fig 7.52 shows the self-timed pipelined datapath
and assumed that each
combinational function has to be completed a
computation for a particular piece
of data.
The computation of a logic
block is initiated by asserting a Start signal. The
combinational logic block computes on
the input data, and generates a Done ilag
once the computation is finished.

In the case of the pipelined data path,

the functions are as follows:
() An input word arrives, and a Reg(uest)
to the block F1 is raised. F1 is
inactive at the time, it transfers If
the data and acknowledges
input buffer,which can go
this fact to the
ahead and fetch the next
word.
(i) F1 is enabled by raising
the Start signal. After a certain amount
which is dependent upon of tine
the data values and operating
Done signal goes
high and indicating the
conditions,
completion of the computation.
e
(i) A Req(uest) is issued
to the F2 module,
If this function
Ack(nowledge)
is raised, the output is free,
ahead with its next value is transferred and
computation. l can
The self - timed
approach effectively
functions implied separates the physical
in circuit timing. and logical ordering
Sequential Logic Circuit Design
7.51
The logical ordering
of the operations is ensured by the acknowledge-request
scheme. This isalso referred as a
hand-shaking protocol.

a Properties
When compared with the synchronous approach,
self-timed circuits have
following properties.

() Here the timing signals are generated locally, which avoids

all problems
and overheads associated with distributing high-speed clocks used in
synchronous approach.

(i) Separating the physical and logical ordering mechanisms results in a

potential increase in performance. In synchronous systems, the period of
the clock has to be stretched to accomnodate the slowest path over all
possible input sequences.
(ii) The automatic shutdown of blocks that are not in use can result in power
savings. The power consumption overhead of generating and distributing
high-speed clocks can be partially avoided.
iy) Synchronous systems are limited by their performance at the extremes of
the
operating conditions but the performance af a self-timed system is
determined by the actual operating conditions.
7.8.2 Self- Timed Signaling: Handshaking Protocol
& A self-timed approach requires a hand-shaking protocol to logically order the
races and hazards.
circuit events in order to avoid
The functionality of the two-phase signaling (or) handshaking logic is illustrated
a
in Fig 7.53. A sender module transmitting data to receiver. The sender places
the data value on the data bus
by changing the polarity of the signal .
and produces an event on the Req control signal

and
When receiving the request, the receiver accepts the data when possible
have been
produces an event on the Ack Signal to indicate that the data
accepted ).
 VLSI and Chip Design
7.52
On

the receiver is busy or its input buffer is full, no.Ack event is generated
If
event produced, the transmitter goes ahead and produces the next dns.
the Ack is
word ).
2
Req

Ack

Reg
Data. 1
Ack
SENDER RECEIVER cycle 1 cycle 2
Data

Sender's action
Receiver's action
(a) Sender-receiver configuration (6), Timing diagram
1

Fig 7.53 Tvo-phase handshaking protoco!

o
Four events willtake place in a cyclic order:
Data change,
Request,
Data acceptance, and
Acknowledge.
Successive cycles, may
take different amounts of time, depends on the time i1
takes to produce or consume the data. This is called as two
plhase protoCOI -
-
because only two phases of operation.

() Active cycleof the sender.

uug aN

(ii) Active cycle of the receiver. ti2ist s

Bothe phases are terminated by certain events.

The correct operation of

the sender - receiver system requires a strict orderine
the signaling events, as indicated by
the arrows in Fig 7.53 (b)
 Seguentiall Logic Circuit Design
7.53|
7.8.3 Muller C-Element

a Definition:
The Muller C-element is a small
binary logic circuit widely
of asynchronous used in design
circuits and systems. It outputs 0
outputs l when all inputs are
when all inputs are U, lr
1, and it retains
.
itsoutput state otherwise.
It performs an AND-operation on events,
The output of the C-element
copy is a
of its inputs when both inputs are identical. When the
inputs differ, the
output retains its previous value.

Events must occur at both inputs of a Muller C-element

change state and to create an output event.
for its output to

An essential component
of virtually any handshaking module is the Muller
C-element. Its schematic symbol and
truth table is shown in Fig7.54.

A B Fn+t

A 0

1
F Fn
0
Fn
B
1 1 1

(a) Schematic (b) Truth table

Fig 7.54 Muller C-element

*Fig 7.55 shows how to use this component to enforce the two-phase
handshaking protocol i.e., sender-receiver.

Assume that Rea. Ack and Data Ready are initially 0. When the sender wants to
transmit the next word, the Data Ready signal is set to 1,
which triggers the
C-element, because both its inputs are at 1. Req goes HIGH (Reqt).
Now the sender
is in wait mode, and control is passed to the receiver..The
C-element
is blocked, and no new data are sent to the data bus.
 VLSI and Chip Design
7.54

Once the transmitted data processes by the receiver, the Data accepted signal i
raised. An Ackt ensure this and unblocks the C-element which passes the
control back to the sender.

Data Receiver
Sender
logic logic)
Data ready Data accepted

Re

Ack

Handshake logic

Fig 7.55A Muller C-element implements a tw0-phase handshake protocol

7.9 TWO MARKS QUESTIONS AND ANSWERS

1. What is meant by sequential circuit?
The circuits in which an output depends on the current
inputs as well as previous
inputs are called sequential circuits. The output
is feedback to the input and
these circuits are also known as regenerative circuits.
Examples: Registers, Oscillators and Counters.

Inputs
Combinational Outputs
circuit

Memory
 Sequential. Logic Circuit LDesign

2 Give the comparisons between |7.55

combinational
and sequential
S.No Combinational Circuits circuits.
SequentialCircuits
1
The output depends
on the The output
current input values, depends on the current
input and previous input
2. Non-Regenerative circuits. values.
Regenerative circuits.
3. No memory unit is required.
Has memory
unit.
4. For designing logic,
basic gates Used to construct
(AND, OR, NOT) or a Finite State
universal| Machine (FSM) that
gates (NAND, NOR) are consists of
used. both combinational logic
and
registers, which stores
the system
state information.
5. Examples: Half adder, Full .
Examples: Registers, Oscillators,
adder, Encoder,Decoder.
Counters.
3. What is latch?
A latch is an essential component
in the construction of an edge-triggered
register. Latches is a level sensitive circuit
which passes the D input to the Q
output when the clock (CLK)) signal is HIGH.
This latch is said to be in
transparent mode.
4. Define register.

The word register" often means memory elements in digital systems.

An edge
triggered storage element is called register. i.e., the input is transferredto an
a
output at the edge of clock signal.
Positive edge triggered register: 0 1 transition
Negative edge triggered register: 1
0,transition
S.
Compare registers and latches. NOV/DEC-2018]
S.No Registers
Latches
1,
Latches are level sensitive i.e., Registers are edge-triggered
they are transparent for certain storage element. They transfer
level. input to the output at clock's
edges.
 VLSIand Chip Design

7.56
Registers
S.No Latches
clock rises.
It stores data when
2. It stores data when clock is low.
information
register retains the
A latch losses
the information A
3
on to the next until cleared.
data) when passed
device.

6. State the types of registers. - the input data is copied on the

Registers can be positive edge triggered registers

- the input data is
triggered registers
(or) negative edge
rising edge of the clock by a small circle at the
which is indicated
the clock
copied on the falling edge of
clock input.

7. What flip-flop?
is
a single bit information. A
that is capable of storing
a
A flip-flop is device
a number of flip-flops. To be more
specific
register is a device that consists of
n flip-flops. Hence, a flip-flop is a single bit
specific, an n -bit register contains
register.

8. Define static latches.

as the supply voltage is applied to the
circuit
The stored value remains valid
can be formed.
latches. It uses positive feedback so that bistable circuit
static
has two stable states that represent 0° and 1'.

List the drawbacks ofstatic latches.

.
9.
are:
The main drawbacks of static latches

() Its complexity. constantly

are
(ii) When registers are used in computational structures that
clocked. then
time,
(iii) If the memory requires holding state for extended period of
the static latches cannot be used.
Sequential Logic Circuit Design
7.57|

10. flip-flop.
Compare latch and
[APRMAY-2019, NOVDEC-2020& APR/MAY-2021/

Sr. No Latches Flip-flops

1.
It is level triggered that is, outputs It is edge triggered that is, only
can change as soon as the inputs changes state when a. control signal
changes. goes from high to low or low to
high.
2.
It does not required clock signal. It requires clock signal.

3. Asynchronous device. Synchronous device.

4. It works based on the enable It works based on the clock
signal. signal.
5. The power requirement of a latch is The power requirement of a flip
less. flop is more.
I1. What do you mean by dynamic registers?
Due to charge leakage in capacitor, the charge is stored for a limited amount of
time (order of ms). The capacitor should be periodically refreshed to obtain
signal integrity. So, the register iscalled as dynamic storage.
12. Write the types of dynamic registers.
o
There are three types of dynamic registers,
() Dynamic Transmission-Gate Edge- Triggered Register.
(ii) Clocked CMOS (C2MOS) Register.
(Gi) True Single- Phase Clocked Register (TSPCR).
13, Draw the schematic of dynamic edge-triggered register. JNOVDEC- 2016]

CLK CLK

B
D

CLK CLK

Master Slave
 VLSI and Chtp Deson

7.58| [MAYJUNE -2016]

CMOS register?
14. What is clocked master-slave concept which is
on the
positive edge-triggered register based CMOS (C'MOS)
A called as Clocked
This circuit is
insensitive to clock overlap. to increase the speed.
power dissipation and layout size and
and it used to reduce
C'MOS logic based register over pass-transistor
15. List out the
advantages of
[NOVDEC -2018)
logic based master-slave register. layout size and
to reduce power dissipation and
used
Clocked CMOS (CMOS)is
to increase the speed.

16. Write the advantages of TSPCR.

The advantages of TSPCR
are,

) Using single clock phase to avoid overlap.

(i) Possibility of embedding logic functions into the latches.

(ii) Delay overhead associated with the latches is reduced.

17. List the disadvantages of TSPCR.
The disadvantages of TSPCR are,
(i) Number of required transistors will increase.
(ii). Charge sharing occurs. This can be avoided by isolating dynamie
nodes with static inverters.

(ii) Complex circuit.

20. What is meant by pipelining?
[NOV/DEC- 2016, APRMAL-2017/
A
pipeline is a set of data processing
elements connected in series, Wnele
output of one element is
the input of the next one, Here, a data stream ca
continuously applied to a
computational circuit a results
in a sequence. in regular way to yield

21. What is NORA CMOS?

The latch-based [NOVDEC- 2017
pipeline circuit isimplemented
as NORA-CMOS latches. by using C'MOS latches is called
Seauential Logic Circuit Desigm
|7.59
NORA -
CMOS combines C'MOS pipeline registers
and NORA dynamic logic
function blocks.
9 Write the advantages ofpipeline process.l h0fiuo ss ottt Y

The advantages of pipeline process are as followg: 6i 3lonom boflae

i) Reduction in the critical path. hes d as th444 8S

(ii) Higher throughput (number of computed results in a given time)
e
(iii) Increases the clock speed (or sampling
speed)
or3
(iv) Reduced power consumption.

23. What is Schmitt trigger?

A Schmitt trigger is a comparator circuit
that makes use of positive feedback
(small changes in the input lead to large changes in the output in the same phase)
to implement hysteresis and is used toremove noise from an analog signal while

converting it to a digital one.

It displays hysteresis in their dc characteristic and fast transitions in their
suppress noise.
transient response. They are mainly used to
24. List the properties of Schmitt trigge.

A Schmitt trigger is a device with two important properties:

It responds to a slowly changing input waveform

with a fast transition
(i)
iii time at the output.
device displays different
(ii) The voltage-transfer characteristics of the
signals.
switching thresholds for positive- and negative going input

23. Mention the main adyantages of Schmitt trigger.

The main advantages of Schmitt trigger are,

signal into a clean digital output
) It turn noisy or slowly varying input

ta eniesignal.
the direct-path currents.
g
(ii) It reduces power consumption by suppressing
 VLSI and Chip Design
|7.60

26. Define monostable circuit.

a a predetermined width
A monostable element is a circuit that generates pulse of
every time the quiescent circuit is triggered by a pulse or transition event. It
je

one stable state (the quiescent one).

called monostable because it has only

27. What do you nmean by astable circuit?

no stable states. The
An astable circuit (or) multivibrator (or) oscillator has
a
output oscillates back and forth between two quasistable states, with period
determined by the circuit topology and parameters such as delay,
power supply,

etc.
Example: ring oscillator
28. List the timing classification of digital systems.
[NOVDEC-2020 & APRMAY-2021]
Signals that transition only at predetermined periods in time with respect to a

system clock can be classified as follows,

i) Synchronous,

(ii) Mesochronous,

(iii) Plesiochronous, and

(iv) Asynchronous.

29. Define synchronous signal.

A
synchronous signal is one that has the exact same frequency as the local clock
and maintains a known fixed phase offset to that clock. In such a timiny
framework, the signal is "synchronized" with the clock, and the data can
sampled directly without any uncertainty.

30. What do you mean by mesochronous signal?

A mesochronous signal is a signal that not only has the same frequency 2s
local clock, but also has an unknown phase offset with respect to that clock.
then
Forexample, if data are being passed between two different clock domains,
phase
the data signal transnmitted from the first module can have an unknown
relationship to the clock of the receiving module.
 Sequential Logic Circuit Design 7.61|

31. Define plesiochronous signal.

A
plesiochronous signal is one that has a frequency that is normally the samne as
that of the local clock, yet is slightly different. This causes the phase difference to
drift in time.

32. What is meant by asynchronous signal?

Asynchronous signals can transition arbitrarily at any time, and they are not
slaved to any local clock. As a result, it is not straightforward to map these
arbitrary transitions into a synchronized data stream.

33. List the advantages of asynchronous design.

The advantages of asynchronous designs are,
(i) Computations are performedat the native speed of the logic.
(i1) Block computations Occur whenever data becomes available.
(iii) No need to manage clock skew.
an
(iv) The design methodology leads to a very modular approach in which
interaction between blocks simply occurs through a handshaking,
procedure.

34. Defe synchronous sequential circuit.

In synchronous sequential circuit, the output depends on present and previous

of the inputs at the clocked instances.

states

35. What is an asynchronous sequential circuit?

A sequential circuit for which its output depends on the
sequence in which the

input signals change is referred to as asynchronous sequential circuit.

36. Compare and contrast synchronous design and asynchronous design.

[APR/MAY 20177
(or)
Mention the comparison between asynchronous and synchronous sequential
circuits.
 VLSI and Chip
7.62| Design

Sr.No Asynchronous Design Synchronous Design

1. The state of circuit can change A change of state occurs only in
immediately when an input response to a synchronizing
change occurs. clock pulse.

2. It does not require clock pulse. It requires clock pulses and

circuit speed of operation
depends On the maximum
allowed clock frequency.

37. Define clock skew.

[NOVDEC -2018, APRMAY-2019]
The spatial variation in arrival time of a clock
transition on an integrated circuit
is commonly referred as clock skew.

38. Define clock jitter.

Clock jitter refers to the temporal

variation of the clock period at a
given point on
the chip that is the clock period can
be reduced (or) expand on a
cycle-by-cycle
basis. It is strictly a temporal
uncertainty measure and it is
specified at a given
point.

39. Differentiate absolute

and cycle-to-cycle jitter.
The absolute jitter (titer) refersto the worst case
variation (absolute value) of a
clock edge at a given location
with respect to an ideally periodic
edge. reference clock

The cycle-to-cycle jitter (Tjiter)

typically refers to the time-varying
single clock period deviations of a
relative to an ideal reference
clock.
40. List out the properties
of
ihio iiAtSape
self-timedcircuits.
When compared with
the synchronous approach.
following properties. self-timed circuits hay
() Here the timing
signals are generated
and overheads locally, which avoids problems
associated with all
synchronous distributing high-speed
approàch. clocks used in
Sequential Logic Circuit Design
|7.63
Gi) Separating the physical and logical
ordering mechanisms results in a
potential increase in performance.
In synchronous systems, the period
of
the clock has to be stretched to
accommodate the slowest path Over
all
possible input sequences.
é
41. Write the functionof Muller C-element.
The Muller C-element is a small
binary logic. circuit widely used
in design
of asynchronous circuits and systems. It outputs 0
when all inputs are 0, it
outputs l when all inputs are 1,
and it retains its output state otherwise.
It performs an AND-operation on events. The output
of the C-element is a copy
of its inputs when both inputs are identical. When
the inputs differ, the output
retains its previous value. Events must occur at both
inputs of a Muller C-element
for its output to change state and to create an output event.

42. Draw the schematic diagram of Muller C-element.

A Fn+1

1
-
Fn

0
En
B
1 1

(a)Schematic (b) Truth table

7.10 REVIEW OUESTIONS

I. Discuss in detailabout various static latches and registers with neat sketches.
[NOVW DEC-2016]
a Explain about multiplexer based latches with neat sketches.
3, Explain the operation of
Master-Slavebased edge triggered register.
IMAYIJUNE- 2016,APRMAY- 2018, NOV/DEC -2018/
 VLSI and Chip Design
7.64
an edge triggered
4. Realize a negative level sensitive latch using which realize
NOV/ DEC-2019)
master slave D-flip-flop. Explain its working.

5. Write note on static SkR flip-flops.

with neat
6. Discuss in detail about various dynamic latches and registers
sketches.
7. With neat sketch, discuss about Dynamic TransmissionGate Edge Triggered
Registers.
Explain the operation of
Clocked CMOS register.

9. Explain the operation of True Single Phase Clocked Register (TSPCR)

[APR/MAY-2017|
10. Discuss in detail various pipelining approaches to optimize sequential circuits.

[APR/ MAY-2016, NOVDEC -2017|

II. Describe the concept of pipelining in sequential circuits with a suitable
example. NOVDEC-2020 & APRMAY-2021]
12. Write note on NORA-CMOS latches.
[NOVIDEC-2016]
13. Explain about Schmitt Trigger and its voltage-transfer
characteristicwith neat
sketches.
14.Sketch
and explain the Monostable sequential
circuits based on CMOS logic.
NOV/DEC-2020& APRIMAY-2021|
15. Explain the
operations of Astable sequential
circuit with neat sketches.
16. Write note on

() Ring oscillator,
(ii) Voltage controlled
Oscillator, and
(ii) Differential delay
element.
17. Explain the timing
basics and clock
design in detail. distribution techniques
in Synchronous
NOVDEC-2017|
Sequential Logic CircuitDesign 7.65
18. Explain the concept of timing issues and pipelining. [APRMAY-2017]
10. Design a
clock distribution network based on H-tree model for 16 nodes.
NOVDEC -2018]
20. Discuss in detail about self-timed logicwith neat diagrans.
21. List out the properties of
selftimedcircuits.
22. Write noteon Muller CCelement.
 UNIT INTERCONNECT, MEMORY
ARCHITECTURE AND
IV ARITHMETIC CIRCUITS

Chapter 8
INTERCONNECT

8.1 INTERCONNECT PARAMETERS

8.1.1 Capacitance
An accurate modeling of the wire capacitance(s) in a integrated circuit is a big
task. This task is further complicated by the interconnect structure of the
contemporary integrated circuits which is three-dimensional.
The capacitance of an interconnect wire is a function of following:

Shape,
Environment,

Distance to the substrate, and

Distance to surrounding wires.
A designer use an advanced extraction tool to get precise values of the
interconnect capacitances of a completed layout.
Most of the semiconductor manufacturers also provide empirical data for the
test dies.
various capacitances contributions, as measured from anumber of
Consider a simple rectangular wire placed above the semiconductor substrate as
shown in Fig 8.1.
 VLSIand Chip Design

8.2
insulatino
substantially larger than the thickness of the
is
If the width of the wire electrical field lines are orthogonal +.
assumed that the
material, then it may be parallel-plate
plates and its capacitance can be modeled by the
the capacitor
as area capacitance.
capacitor model which is also called

Current flow

W Electrical-field lines

tdi Dielectric

Substrate

Fig. 8.1 Parallel-plate capacitance model of interconnect wire

* The total capacitance of the wire can be approximated as,

Cint ..
(1)

where W and L are the width and length

of the wire.
li and i represent the thickness of the dielectric
layer and its
permittivity.

Equation (1) represents that the capacitance

is proportional to the overlap
between the conductors and inversely
proportional to their separation.
The capacitance between the side
wallsof the wires and the substrate is calld a
fringing capacitance which is contributes
overall capacitance. We can use
simplified model that approximates
the capacitance as the sum
components which is shown in Fig 8.2 (b).
of two

() Parallel plate capacitance which is

determined by the orthogonal Seld
between a wire of
width w'and the ground plane.
(i1) Fringng capacitance which is modeled by a cylindrical
wire with
dimension equal to the interconnect thickness
H.
nterconnect
8.3

Ctinge

Cpp

(a) Fringing fields

(b) Model of fringing-field capacitance

Fig. 8.2
Then, the approximation of wire capacitance is given as,

Cwire + Cfringe

w Edi 2 Edi
... (2)
tai log (a/H)

where w = W- H2 is a good approximation for the width of the parallel plate

capacitor.
* Figure 8.3 plots the value of the wiring capacitance as a function of W/H. For
larger values of W/H, the total capacitance approaches the parallel plate mode.
For W/H values smaller than 1.5 the fringing component actually becomes the
dominant component.
The fringing capacitance can increase the overallcapacitance by a factor of more
than 10 for small line widths. Fig 8.4 shows the capacitance components of a
wire embedded in an interconnect hierarchy are identified.
 VISIand Chip Design
8.4

(pF/cm) H/tai = 1

= 0.5
Capacitance H/tj

0.4
Cp-p

0.2

0.1
.
0.1 0.2 0.4 0.6 1 4 6 10
2
WTdi

Fig. 8.3 Capacitance of interconnect wire as a function

of (Whái)

fringing
parallel

Fig 8.4 Capacitive coupling

between wires in interconnect hierarcy
Each wire
is not only coupled to the grounded to the
neighboring wires on substrate, but als0
the same layer and on adjacent change
the total capacitance layers. This does not
connected to a given
wire.
 ere not all of 1ts capacitive components 8.5
olarger number of terminate at the grounded
them connected to other substrate.
varying voltage levels. wires which have dynamically
The floating
capacitors form not only a source
negative impact on the performance of
can have a noise i.e. cross-talk, but
also
, The of the circuit.
inter-wire capacitances
become a dominant factor
structures. The in multi-layer interconnect
increasing contribution of the
inter-wire capacitance to
capacitance with decreasing the total
feature sizes is best illustrated by
Fig 8.5.
5

1 um field oxide
1 um metal
1 um sin cap layer

(pF/cm)

Ctotal

Capacitance

Cinterwire
Cground

Cparallel - plate

1 2 3 4 5
Design rule (um)

Fig. 8.5 Interconnect capacitance as a

functionof design rules .

8.1.2
Resistance
The
resistance of a
proportional to its length
wire is
, L and inversely
proportional as,
to its cross-section A. It is expressed
= pL pL
R (3)
A HW
where,
the constant p
is the resistivity of the naterial (in 2-m).
 VLSI and Chip Design

integrated
8.6| most often used in
which is
interconnect material the standard integrated.
Aluminum is the compatibility with
lowcost and its compared to materials
its
circuits because of has a large resistivity
process. But it
circuit fabrication
such as copper.
can alsoexpressed as,
Equation (3) be ... (4a)
L
R = Rp W

where ...
(4b)
P
Ra H
S2/O.ie. olhm
resistance of thematerial with the units of
where Ra is the sheet

per square.
square
equations (4a & 4b) reprsents that the resistance of a
The above
conductor is independent of its absolute size. To obtain
the resistance of a wire,
simply multiply the sheet resistance by its ratio (L/W).

(1) Polycide

A
compound, materialformed using silicon and a refractory
silicide is a

metal. This creates a highly conductive material that can withstand high
temperature process steps without melting.
The silicides are most often used in a configuration
called a polycide, whic
is asimple layered combination of
polysiliconand a silicide.
A typical polycide consists
of a lower level of polysilicon with an uppe
coating of silicide which combines
the best properties of both materials. Tno
good adherence and coverage
from the poly and high
silicide.
conductance from ti
A
MOSFET fabricated
with a polycide gate
advantage of the silicided
is shown in Fig 8.6.
gate is a reduced gate
silicided source and drain resistance. Simila
regions reduce the source
the device. and drain resistance
Interconnect

8.7|
Silicide

Polysilicon
SiO2

n+
p. n+

He
N
312ig
Fig 8.6 A Polycide-Gate
MOSFET
Transistors between
routing layers add extra
called the contact resistance. resistance to a wire which
It is possible to reduce the contact is
making the contact resistance by
holes larger.
The current tends to concentrate
around the perimeter in a larger
hole. This effect is called as current contact
crowding, which makes a
limit on the size of practical upper
the contact.
(2) Skin Effect
In most of semiconductor circuits, the
resistance of a semiconductor wire to be
linear and constant. But because
of skin effect, at very high frequency, the
resistance becomes frequency dependent.

High frequency currents tend to flow primarily on the surface

of a
conductor, with the current density falling off exponentially
with depth into
the conductor.

The skin depth 8' is defined as, the depth at which the current falls off toa
value of e ofits nominal value" and it is expressed as,
... (5)

where

j- Frequency of the signal, and

- Permeability of the surrounding dielectric.
The effect can be approximated by assuming that the current flows uniformly
In an outer shell of the conductor with thickness 8, as illustrates in Fig 8,7 for
a rectangular wire.
 VLSI and Chip Design
|8.8|

Fig 8.7 The skin-effect reduces the flow of the current to the surface
of the wire
Assume that the overall cross section of the wire is now limited to
approximately 2(W+H)8. Then, the expression for the resistance per unit
length at high frequencies (f > f) is,

r) ... (6)
2(H+W)
The increased resistance at higher frequencies may cause an extra attenuation
that is distortion of the signal being transmitted over
the wire. The frequenc)
of
theskin effect is expressed as,

4p ... (7)
T (max (W, H))2
E W=1 um

W= 10um
W=20 um

Resistance
100

in
increase

0,1

18 1E9
Frequency (Hz) 1E10
Fig 8.8 Skin-effect
for different width
conductor
Interconnect
8.9|
Erom Fig 8.8, we can observe that the
skin-effect induced increase in resistance
as a function of frequency and
wire width.

8.1.3 Inductance
The inductance of a circuit can be evaluated by a
changing of current when
passing through an inductor and generates a voltage drop
as,osrekeS5
AV = L di ... (8)
dt
to compute the inductance a wire directly from its geometry and its
It is possible
environment. The capacitance 'c' and the inductance ' (per unit length) of a
wire are related by the following expression:.

cl = E
(9)
where 'e' and ' are the permittivity and permeability of the surrounding
dielectric, respectively.
The constant product of permeability and permittivity also defines the speed v
at which an electromagnetic wave can propagate through the medium and it is
given by,
1 1
Co .. (10)
where
a vacuum, and
Co is the speed of light (30 cm/ns) in
H, isthe elative permeability.
Š.2 EECTRICAL WIRE MODELS
The electrical models that estimate and approximate the real behavior of the wire
as a function of its parameters.

8.2.1 The Ideal Wire

no attached parameters or
In schematics. wires occur as simple lines with
circuit.
Parasitics. These wires have no impact the electrical behavior of the
on
 VLSI and Chip Design
8.10
to its other
change at one end of the wire will propagate immediately
A voltage
away.
ends, even if they are some distance
every segment of the wire
Whenwe assumed that the same voltage is present at
to an equipotential region.
at every point in time. Thena whole wire is said be

8.2.2 Lumped Model

As long as the resistive component of the wire is small and the switching
frequencies are in the low to medium range. Then we have to consider only the
capacitive component of the wire.
Lump the distributed capacitance into a single capacitor, as shown in Fig 8.9.

Rdriver
Vout Vout
HHH
HH Vin
Driver HH HH HH HH Cwire
Clumped
Fig 8.9 Distributed versus
lunped capacitance
o In this model, model of wire
the wire still represents an
itself does not equipotential region
introduce any and that the wire
introduced delay. The only
by the loading
effect impact on performance 1s
of the capacitor on
This capacitive
lumped model
the driving gate.
for the analysis is simple and
of most interconnect effective.
lumped capacitance It is the model
wires in digital of choice
ofthis model integrated
is expressed as, circuits.Then,the
lumped
where LX Cwire
L - Length ofthe wire,
Cyire
Capacitance
per unit
The driver length
is modeled as
advantage
of
a voltage source
an this approach
ordinary
differential is that the effectsand the source
respect equation. resistance
ofthe parasitics
to either These lumped
Rdriver
resistance can
or inductance. models are be described
useful for b)
wirsN
 3The Lumped RC Modeltsis
model that lumps the
total wire resistance of each wire segment
R and similarly combines the into onesingle
global capacitance into a single
simple model is called capacitor C. This
the lumped RC model and
it is inaccurate for long
interconnect wires, which are
more.adequately represented by a
rc-model. distributed

Consider the resistor-capacitor

network of Fig 8.10, which is called as
RCtree
and has the following properties:

Network has a single input node (called s

in Figure 8.10).
- Allthe capacitors are between anode and the ground.
Network does not contain any resistive loops (which
makes it a tree).
2
R2
R1
1 1
4

I R3
G4

Fig 8.10 Tree-structured RC network

In this particular circuit topology, there exists a uniqueresistive path between the
source node s' and any node i' of the network. The total resistance along this
path is called the path resistance Ri.

For example. the path resistancebetween the source node s and node 4 is
expressed as,
= Ry
R4 R+R,+
 VZSI and Chip Design
8.12
extended to address the shared path

the path resistance can be paths from the

The definition of
resistance shared among the
Which represents the
resistarnce Riks

root node s to nodes k and

i. npaths (s*)).. )
= ER, (R, [paths (s i)
R R,2 =R.
For the circuit
of Fig 8.10, R, -R,+ R, while to
network is initially discharged
the N nodes of the
Assume now that each of s at time t =0. The Elmore delay at
a sep input is applied at node
GND, and that
the following expression,
node i is then given by
N ... (2)

k=1
order time constant of the network
-
equivalent to the first
The Elmore delay is designer should be aware that
the impulse response).
The
(or the first moment of approximation of the actual delay
constant represents a simple
this time
between source node and node i.
(1) RC Chain (or) Ladder:
RC chain (or ladder) shown in Fig 8.11 which
Considerasimple, non-branched
case RC tree network. This network is worth analyzng
is a special of the represents 2
structure is used in digital circuits and also
because this
wire.
approximative model of a resistive-capacitive
i-1 R; RN N
R1 1 R2 2 R1 VN

I I
Fig 8.11 RC chain network
The Elmore delay of this chain network can be expressed as,
N N ..(3)
i=1 j =1 i=1 As
an
resistance.
The shared - path resistance is replaced by simply the path oftwo
- Consists
example, consider node 2 in the RC chain of Fig 8.11. Its time
components contributed by nodes 1
and 2.
Tnterconnect 8.13
The component of node 1 consists of CR,with R, the total resistance between
the node and the source, while the contribution of node 2 equals C, (R, + R,).
The equivalent time constant at node 2 equals C,R,
+C, (R +R,).
Trof node i can be derived in a similar way as,

tpi CjR
+C, (R + Ry) +... +C; (R+ R,
t... +R) ....4)

8.2.4 The Distributed rc Line

rAL rAL rAL V rAL
Vin Vi1 rAL
WW Vout

CAL: CAL caLt cALt CALT

(a) Distritbuted model

(, c, L)
Vin W
Vout

(b)Schematic Symbol for distributed RC line

Fig 8.12
distributed rc model is shown in Fig 8.12 (a), here L represents the total length
A

of the wire, while r and c stand for the resistance and capacitance per unt
length. A schematic representation of the distributed re line is given in
Fig 8.12(b).
The voltage at node i of this network can be determined by solving the following
set of partial differential equations:et
(V+1-V) + (V,-j- V)
cAL *. (5)
The correct behavior of the distributed re line is then obtained by reducing AL
asymptotically to 0. For AL 0, Equation (5) becomes the well known
diffusion equation:
 VLSI and Chip Design

•.. (6)
T
differoyoe do
particular point in the wire, and x is the
a
Where V' is the voltage at
source.
between this point and the signal
equation, but tha
no closed-form of solution exists for the above
There is
are given as, TE
approximated expressions
RC t>> RC ch
= 2erfe |
Vour
() 4t
-2.5359 -9.4641! 4 rc de
=1.0- 1.366 e RC
+0.366 e RC t<< RC... (7) Small

These equations are difficult to use for ordinary circuit analysis. The distributed
rc line can be approximated by a lumped RC ladder network, which can be easily
used in computer-aided analysis. with

2.5,
8.2.5 Tr-.
X=L/10
2 A Defin
X= LI4 A
(V) 1.5 dist.
voltage

X=LI2 this rl
7
accurc
X=L
0.5H
The
tr
interco
0 0.5 1.5 2 2.5 3 3.5 4 In
time (nsec) 4 the
Fig. 8.13 Simulated
step response the ele
as a function of resistive-capacitive
of time and place wire inducti
Fig 8.13 shows the response
at different of a wire to a
points step input
in the wire as a which plots
the waveforms
delay for long wires. function of
time and resulting considerable
Driving these rc
lines and minimizing
ina
hetickiestproblems
in modern digitalthe delay and signal one of
integrated degradation is
circuit design.
Interconect
8.15
a Critical Length:

L The critical length Lerit

of the interconnect wire where RC
dominant and it is expressed delays become
as,

Ipgate
... (8)
0.38rc
The actual value of Lerit depends upon the sizing of the driving gate
and the
chosen interconnect material.
rc delays should only
be considered when the rise (fall) time at the line input
is
smaller than RC, the rise (fall) time the line.
of
rise RC
*. (9)
with 'R and C
the total resistanceand capacitance of the wire.

8.2.5 Transmission Line Model

a Definition:
A distribution of resistances, capacitances and inductances over the wire. Then
this rlc model of a wire is known as the transmission line model. It is a nost
accurate approimation ofthe actual behavior.
The transmission line has the prime property that a signal propagates over the
interconnection medium as a wave.
In the wave mode, a signal propagates by alternatively transferring energy from
the electric to the magnetic fields, or equivalently from the capacitive to .the
inductive modes.

Vin out

C C
8

Fig 8.14 Lossy transmission line

at t the set
Consider the point x along the transmission line of Fig 8.14 time and
of equations:
 VLSl and Chip Design

8.16
= ai
-ri-l at
... (10)

that
conductance g = 0, and eliminating the currenti
Assuming that the leakage
the wave propagation equation as follows,
yields
= rc + lc .(11)

are resistance, capacilance, and inductance per unit length,

where r, c, and I the
respectively.

a Lossless Transmission Line:

as lossless transmission line
A
simplified capacitive/inductive model is called
that line has small resistance.
This model is applicable for wires at the Printed-Circuit Board (PCB) level.
Here, high conductivity
of
the copper interconnect material is used, due to this
the resistance ofthe transmission line can be ignored.

In the lossy transmission lien model, the resistance plays an important role n
integrated circuits.

(1)The Lossless Transmission Line

For the lossless line, Equation (11) can be simplified to the ideal
equation as,

= lc 02y
1
2y ... (12)
y2 dr2
the
A
input is applied to a lossless transmission line that propagates along
step

line with a speed v as,

Co .. (13)
wire
and
The values of both
depend on the geometric shape of the
l and c
media.
their product is a constant which is only function of the surrounding
Interconnect
8.17
The propagation delay per unitwire
length (t) ofa transmission line is the
inverse of the speed and it is expressed as,

... (14)
dx

Wire

Substrate

Direction of propagation

Fig 8.15 Propagation of voltage step along a lossless transmission line

Suppose that a voltage step V has been applied at the input and has propagated
to point x of the line as in Fig 8.15.
All currents are equal to 0 at the right side of the x, while the voltage over the
line equals V at the left side. An additional capacitance cax must be charged
for the wave to propagate over an additional distance dx. This requires the
Current to be

d dx ... (15)
i= dt
C dt V=
dx
Since the propagation speed of the signal, equals v. This means that the
signal sees the remainder of the line as a real impedance as,

Zo =
.
= (16)
C CV

This impedance is called as the characteristic impedance of the line and it is a

function of the dielectric medium, geometry of the conducting wire and
isolator which is independent of the length of the wire and the frequency.
(2) Termination

The behavior of the transmission line is strongly influenced by the termination

of the line. The termination determines how much of the wave is reflected
upon arrival at the end of the wire.
 VLSI and Chip Design
|8.18

coefficient (p) that determines the relationship

ioThe expression of reflection
waveforms
between the voltages and currents of the incident and reflected
Vreft R-Zo ... (17)
/inC R+ Zo
voltages and
where R' is the value of the termination resistance. The total
sum of incident and reflectod
currents at the termination end are the
waveforms:
.e = Vie(1 + p)
... (18)
I= I,pc (l-p)
Incident wave
wave
Zo V EReflected

Zo
W

L X
(a) Matched termination

(b)Open- circuit termination

Zo
V

(c) Shot- circuit termination

Fig 8.16 Behavior of various transmission lineterminations
equal
In case of
matched termination Fig 8.16 (a), the terminating resistance is
to the characteristic impedance of the line. The termination appears
infinite extension of the line, and no waveform is reflected (p =0).
open
an
In case of open-circuit terminatiton Fig 8.16 (b), the line termination is twice
is
circuit (R= c), andp= 1. The total voltage waveform after reflection

the incident one.

 Finally, in ase
Fig 8.16 (c)
whether B.19
and p-1. The total voltage the line termination
atthe
end ofthe wire is a short circuit,
R
after reflection R=0,
=0,
equals to zero.

Zo

H
Fig 8.17 Transmission
A line withtermninating
Only a small impedances
fraction of the incoming
signal V.in is injected into the transmission
line. The amount
injected is determined
source by the resistive divider
resistance and the characteristic formed by the
impedance Z,.

Vsource Zo
... (10)
Z+ R)
This signal reaches the end of
the line after sec, where L stands for the length
of the wire and is fully reflected, which effectively doubles
the amplitude of the
wave.

G6 TWO MARKs QUESTIONS AND ANSWERS

List out the factors that influence an interconnect wire capacitance.
The capacitance of an interconnect wire is a function of following:

Shape,
Environment,
Distance to the substrate, and
Distance to surrounding wires.
2,
wire.
Express capacitance of the
thetotal
wire can be
approximated as,
Thetotal capacitance ofthe

Cint WL
 VLSIand Chip Design
8.20
s
. L are the width and length of the
wire..3i tiks
where, W and
of the dielectric layer and its
and Edi represent the thickness
ti
permittivity
capacitance is proportional to the overlan
represents that the
The above equation proportional to their separation.
inversely
between the conductors and
3. Define fringing capacitance. substrate is called
as
wires and the
between the side walls of the
The capacitance
capacitance which is contributes overall capacitance.
fringing
interconnect wire.
4. Express resistance ofa proportional.
proportional to its length L
and inversely
a
The resistance of wire is
as,
to its cross-section A. It isexpressed
pL_pL
R= A HW

the material (in 2-m).

where, the constant p is the resistivity of

5. What do you nmean by silicide?

metal.
formed using silicon and a refractory
A silicide is a compound material
high-temperature
creates a highly conductive material that can withstand
This
process steps without melting.

6. What is polycide?
a
a configuration calleda polycide, which 1S
The silicides are most often used in
a
simple layered combination of polysilicon and silicide.
coating
with an upper
A a
typical polycide consists of lower level of polysilicon
good
materials. The
of silicide which combines the best properties of both
silicide.
adherence and coverage from the poly and high conductance from the

7. Define skin effect.

off to a
The skin depth '8' is defined ás, * the depth at which the current falls

value of e of its nominal value" and it is expressed as,

8 =
ntérconnect
8.21|
where

f- Frequency of the signal, and

u- Permeability of thesurrounding
dielectric.
e
Name the electrical wire models.
Some of are
the electrical wire models are, so s
it
(1) Ideal wire,

(i) Lumped model,

(ii) Lumped RC model,
(iv) Distributed rc imodel, and
(v) Transmission line.
9. Define lumped RC model.
A model that lumps the total wire resistance of each wire segment into one single
R and sinmilarly combines the global capacitance into a single capacitor C.
This
simple model is called the lumped RC model and it is inaccurate for long
interconnect wires, which are nmore adequately represented by a distributed rc
model.

10. Write the properties of

RCtree.
The RC tree has the following properties:
Network has a single input node 's'.
Allthe capacitors are betvween a node and the ground.

Network does not contain any resistive loops (which makes it a tree).

Define transmission line model.

A distribution of resistances, capacitances and inductances over the wire. Then
a
nis rlc model of a wire is known as the transmission line model. It is most
accurate approximation of the actual behavior.

Lne transmission line has the prime property that a signal propagates over the
interconnection medium as a wave.
 VLSI and Chp Design

8.22|

transmission line?
12. What is lossless
model is called
as lossless transmission line
simplified capacitivelinductive
A

that line has small resistance.

This modelis applicable for wires at the
Printed-Circuit Board (PCB)level. Here
high conductivity of the copper interconnect material is
used, due to this the
resistance of the transmission line can be ignored.

8.7 REVIEW.QUESTIONS
1. Discuss in detail about an interconnect capacitance
ofa wire.
2. Briefabout interconnect resistance of a wire.
3. Write note on inductance.
4. Illustrate about the lumped model
with diagrams.
5. With neat sketches, explain
in detail about the electrical
6. Discuss in detail about
wire models.
the lumped RC model.
7. Briefabout the distributed
model rc line.it
8. Explain in detail
about the transnission
line model.
 UNIT.IV
)

Chapter9
SEQUENTIAL DIGITAL
CIRCUITS
9.1 ADDERS

9.1.1 Introduction
4 Addition is one of the basic operation in data processing
used in
which is most commonly
arithmetic operation. It is used in every
stage, starting from
multiplication and also.in counting to
filtering.
Adders can be implemented in various forms which suits different
speed and density
requirements.

li2 Single - Bit Binary Adder

When two half adders are cascaded, the carryoutput of one half adder is connected
4S inputto the second half adder. This is called as full,adder.

A B

A Half Half Sum

B Adder Adder Cout
1 S
adder
Fig 9.1Block diagram offull
 VLSI and Chip Design
9.2
binary full adder is shown in table9.1. A and B are the inputs of
The truth table ofa
Cout iS the carry output. The
an adder. C is the carry input, S is the sum output and
are given in equations (1)and (2).
Boolean expressions for S and Cout
as functions of some intermediate signals
It is often useful to define S and Cout
(propagate). The truth table for full adder is
G (generate), D (delete) and P
given as:
Carry
B C: G=A.B D=A.B P=AB S Cout
A
Status
0 1
Delete
1
0 1
0 Delete
1 1 1
Propagate
0
.

0 1 1
Propagate
0 0 0 1
0 Propagate
1
0
Propagate
1
0
0 1
Generate/
Propagate

0 1 1
Generate/
Propagate
Table 9.1 Truth
table of fulladder
A Sum of Full Adder

Thelogical
expressions
for sumand carry can
be obtained by using K-map,
Sum, S =
ABC+BC+ ABC + ABC
= A
(BC+ BC)+A (BC +
BC)
Souetial Digal Circuits
9.3

= A (B C) +
A (B C)

|S=A BC ...
The Sum logical (la)
expression in terms of propagatesignal
(P) is given as,
S= (A B) C=PC .. (1b)
A Carry of Full Adder

Carry,
C= ABC+ ABC + ABC+ABC+ABC
+ABC9bb tist uff
= BC (A + A) + AC (B + +
B) AB (C + C)
= BC+ AC+ AB

= AB + BC + AC= AB+C (A+B).

Cout MAJ (A, B, C) (Majority of A, B, C) ... (2)

A
B P MAJ – Cout
C

Fig 9.2 Logical diagram of'sum and carry of fulladder

a

The carry gate is also called majority gate because itproduces a, 1 if atleast hyo of
ne three inputs are l. The logic gate implementation of sum and carry is shown in
Fig 9.3.

SUM =ABCie, l- io,

(a)
 VISI and Chip Design
9.4

CARRY AB + C (A + B)
=

(b)

Fig 9.3 Logic gate implementation of sum and carry

The full adder can be drawn using logic gates are as shown in Fig 9.4.

B Sum =A BC
C

Cout =AB+ BC +AC

Fig 9.4 Full Adder

9.1.3 CMOS Implementation

of Full Adder
An implementation
of 1-bit adder for 3-input XOR gate
Figure 9.5. using transistors is show

If the circuit uses

3-input XOR gate,
32 that is, the total.number of transistors required. are
16 transistors for sum
(3-input XOR), and
6 transistors for inverted Io transistors for carry
inputs (A, B, C).
 tal1Digital Circuits

|9.s
Vpo

VoD

B B

Cout
B
B A

B
A
B

B)CARRY
A) SUM

of full adder
Fig 9.5 CMOS Implementation
* The sum equation can further be simplified in order to reduce the number of
transistors.

S = ABC + ABC + ABC+ ABC

as,
The above expression can be factorized
+ C) +
ABC
S =(A+ B+ C) (A+B) (B + C)(

=
·
(A +B +C) (AB BC. AC)
c) +ABC

= (A + B+ C) AB + BC +
AC ) +ABC
 VLSI and Chip Design
9.6
Co t ABC
... (3)
C)
S= (A+B+
This equation (3) minimizes the number
of
transistors to be used. Also, it eliminatos
the need for inverting the inputs.

A MINORITY.

C Cout

Cout

(a) Logical implementation

MINORITY

VDD

B.

C
E
Cout

H
Gout
(b) Transistor
level CMOS
implementation
Fig 9.6
 Soquemtial LDigial Circuits

This uses only28 transistors. Thus,

9.7
more
the number of series
the layout is uniform. The addition transistors is reduced and
function is
of the function is the function
symmetric that is complement
of complemented
gate level in Fig 9.6 (a) and transistor
inputs, which is also shown at the
level in Fig 9.6 (b).
But this increases the delay
for computation of sum
than carry.
VoD
Vop

B-d|
VoD
A-4|
X

Vop
TA
-c,

Fig 9:7 Complementary Static CMOS

inmplementation offull adder

9.1,4 Ripple-Carry Adder

Definition
series, The
N-bit adder can be constructed by cascading N-full adders (FA) in
4
of first adder is connected as an input to the second one andit is continmed
Carry bit carry bit
This adder is called a Ripple-carry adder because the
l Nth adder.
pples from one state to the next stage.
 VLSI and Chip Design
9.8
A3 B3 A4 B4
A4 B4 Ag B2

C1 C2
Gin' FA FA FA FA Gout

So S1 S2 S3

Fig 9,8 Four-bit ripple-carry adder

The delay in a circuit depends on thè number of logic stages and the applied input
signal. For some inputs, no ripples occur, while for the other inputs, carry occurs,
which ripples from LSB to the MSB.

The propagation delay of such a structure (also called the

critical path) is defined as
the worst case delayover all possible input patterns.

Inthe case of the ripple-carry adder, the worst case delay happens only when a carry
generated at the LSB propagates all the way to
the MSB. This carry is finally
consumed in the last stage in order to
produce the sum.
The delay is then proportional to the
number of bits in the input word N
and it is
approximated by the following equation:

ladder (N- 1) carry

Sum
... (4)
.
where toarry
and Lsum
equals the propagation
delays from Cn to Cout and D,
respectively.

The above equation

(4) represents that
adder is linearly the propagation delay
proportionalto N. of the ripple -carr)Y
This property
adders for the wide
data paths is important when designing the
and future computers. (N= 16, 32, 64, 128) that are desirable both current
in
 Owehtial Digital Circuits

-
9,1.5 Carry Bypass (Skip) 9.9
Adder
Drawbacks: Why Ripple
-Carry Adder Not
The ripple-carry Used in High
Speed Adders?
adder is useful onty
lengths. for the implementation
Most desktop computers use of small word
word length of 32 bits,
64 bits. while servers require

Very fast computers such as mainframes, supercomputers,

processors require and multimedia
word lengths of upto 128 bits. The linear
dependence of the
adder speed is mainly based on the number
of bits which makes usage of ripple
adders and it is practically not good. Therefore,
the logic optimizations are
necessary.

Definition
The carry skip adder provides compromise between a ripple carry adder and a
Carry Lookahead Adder (CLA), It divides the words that to be added into the blocks.
Within each block, ripple carry is used to produce the sum bit and the carry.

The carry skip adder reduces the delay due to the carry computation that is by
stages.
Skipping over group of consecutive adder
in Fig 9.9 (a), suppose
that the values
Consider the four-bit adder block shown
are high.
= are such that over all propagate signals P& (k=0...3)
A and (k 0...3)
B

conditions through the

incoming carry C:0 which propagates under those
* An =l
causes an outgoing carry Co3 =1.
complete adder chain and ...
= 6)
P> P3 = 1), then Co.3 Ci,o
If (Po P; occurs.
DELETE or GENERATE
Else either of the adder.
used to speed
up the operation
of adder can be
The above property
which is shown in Fig 9.9 (b).
 VLSI and Chip Design

9.10|
P3 G3
Po Go P1 G1
P2 G2et
Co.2 Co,3
Co,1 FA
Co,0 FA
FA
Ci, 0 FA

(a) Carry propagation

P3 G3 BP= PóPiPzPa
G1 P2 G2
Po Go P

Co,1 Co.2
Co,0
FA FA FA Co3
C,o FA

a
(b)Adding bypass

Fig9.9 Carry-bypass structure-basic structure

When “Block Propagate" BP = Po Pi P2 P3 =
an incoming carry is forwarded 1,

immediately to the next block through the bypass transistor. Hence, it

is called as
carry-bypass adder (or) carry-skip addler. If this is not the case, the carry is obtained
by the way of the normal route.

(1) Carry Bypass in Manchester Carry-Chain Adder:

Fig 9.10shows the possible carry-propagation
paths when the full-adder circuit S
implemented in Manchester-carry
style. The carry propagates
bypass path, (or) a carry either throug the
is generated somewhere
in the chain.
In both the cases, the delay is
smaller than the normal
area overhead may ripple configuration.
incurred by adding
typically ranges the bypass path which is Small and it is
between 10 to
regular bit-slice 20%. Adding
structure. the bypass may breaks the path
 tial Digital Circuits

9.11
Po
BP

G,o

Go
G2 G3

BP

Fig 9.10Manchester carry-chain implementation

of bypass adder
(2) Computation of Delay
Let us now comnpute the delay of an N-bit adder. At first, we assume that the total
adder is divided into (N/M) equal-length bypass stages, each of which contains M
bits. The worst case delay pah is shaded in gray. An approximated total
propagation delay time expression is given as:
...
T9Nhy ,setip +M carry +
M
Tbypas t(M-1)oary tsum (6)

tcarry Propagation delay through a single bit. The The worst case carry

propagation delay through a single stage of M bits is approximately M

times larger.
of a single stage.
tbypass Propagation delay through the bypass multiplexer
sum of the final stage.
tsum Time to generate the
gray on the block diagram of Fig 9.11. From
The critical path is shaded in
in the
it follows that t, is still linear in the number of bits N, since
equation (6),
the first
at
Worst case, the carry is generated the
first bit position, ripples through
(N/M -2) bypass stages, and it is consumed at the last bit
block, skips around
carry.
position without generating an output
 VISI and Chip Design
9.12
Bit &-11 Bit 12-15
Bit 4-7
Bit 0-3
Setup Setup
setup Setup
Setip| tbypass

Cary
cary Carry
propagation
Carry
propagation propagaton
propagation

Sum Sum Sum tsum

M bits

Fig 9.11 (N=16) Carry-bypass adder

The optimal number of bits per skip block can be determined
by technological
parameters such as the extra delay
of the bypass selecting multiplexer, the
buffering requirements in the carry chain, and
the ratio of the delay through the
ripple and the bypass paths.
Fig 9.12 shows the propagation
delay of ripple -carry and
The ripple adder is actually faster
carry-bypass adders.
for smaller values of N. The cross -over
point
depends upon the technology
considerations and it is
normally situated betwe
four and eight bits.

tt
Ripple adder

Bypass adder

4.8
Fig 9.12 Propagation
delay of ripple-carry versus
carry-bypass adue
Ceguential Digital Circuits
9.13
1.6 Linear Carry-Select Adder
Drawback

In a
ripple-carry adder, every full-adder cell has to wait
for an incoming carry
before an outgoing carry can be generated.
Definition

Carry select adder is based on the principle to calculate the sum that is based on
assuming input carry from the previous stage. Sum and carry are calculated by
assuming input carry as l and 0
prior toan input carry comes.
When actual carry input arrives,
the actual calculated values of sum
Setup
and carry are selected using a
P.
multiplexer.
0 0 Carry propagation
An implementation of this idea, is
appropriately called the
1 1Cary propagation
Carry-select adder is demonstrated
in Fig 9.13. Co,k-1 Co,
k+3
Mültiplexer
Consider the block of adders,
to k+3, Carry vector
which is adding bits k
Instead of waitingon the arrival of Sum Generation

the output carry of bit k-l, both

.
the
Fig 9.13 Four-bit carry select module
0
and l possibilities are analyzed3
that is
two carry paths are
implemented.

When Co finally settles, either the result of the 0 (or) the

k
1 path is selected by the
a minimal delay.
multiplexer, which can be performed with
 VISI and Chip Design
9.14
Bi 8-11 Bit 12- 15
Bit 0-3
Bit 4
-7
Setup Setup
Setüp Setup

0-Carry
0-0Cary 0- 0-Carry o-0-Carry 0-
Cary 1 1-Carry
11arry 1- 1-Carry11-
Mutiplexar Multiplexer
-MOporer-Mütiperer
Go,3 Co. 11 Co.15

Sum generation |Sum generation |Sum generation Süm generation

So-3 S4-7 S8-11 S12-15

Fig 9.14 Sixteen-bit, linear carry-select adder

A full carry-select adder is now constructed by chaining a number of equal-length
adder stages, as in the carry-bypass approach which is shown in Fig 9.14.
The critical path is shaded in gray and a first-order model
the worst caseof
propagation delay of the module is expressed as,

Isetup + N ... (7)

add t M 'carry + M)
mux

Where tsetun, tgum are fixed delaysand

and tmux N and Mrepresents the total numbero
bits, and the number per
of bits stage, respectively. Tcarry is
through a single full-adder the delay of the cary
cell.
The carry delay
through a single block is
is equal to Mtcary: proportional to the length
of that stageO
The propagation deelay of
to N. the adder is linearly proportional
9.1.7 Square-Root
Carry -Select
To optimize
the above
Adder
Consider a design, it
16-bit is essential to locate
linear
carry-select adder
the critical timing path first.
and assume full-adder and
that the
Seauential Digital Circuits
9.15|
multiplexer cells have identical propagation
delays which is equal to a
value of 1. normalized
The worst case arrival times
of the signals- at the different network
respect to the time, nodes with
the input is applied and it is marked on
Fig 9.15 (a).
This analysis will represent
that the critical path of the adder
multiplexer networks ripples through the
of the subsequent stages.
&
Consider the muitiplexer gate
in the last adder stage. The
are the two carry inputs to this multiplexer
chains of the block and the block
multiplexer signal from the
previous stage and a major
mismatch between the arrival times
then be observed. of the signals can
The results of the carry
chains are stable for long enough before
signal arrives which makes sense
the multiplexer
to equalize the delay through
can be
both the paths. This
achieved by progressively adding more bits to
the subsequent stages in the
adder, requiring more time for the
generation of the carry signals.
Bit 0–3 Bit 4
-7 Bit 8 – 11 Bit 12 - 15
Setup Setup Setup Setup
J()
0
0-Carry 0-Carry 0 -Carry
0-Carry
(1)I
1 1- Carry 1-Carry 1-Carry 1-Carry
(5)J (5)
(6) (5)
Multiplexer Multiplexer Multiplexer Multiplexer

(9)
Sum generation Sum generation
|Sum generation |Sum generation
So-3 S4-7 Sg-11 S12-15 (10)

(a) Linear configuration

 VLSI and Chip Design
9.16|

Bit 0 - 1 Bit
2-4tk Bit
5- 8 Bit 9–13 Bit 14-19

Setup Setup Setup Setup

Carry 0-Carry 0-Carry

0-0- 0 0-Carry

1 1-Carry 1- Carry 1+ 1-Carry 1 1-Carry

(4) (5) J JL (6)
(4 (5) (6)
Multiplexer Mux
Multiplexer Multiplexer Multiplexer

Sum generation Sum generation |Sum generation Sum

Sum generation
Sg-13 (9) S14-19
So-1 Sp-4 S5-8

(b) Square root configuration

Fig 9.15 Worst case signal arrival times in carry-select adders

the third has 4, and
Forexample, the first stage can add 2 bits, the second contains 3,
so forth, as demonstrated in Fig 9.15 (b).
than the linear
Even though, the extra stage is added, this adder topology is faster
a adder.
organization. The same propagation delay is also valid for 20-bit
stage adds M bits. An
Assume that a N-bit adder contains P stages, and the first
then holds:
additional bit is added to each subsequent stage. The following relation
=
1) + (M + 2) +
(M+3)..... + (M +
P- 1)
N
M+ (M+

= MP+ PP-D-+P(M-}
2
•..
(8)

Ca
N = 64), the first term dominates, and equation (8)
If M
<<N (e.g., M=2 and
be simplified as,
p2 ... (9)
N (or) P=2N
 Circuits
SauentiallDigital
9.17
50

40 Rippie adier

delays)

unit
30

(in
tp Linear select
20

10
Squere root select

20 40
N

Fig 9.16 Propagation delay of square-root carry select adder Vs

linear ripple and select adder
Equation (9) can be used to express tdd as a function of N by rewriting
equation (8).

tadd setup t M Icarry+ (V2N)mug ...(10)

M).
The delay
is proportional to N
for large adders (N>> Fig 9.16 shows the
as a function
uelays ofboth the linear andsquare-root select adders which are plotted
ofN, For the large values of N, ada becomes almost a constant.

9.1.8
Carry Look ahead Adder (CLA)
1) Introduction
of the
10 Improve the speed of an addition operation, the carrY propagation delay
adder is limitation.
the major
9.18 VLSI and Chip Design

Although ripple carryadder is simple in logic, but it has a long circuit delay due
to many gates in the carry path from the LSB to the MSB. This ripple effect also

be present in both the carry-bypass and carry-select adders.

Among the various approaches, the principle of carry look-ahead adder will
reduces this problem by calculating the carry signal in advance, based on the
input signals.

(2) Monolithic Lookahead Adder

The following relation holds for each bit position in a
N-bit adder
Co= f4,, B.Cok-) = G+ P,C,k-l ... (11)
The dependency between Co and Cok can be eliminated
by expanding Cok-:
Co,k = G;
+PlGtPCok-2) ... (12)
In a fully expanded form,
Cok = G,
+P,(GtR..+ p(G,+ P,c, )) ...(13)
with C,o which is typically
equal to 0.
o. This expanded relationship can
then be used to implement an
every bit, the carry N-bit adder. For
and sum outputs are independent
the ripple of the previous bits. Thus,
effect has been effectively
eliminated, and the
addition time should be
independent of the number of bits.
A block diagram of
the overall composition
of a carry-lookahead adder is shown
in Fig 9.17. At the high-level
model, the constant
one and that addition time is.the very
the real delay is atleast useful
increasing linearly
with the number of bits.
Fig 9.18shows the possible
circuit implementation of
circuit exploits the self-duality
equation(13)forN=4.Th
and the recursivity
of the carry-lookahead
equation to build a mirror structure.
ial DigitalCircuits
Ao, Bo
9.19
A1, B1
.AN-1,BN-1 r

Cio Po Ci1 P1
CN-1 PN-1eB

So S SN-1
Fig 9.17 Conceptual diagram of a Carry-Look ahead Adder
Vop

-G3

G2

G1

Go

Cio
Co,3

Po

P1

P2

P3

mirrorof implementation
diagram
Fig 9.18 Schematic
offour-bit lookahead adder
 VLSI and Chip Design
9.20
values of N
The large fan-in of the circuit makes it prohibitively slow for larger
In order to implement this, even a simpler gates requires multiple
logic levels. In

both the cases, propagation delay increases and it seems to be the maior

limitations.

For instance, the signals Go and Po appear in the expression for every one of the
subsequent bits. Hence, the capacitance on thesé lines is substantial. Finally, an
area of the implementation grows progressively with respect to N.

(3) Logarithmic Lookahead Adder

E Drawbacks of Carry-lookahead Adder:

For a
carry-lookahead group of N bits, the transistor
implementation has N+1
parallel branches with upto N+ltransistors
in the stack. Since wide gates
stacks display poor performance and large
and the computation has to be limited upto two
(or) four bits in practice.

In order to build a very

fast adders, it is necessary
and generation into
toorganize a carry propagatio
recursive trees. A more
hierarchically decomposing effective implementation
the carry propagation b
into subgroups
Co,o = Go + Cyo of N bits:
P,
Co,l = G+P, Go+
PPCuo
(G+ P G)+ P,
P) C,o=Gio+ Pio
Co,2 = G,+ Co
P,G+ PP{G, +P,P,
Cos = G, +P, +
P, Cio= G, + P, Co,I
G, P, P, G + P,
P, P,Go+P, P, P
(G,+ P, G) + P,Ci,0
(P,P) Co,i=G2+
In equation P32 Co, 1 •.. (14)
(14), the carry-propagation
two bits. Gij process of
and Pi denotes
the generate and
is decomposed into
subgroups of
propagate
functions, respectively.
 Digital Circuits
oential
9.21|
for a group start from bit
of bits,
positions
generate and propagate signals. ito j. These are called as
block

o
If the group generates a carry
and independent of the incoming carry,
equals to 1. The block propagate then Gi:j

Pii is true if an incoming carry propagates

through the complete group. "This
condition is equivalent to the carry
bypass.
For example, G3:2 is equal to I
when a carry is either generated at bit position 3
(or) at position 2 and it is propagated through
position3.t
+ P, G,
G
G,

P32 = P3P2, when an incoming carry propagates

through both bit positions.

The format of the new expression for the carry is equivalent to the original one,
except that it generates and propagate signals which are replaced with block
generate and propagate signals.
=
The notation Gi:i and Pii generalizes the original carry equations, since G; Gii
and P; = Pii and a pair of generate and propagate functions is expressed as
as aseparate functions.
(, P;:i), rather than considering them

A Dot Operator ()
(), operator which is used on the pairs and
A new Boolean operator, called dot
combination and manipulation of blocks of bits:
allows for the
= (G+ PG, PP)
... (15)
(G, P) (G, P)
= P3) (Gz P2). This dot operator only obeys the
For example, (G, Pai) (G,
commutative.
associative property and not
 VLSI and Chip
9.22 Design

of operator, a tree can

exploiting the associate property the
dot
By be constructed

that is efiectively useful.to compute the carries

at all
2-1 positions ((that
is,I,3,
=
7, 15, etc) for i 1...log,(N).
The main advantage is that the computation of the carry position 2
-1takes only
log, (N) steps that is the output carry of an N-bit adder and it can be computed
in
og, (N) times.

For example, for an adder of 64 bits, the

propagation delay of a linear adder is
proportional to 64. For a square-root
select adder, it is reduced to 8,
while, for a
logarithmic adder, the proportionality
constant is 6.
Fig 9.19 shows the block diagram
of a 16-bit logarithmic adder.
15is computed by combining The carry at position
the results of
blocks (0:7) and (8:15).
turn, is composed hierarchically. Each of these, in
For instance, (0:7)
(4:7), while (0:3) consists is the composition (0:3) and
of
of (0:1) and (2:3), etc.
Computing the carrier
just at the 2 -1 positions
derive the carry signals is not sufficjent.
at the intermediate It is necessary w
this is by replicating positions as well.
the tree at every One way to accomy
= 16. bit position,as
ilustrated in Fig 9.19 for N
Forinstance, the carry
at position 6
(6:3) and (2:0). This is computed by
complete structure combining the results of blocks
member of the is referred as
radix-2 class trees.
of Kogge-Stone tree, which is a
Radix-2 means
that the tree
each level of is binary: It combines
the hierarchy. The the two carry Words atta time at
implement the total adder requires to
dot operator. 49 compleX:logic gates each
Additionally,
16 logic modules
generate signals
are needed
at
the first level for the generation- propagate and
of the
(P; andG), as
well as
16 Sum-generation gates.
 S4
9.23
S12 S13

O
Creation of
P
and G
signal

D O
D O O O O D o O o
- Dot operator
in look ahead
Bo) B1) B2) B3) B4) Bs) Bs) B7) Be) Bg) B10) B12) B13) B15)
B11) B4) tree
(A1, (Az. (Ag, (A4, (As, (A6, (A7, (Ag, (Ag,
(Ao. (A10. (A11, (A12, (A13, (A14, (A15, Sum generation

Fig 9.19 Schematic diagarm for Kogge-Stone 16-bit lookahead logarithmic adder

9.2 MULTIPLIERS

9.2.1 Introduction
computation process. Multiplications are expensive
* Multipliers plays a major role in in
used in digital signal processing and also
widely
andalso slow operations. It is
graphic engine etç.,
as microprocessOr,
high performance systems such power.
consumes considerable
latency and
have a large area, long one in
low power
udpiers has been an important
Therefore, low-power multipliers design

VLSI design system.

of
9.2.2 Multiplier The result
Definitions of
AND operation.
equivalent to logical
* Binary is
Multiplication
to get the
final output.
individual bit multiplication is added
 VLSI and Chip Design

9.24
Multiplicand (22)
10110 (9)
1001 Multiplier

10110
00000 Partial products
N O0000
10110
Result (198)
11000110

of binary multiplication
Fig 9.20 Anexample
upto times. M × N multiplication creates
means adding N M,
fo MxN multiplication partial products are added to get
bits each. The shifted
N partial products with M
M+Nbits in result.
ing the appropriate bits of the
multiplier and
Partial products are formed by AND
is added and if carry
occurs it is
multiplicand. Each column of the partial products
as X
us denote the multiplicand as Y and multiplier
passed to the next column. Let
and it is represented as,
Multiplicand, Y = (M-}M-2...., y1:Vo)
Multiplier, X = (N-|, XN-2 *...,*i Xo)

The result P can be then given as,

M-1

.j=0. \i=0

Multiplicand Multiplier
N-1 M-1
2'+J
i=0 j=0
For MxNMultiplication,
-
Nbit adder is used.
Mcycles are required.
Shift and add algorithm is used to get M
partialproducts.
 Circuits
SeguenttaI Digital

9.25
products are generated
All partial at the same
time and organized
Then, the final productis Computed in an array
using multi-operand
manner.
addition.

9.2.3 DOT Diagrams

Large
multiplications can
be more conveniently
a dot
illustrated using dot diagrams.
Fig 9.21 shows diagram for a simple
example.
Cach dot fepresents a placeholder for single
bit either 0.(or) 1. Partial products are
represented by a horizontal boxed row of dots, shifted
depending on their weight.
Y3 y2 y1 yo Multiplicand
Xo
Multiplier

Partial
X2 Y3 X2 Y2 X2 y1 X2 yo products
X3 y3 X3 Y2 X3y1 X3 Yo

P6 Ps P4 P3 P
P Po Prodcut

Multiplicand y

Multiplier x

X4
Partial
products

oteite

Productii3oni

Fig 9.21 M xN Dot Diagram

9.2.4
Partial - Product Generation: Booth's Multiplication
multiplicand X with multiplier bit
rartial product. is obtained by the logical AND of
Y; which is shown in Fig 9.22.
 VLSI and Chip Desigm
9.26|
Xo
X6 X5
X

PP; PP6 PP5 PP4 PP3 PP2 PP1 PPo

Fig 9.22 Partialproduct generation logic

Each row is either a copy of the multiplicand (or) a row of zeroes. Careful
optimization of the partial-product generation can lead to some substantial delay and
area reductions.

In most cases, the partial -product array has many zero rows that have no impact on
the result and thus represent a waste of effort when added. In the case
of a multiplier
which is consisting of all ones, all the partial products exist.

If X,is zero, then it will result in a row

of zeroes in partial product. This results in
excess time for calculation
of the partial product.
(1) Booth's Multiplication Algorithm (or) Encoding

Definition
Booth encoding is a method to reduce the
number of partial product. Simply it is a
multiplication algorithm that multiplis hwo signed
binary mmbers in two's
complement notation.

For Booth -n(number of bits)

Examines n+1 bits of the multiplier, and
Encodes n bits.
 Circuite
ential Digital

9.27

Yn
Yo

X-1 Operation
Shift only
4
Shift only

1 Subtract Shift -1
1
Addition Shift

Table 9.2 Booth Encoding.

Assume, for example, an eight-bit multiplier of the form 01111110, which
nonzero rows can be
produces six nonzero partial-product rows. The number of
a Here we are using
reduced by recording this number into different format.
Booth encoding table as follows:

1 1 1 1 1 1 0
0
Given:
0 0 -1

-1 (or) 1
Add 'o' at
LSB: 0. 0
0
0
4 0 0 -0 0 0 1

of booth
encoding
9.23 Example
Fig but the final adder
only two partial products,
we have to add also
Using this format, of transformation is
as well. Thistype
subtraction
has to be able to perform

called Booth's recording.

9.28| VISIand Chip Design

It reduces the number of partial products almost one half. It ensures that for every
two consecutive bits, at most one bit will be 1
(or)-1.

Advantages

Reducing the number of partial products is equivalent to reducing the number of

additions, which leads to speed up as well as an area reduction.

(2) Modified Booth's Recording

In the multiplier design, for a variable

-size partial product a modified Booth's
recording is most often used.

Ina modified Booth's recording, the multiplier

is partitioned into three-bit groups
that overlaps by one bit. Each group
of three is recorded, as shown in Table 9.3,
and forms one partial product.

The resulting number

of partial products equalsa half
input bits to the recording process are
of the multiplier width.The
the two current bits and gets
an upper combined with
bit from the next group which
is moving from MSB
toLSB.
PartialProduct Selection
Table
Multiplier Bits
Recoded Bits
000
001
+ Multiplicand
010 + Multiplicand
011
+2x Multiplicand
100
Ssu 101.
-2x Multiplicand
-Multiplicand
110
-Multiplicand
111
Table 9.3 Modified
Booth's recording
 Sauential. Digital Circuits

9.29
Example

2x

-2x
+X

= 4(+x)-2x
= 4x
-2x
=2x

Fig 9.24 Example of

modified Booth's recording

Multiplicand = 0010 = 2. i.e., binaryvalue. Here n

=4.i.e., number ofbits.
Add '0' to the right of LSB since first group has no group with which to overlap.

Examine 3 bits at a time.

Encode 2 bits at a time.

Overlap one bit between partial products.

9.2.5 Partial-Product Accumulation: Array Multipliers

structure. This multiplier circuit is
Array multiplier is. well known due to its regular
based on repeated addition and shifting
procedure. Each partial product is generated
of the multiplicand with one multiplier bit.
0y the multiplication

are shifted according to their bit orders and then added. The
Ihe partial product
normal carry propagate adder.
dddition can be performed with the help of
N x M
two-bit AND gates and
4 The generation of N
partial products requires
N-IM-bit adder.
9.30 VLSI and Chip Design

A3 A2 A1 A0
Inputs
X B3 B2
. B1 BO

B0 x A3 B0 x A2 BO xA1 BO × A0

x
B1 x A3 B1 x A2 B1 xA1 B1 A0

C Sum Sum Sum Sum

B2 x A3 B2 x A2 B2 x A1 B2 x A0 Internal Signals

C Sum Sum Sum Sum

+ B3 x A3 B3 x A2 B3 x A1 B3 x A0

C Sum Sum Sum Sum

Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO Outputs

Fig 9.25 Partial products

(1) Array Multiplier Using Ripple-Carry

Structureu
Although this method is simple, the delay was high
and also consumes large area
by using ripple carry for an array multiplication. A four bit multiplier for
bL unsigned numbers using ripple-carry is shown in
Fig 9.26. The addition is done
not only serially as well as in parallel.

HA stands for a half adder, or an adder

cell with only two inputs. The hardware
for the generation and addition one
of partial product is shaded in gray.
Cguential
Digital Circuits

9.31
Yo

HA
FA
FA HA

HA

Y3

FA FA FA HA

Z,
Z

Fig 9.26 4-bitmultiplication using Ripple-carry based array

multipliers
0 The partial sum adders are implemented as
ripple-carry structures. The
performance of this optimization requires that the critical timing path need to
be
identified first.

Anapproximated propagation delay for critical path 2 from the Fig 9.27 can then
be expressed as,

1) gum + tand ...

mult [(M- 1) + (N-2)]carry t (N- (16)
where,
lcarry. Propagation delay between input and output carry.
tsum Delay between the input carry and sum bit of the full adder.
tand Delay of the AND gate.
 VLSI and Chip Design
9.32

HAFAEAA Critical Path

Critical Path 2
1

FA
FAFA FA
--HA

FA
eFA FA HA

Fig 9.27 Simplified diagram of

ripple-carry base 4 x4 multiplier
(2) Array Multiplier Using Carry-Save Adders (CSA)

A Definition
In order to improve on the delay and area as welas speed ofa array multiplier, the
Carry Save Adders are used in which every carry and sum signal from one stage is
passed to the adders of the next stage. Fig 9.28 shows a 4
x4 carry-save multiplier.
Due to the large number of almost identical critical paths, a more efficient
realizatioñ can be obtained by that the multiplication result does not change when
the output carry bits are passed diagonally downwards instead passing only to
of
at o
betheright, as shown in Fig 9.28.
An extra adder called a vector-merging adder is used to generate
the final result.
nsit teThe resulting multiplier is called a carry-save multiplier, because the carry bits
are not immediately added,
but rather are "saved" for the next adder stage.
In the final stage, the carriers and sums are merged in a
fast Carry-Propagate
Adder (CPA) stage. While this structure has a slightly
increased area cost (one
extra adder), it has the advantage that its worst case
critical path is shorter ana
.c r
uniquely defined. Ie
Sayential! Digital Circuits
tial
9.33)

HA
HA HA

HA FA
FA

HA FA FA

HA
FA

Vector - merging adder

Fig 9.28 A4x4carry-save multiplier. The critical path is highlighted gray

in
An approximated propagation delay
for the worst case critical path then can be
expressed as,

Imult tand t (N-1) carry

+Imerge ...
(17)
where, Emerge Propagation delay of vector-merging adder

9.2.6 Tree Multiplier: Wallace Tree Multiplier

he tree multiplier realizes substantial hardware savings for larger multipliers. The
propagation delay is reduced as well. It is substantially faster than the carry-save
Structure for the large multiplier word lengths. t
s The tree structure helps in reducing both the critical path and the number of adders
cells is needed,. Consider the simple example of four partial products each of which
is four bits wide as shown in Fig9.29(a). Here only column 3 in the array has four
DItS, SO number offull. adders needed are reduced. All the other columns has less
complexity.
 VLSI and Chip Design
9.34
a tree shape to visuall.
The original matrix of partil products is reorganized into
in Fig 9.29 (b).
illustrate its varying path. This illustration is shown

Partial products First stage

1
6 5 4 2 1. 0 6 5 4 3 2 Bit
position

.(a) (b)
Second stage Final adder
6 5 3 2 0 65 4 3 2
)

FA HA

(c) (d)
Fig 9.29 Transfornming of partial-
product in to tree structure
(a) intoa Wallace tree(b,c,d)
The first type of operator that can be used to cover an array
is a full adder, which
takes three inputs and produces two outputs:
the sum is located in the same column
and the carry is located in the next one.
& For the above reason, the Full
Adder FA) is called as a 3-2 compressor. 1S
denoted by a circle covering three lt
bits. The Half- Adder (HA) takes two
in acolumn and produces two outputs. input bitS
It is denoted by a circle covering two
In the first step, we introduce bits.
HAs in columns 3 and 4 (Fig
is shown in Fig 9.29 (c). 9.29 b). The reduced treo
The second round reductions
of creates a tree of depth 2
shown in Fig 9.29 (d).
Sequential Digital Circuitt

Becausef this tree structure,

of 9.35
only three FAs
process, when this and three HAs are
is compared with six used for reduction
multiplier. Fig FAs and six HAs
9.30 shows the implementation in the
carry.
of Wallace tree multiplier.

*3 V3
x3 Y2
Partial products |X2Y3

First
stageris sn HA HA

FA FA FA FA
Second stage

Final adder
: -o

Sin3! 3
726 Z5 z4
0

Fig 9.30 Wallace tree for four-bit multiplier

M
Advantagestee
The advantages are,ea
of the tree multiplier ivg
()-The tree multiplier realizes substantial hardware saings for larger multipliers.
(1) The propagation delay is reduced as well.

A Wallace tree is an efficient hardware implementation of a digital circuit that

multiplies two integer numbers.
ot bot
thas three steps to be. followed:srst s.l
(9 Multiply each bit of the arguments, by each bit of the
other, yielding n'
2results.
wo by both layers of full and half
() Reduce the mumber ofpartial producis. to
adders.
 VLSI and Chip Design
9.36
a
(iti) Group the wires in two umbers, and add them with conventional adder.

Disadvantages

The Wallace multiplier has the disadvantage of being ery irregular, which

complicates the task in an efficient layout.

9.2.7 Final Addition

The final step for completing the multiplication is to combinethe result in the final
adder. This stage consists of a simple two-input adder, for which anytype of adder
can be used.

* A carry-lookahead adder is the preferable option if all inputs bits to the adder arrive
at the same time and also with the smallest possible delay. This is the case if a
pipeline stage is placed right before the final addition, which is actually a technique
frequently used in high-performance multipliers.

In nonpipelined multipliers, the arrival time profile

of the inputs to the final adder is
quite uneven due to the varying logic depths
of the multiplier tree.

9.3 SHIFT REGISTERS (OR) SHIFTERS

9.3.1 Introduction
Definition

Shifters are used to shift the

umbers from one bit position to the other. Shifts can
either be performed by a constant
(or) variable amount.
Constant shifts are trivial
in hardware, requiring only
shifters are as follows:
wires. The various types
Sequential Digtal Circuits 9.37

Shifters

Logical Shifter Arithmetic Shifter Barrel Shifter

Fig 9.31 Types of shifers

(1) Logical Shifter

It is used to shiftthe number to the left(or) right and empty spots are filled with O's.
Example: 1011
(i) Left shift (i) Right shift

Extrazero Extra zero

(2) Arithmetic Shifter

but sign bit is inserted in MSB.
If is similar to logical shifter
Example: 1011 =
ASRI = 1101& ASLI 0110

1011
1011 1011
Shift right
1
101

Sign bit
1011 1011
Shift left
0110.
Sign bit
|9.38 VLSI and Chip Design

(3) Barrel Shifter

II ivolves, rotates numbers in a

circle such that empty spots are filled with bits
shifted at an other end.
Example: 1011
ROR 1= 1101 &
ROL1.= 0111

1011 Shift Right 1011 = 1101

Shift Left 101 =

0111

9.3.2 Barrel Shifter

The structure of a barrier shifter is
shown in Fig 9.32. It consists
transistors, in which the number rows are of an array
of equals the word length of the data,
the number of columns equals the and
maximum shift width respectively.
both set are equal to four. The control In this case,
wires are routed diagonally through the array.
Fig 9.32 shows the Barrel shifter
with a programmable shift width
bits to the right. The structure supports from zero to three
automatic repetition of the sign
called sign-bit extension. bit (As), also
A
major advantage of this shifier
isthat the signal has topass through at most one
transmission gate. The capacitance
at the input of the buffers
maximum shift width. rises linearly with the

Barrel shifter needs a control

wire for every shift bit.
needs four control signals. For exanple, a four-bit
To shift over three bits, shifter
value 1000, where only one the signals :
Sh, Sho take on the
of the signals is high.
A barrel shifter performs a
right rotate operation. can
using complementary It also handle left rotation
shift operation. By using
suitable masking hardware,
shifters can also perform barel
shifting.
 Seguential Digital Circuits

19.39
Barrel shiifters are available in two forms
as:
() Array form.
(iü) Logarithmic form.
Tagarithmic barrel shifter is
widely used and they are better suitable
for large shifts.

Ag

Data wire
Sh Control wire

Sh2
A1
B

hti
Sh3__
Ao
Bo

Sh2 Sh3
Sh Sh
shifter
Fig 9.32 4 x4 Barrel

Advantages
barrel shifter are,
Ihe main advantages
of
mumber of bits without the use of any
word by a specified
() It can shift a data combinational logic.
only pure
Sequential logic, microprocessors, typically
n-bits in modern
to shift and rotate
("9 tis ofien used
cycle.
within a single clock an.implementation
multiplexers andin such
as a sequence
of
way that
implemented next MUX in a
(ii) It can be of the
connected to an input
one MUX is
c4 Output of
distance.
depends on the shift
.401
VLSI and Chip Design

.3.3 Logarithmic Shifter

The barrel shifter implements the whole shifter as a single array of pass transistors
but the logarithmic shifter uses a staged approach. The total shift value is
decomposed intoshifts over powers two.
byo.of

shifter with a maximm shift width of M consists of a log, M stages, where the ih
A

stage either.shifts over 2' or passes the data unchanged.

An example of a shifter with a maximum shift value of seven bits is shown in
Fig 9.33. For an instance, to shift over five bits, the first stage is set to shift mode,
the second to pass mode, and the last stage again to shift.
The control word. for this shifter is already encoded, and no separate decoder is
required. The speed of the logarithmic shifter depends on the shift width in a
logarithmic way, since a M-bit shifter requires log,M stages.

The series connection of pass transistors may slows the shifter down for larger shift
values and an intermediate buffers are necessary.

Sh
Sh Sh, Sh2 Sh Sh4 : Data Wire

:Control Wire

As B3

A2
B2

A1
B.

Ao
Bo

Fig 9.33 Logarithmic shifter with maximal shift width of seven

bits to the right
 Digital Circuits
ial
Advantages 9.41
The advantages of 1logarithmic shifter
are,
For smallershifters, Barrel
() shifter is appropriate.
logarithmic shifter becomes For larger shift values, the
effective,
o
in terms of
both area and speed.
tis easily parameterized and allows the automatic generation.
Ai) This
circuit regularity in an arithmetic operator can
leàd to dense and high
speed circuit implementations.

9.4 COMPARATORS

A Definition
A
comparator has twoinputs and three output bits that say whether the first input
is: greater, less, or equal to the second input.

9.4.1 Magnitude Comparator

compares two digital
a A
magnitude digital comparator is a combinational circuit that
or binary numbers in order to find out whether one binary number is equal, less
output terminals as:
than, or greater than the other binary number. It has three
() One each for equality, A =B
() Greater than, A> B, and
<
(iii) Less than B.A

C =AB A<B
A

-D= AB+AB A=B

EAB A>B

B.

Comparator Circuit
Fig 9.34 1-bit Digital
 VLSI and Chip Design
9.42

The binary or digital comparator can be constructed using

standard AND, NOR and N0T gates to compare the digital signals present at their
input terminals and produce an output depending
upon the condition of those inputs,

Inputs Outputs
B A A>B
A
=B A <B
0 0 0
0 1
0

1
0 1

1 1 1
0
Table 9.4 Truth table of magnitude comparison
(1) 4-bit Magnitude Comparator
Binary Binary
Inputs A Inputs

Ao A1 Az A3
(LSB) (MSB)
B B B
B3
(LSB) (MSB)

A<B
4-bit Magnitude
Comparator A=B Comparison
Outputs
A>B

Fig 9.35 4-bit magnitude

comparator
The 4-bit magnitude' comparator
have
additional input terminals
individual comparators that allow more
to be "cascaded together
4-bits with magnitude to compare
comparators
inputs are connected directly of "n"-bits being produced, words larger than
to. the corresponding These cascading
comparator as shown outputs of the previous
to compare 8, 16 or even
32-bit words.
 Sequential Digital Circuits

9.43
9.4.2 Equality Comparator
An equality comparator determines =
4
ncing XNOR gates
if (A B), This can be done more
simply by
and one detector as shown in Fig 9.36.

B[3]
rA[3]
B[2]
A[2)
A=B
B[1]
A[1]

B[O]

hieLtA[O]
Fig 9.36 Equality comparator

9.5 TWO MARKS QUESTIONS AND ANSWERS

1. Write the full adder output in terns of propagate and generate.

[APRMAY-2018]
Consider A and B are the inputs of an adder. Then the full adder output in terms of
propagate and generate can be expressed as,
P = AB
G = A B
4 Express the sum fulladder.
of

Consider, are of an adder, is the carry input andS is the sum

C

and
A B
the inputs
sum can be obtained by using K-map is
output. Then, the logical expression for

expressed as,

ABC+ ABC+ ABC

+
ABC
Sum, S=
 VLSI and Chip Design
9.44
= (BC+ BC) + A
(BC + BC)

= A
(B C) + A
(B C)
B C

S= A

The Sum logical expression in terms of propagate signal (P) is given as,
=
S (A O B)
C=PC
where, P. = AB
3. Express carry of
full adder.
Consider, and B are the inputs of an adder, C is the carry input and S is
A

the sum
output. Then, the logical expression for carry can
be obtained by using K-map is
expressedas,

Carry, Cot = ABC + ABC+ ABC+ ABC +

ABC + ABC

BC (A + ) + AC (B + B) + AB (C +
C)
= BC+ AC+ AB
=
AB + BC+ AC= AB+ C(A+B).
Caut =MAJ (A, B,C) (Majority
of A,B,C)
4. Draw the structure of full adder.

A.

Sum =AB C

Cout
=AB+ BC+AC
 al Digital Circuits

What do you mean

by riPple-carry adder?
A
N-bit adder can be
constructed by cascading
aorry bit of N-full adders (FA) in
first adder is connected as an series. The
input to the second one
tillNth adder. This adder is called a and it is continued
Ripple-carry adder because
from one state to the next stage. the carry bit ripples

s Draw the structure

ofripple-carry adder.
NOVDEC -2017
A1 B1 A2 B
A3 B A4 B4

C1
Cin FA FA FA FA Cout

So S4 S S3

List the drawbacks of ripple carry adder.

NOVDEC -2017]
(or)
Whyripple-carry adder is notused in high speed adder?
The main drawbacks of ripple carry adder are,

) The ripple-carry adder is useful only for the implementation of small

word lengths. Most desktop computers use word length of 32 bits, while
servers require 64 bits.

(ii) Very fast computers such as mainfranes, supercomputers, and

multimedia processors require word lengths of upto 128 bits. The linear
dependence of the adder speed is mainly based on the number of bits
which makes usage of ripple adders and it is practically not good.
Therefore, the logic optimizations are necessary.
 VLSIand Chip Design
9.46|

8. What is meant by carry skip adder?

The carry skip adder provides compromise between a ripple carry adder anda Carry
Lookahead Adder (CLA) adder. It divides the words that to be added into the blocks.
Within each block,ripple carry is used to produce the sum bit and the carry.

The carry skip adder reduces the delay due to the carry computation that is by
skipping over group of consecutive adder stages.
9. Define carry select adder.
Carry select adder is based on the principle to calculate the sum that is based on
assuming input carry from the previous stage. Sum and carry are calculated by
assuming input carry as I and O prior to an input carry comes.
When actual carry input arrives, the actual calculated values of sum and carry are
selected using a multiplexer.
10. Determine propagationdelay of
n-bit carry select adder. [APRMAY-2016]
The propagation delay of the n-bit carry select adder is expressed as,

Ladd setup + M çarry t

where tsetup, tsum and tmux are fixed delays and N and M represents the total numberof
bits, and the number of bits per stage, respectively. Tearry is the delay of the carry
through a single full-adder cell.
11. Write the drawbacks of'carry-look ahead adder.

For a carry-lookahead group of N bits, the transistor implementation has N+!

parallel branches with upto N+1 transistors in the stack. Since wide gates and large
stacks display poor performance and the computation has to be limited upto two (or)
four bits in practice.
 Digital Circuits

9.47
Booth encoding (or) algorithm.
a
Rooth encoding is methodto reduce
the number of partial
multiplication algorithm product. Simply it is a
that mltiplies two
signed binary numbers
notation. in two's
complement

What is Carry save adder?

In improve on the delay and area as well as
order to
speed of a array multiplier, the
Carry Save Adders are used in which every carry
and sum signal from one stage is
passedto the adders oftthe next stage.

4 What is array multiplier?

Fach product terms are the implemented using an array structure
of AND and OR
gate hence it is called array multiplier.

. What are the different types of

multipliers available?
The different types of multipliers are,
Array multiplier.
Booth multiplier.
Wallace tree multiplier.
List the advantages of tree multiplier.
Ihe advantages of the tree multiplier are,
hardware savings for larger
() The tree multiplier realizes substantial
multipliers.
reduced as well.
(ii)
Ihe propagation delay is
What are
shifters?
Shifters one bit position to other. Shifts can either
are used toshift the numbers from
be performed amount. Constant shifts are trivial in
by a constant (or) variable
hardware, of shifters
are as follows:
,requiring only The various types
wires.
 VLSI and Chip Design
9.48

(i) Logical shifter.

(ii) Arithmetic shifter, 3s: : bon: Eaogena

Barrel shifter, ohahe ods nsglu
(ii)
18. Define logical shifier with an example.

Logical shifter is used to shift the number to the left (or) right and empty spots are
ti filled with 0's.

Example: 1011 :iz i

LSL1= 0110 &LSR1 = 0101
n
(i) Left shift (ü)Right shifths

0
110 0 |1lo1
Extra zero Extra zero
19. What is barrel shifter?
A barrel shifter is a digital circuit
that can shift a data word
bits without the use of any sequential
by a specified number of
logic, only pure combinational
used to shift and rotate logic. It is often
n-bits in modern microprocessors,
clock cycle. typically within a single
Barrel shifter rotates
numbers in a circle
shifted at an other such that empty spots are
end. Example: filled with bils
1011; ROR 1
=1101 & ROLI =0111
1011 Shift Right
101 = 1101
Shift
Left1011 0111 sie
 Seguential Digital Circuits
l 9.49
Draw the
structure of 4 x4 barrel shifler.sgo
20. 2fAPR/MAY-2018]

Ag

Data wire
Sh ---. Control wire
A2

Sh2
A1
- B,

Sh3

Ap
Bo

Sh Sh Sh3
Sh
very useful in the designing of arithmetic circuits?
4. Why is barrel shifier
NOVDEC-2018]
(or)
[NOVDEC-2019]
State the merits ofbarrel shifier.
are,
The main adyantages of barrel shifter
without the use of any
number of bits
can shift a data word by a specified
() t pure combinational logic.
Sequential logic, only
microprocessors, typically
to shift and rotate n-bits in modern
() It is often used
within a single clock cycle.
an
sequence multiplexers and in such
as a of
() It can be implemented an input of the next MUX
connected to
implementationan output of one MUX is
distance.
in a way that depends on the shift
 VLSI and Chip Design
9.50|

22. Write the advantages of logarthmic shifler.

are,
The advantages of logarithmic shifter
values.
() For smaller shifters, Barrel shifter is appropriate. For larger shift

logarithmic shifter becomes effective, in terms of both area and speed.

(i1) It is easily parameterized and allows the automatic generation.

can lead to dense and high-speed
(ii) This circuit regularity in an arithmetic operator
circuit inplementations.
23. Draw the dot diagram for Wallace tree multiplier.

NOVDEC-2020 & APRMAY-2021)

Partialproducts First stage

6 5 4 3 2 1 6 5 4 2 Bit
position

(a) (b)

Second stage Final adder

4 3 2 1 6 5 4 3 2
6 5

HA
FA
(c) (d)
N. Define.magnitude comparator. 9.51
A magnitude digital comparator
numbers
is a combinational circuit
or binary in ordertofind out that compares
whether one two digital
or greater than the other binary number
binary number. is equal, less than,
It hasthree output
(i) One each forequality, = terminals as:
A B
(ii) Greater than,
A>B,and
(iii) Less than A < B.

9.6 REVIEW QUESTIONS

1 DiscuSs in detail about the full adder

with suitable expressions.
2.
Draw thestructure of ripple-carry adder
and explain its operation.

NOVIDEC -2017|
3. How the drawback in ripple carry adder overcome carry
by look ahead adder and
discuss.
[NOV/DEC -2017|
4. Explain indetail about
theCarry-Bypass adder with neat sketches.
Explain the operation of a basic 4-bit adder. Describe
the different approaches of
improving the speed of the adde.
[NOVIDEC-2016]
Design a
6-bit carryby pass and carry select adder and discuss their features.

[APR/MAY-2016)
7.
Explain carry look ahead adder and discuss its types.
the concept of

JAPRIMAY-2017& APRMAY-2018)
&.
Derive
the hecessary expression of a 4-bit carry look alhead adder and realize the
carry out logic.
expressions using Dynamic CMOS [APRMAY-2019]
9. Discuss with suitable sketches.
in detail about the logarithmic look akead adder
 VLSI and Chip Design
9.52|

multiplication with suitable examples? Justify ho

10. Explain the operation of Booth
process.
Booth's algorithm speed up the multiplication
NOVIDEC -2016]

modifiedBooth multiplier with a suitable example.

I1. Explain the concept
of

[APRMAY-20177

12. Design 4 x4 array multiplier and write down the equation for delay.
[APRIMAY-2016]

13. Construct 4 x4 array multiplier and findits critical path delay.

[NOVIDEC -2018]
14. Design a 4-bitunsigned array multiplier and analyze its hardware complexity.
[APRIMAY-2019, NOVDEC-2019)
15. Discuss in detail about Tree multiplier with neat sketches.
16. Write note on Wallace tree multiplier.
NOVDEC -2017|
17. Design 4-inputand 4-output barrel shift adder
using NMOS logic.

[NOVDEC -2018]
18. Design a 4-bit barrel shifter.
[NOVDEC-2019
19. Explain the working
principle of logarithmic shifter, with neat sketches.
20. Explain the carry-propagate
adder and show how the generation
signals are framed. and propagation
[NOVIDEC-2020 & APRMAY-2021/
21. Listthe several
commonly used shifters. Design
commonly used shiflers. the shifter that can perform au
tn
22, Discuss NOVDEC-2020 & APRMAY-2021|
in detail aboutcomparators
with neat sketches.
 UNIT- IV

Chapter 10
Logic Implementation using
Programmable Devices
10.1 PROGRAMMABLE LOGICARRAY (PLA)

a Definition:

A Programmable Logic Array (PLA) provides a regular structure for

implementing combinational logic specified in sum-of-products canonical form.
If outputs are fed back to inputs through registers, PLAs also can form Finite
State Machines(FSMs).

* Any logic function can be expressed in sum-of-products form; i.e., where each
output is the OR (sum) of the ANDs (products) of true and complementary
inputs. The inputs and their complements are called literals.
Inputs

AND Implicants OR
Array Array

Outputs

Fig 10.1 Basic structure PLA

of

* Fig 10.1 shows an Mx NxP-bit PLA has M

inputs, N
implicants (or) minterms
and P outputs.
 VLSI and Chip Design
|10.2

& The AND of a set of literalsis called a product or minterm. The outputs are ORs

of minterms. The PLAconsists of an AND plane to compute the minterms and

an 0R plaune tocompute the outputs.
We use DeMorgan's law to replace the AND and OR gates with inverting inputs
and outputs, as shown in Fig 10.2 and the representation of PLA with a dot

diagram as shown in Fig 10.3.

AND Plane OR Plane

bc

ac

ab Minterms

abc

abc

abc

abc

b
Inputs Cout
Outputs

Fig 10.2 AND/OR representation of PLA

Expcrienced designers often add
few unused rows and columns to their PLAS
to accommodate last-minute design changes
without changing the overall
footprint of the PLA.
 ie Inplementation using Programmable
Devices
10.3|
AND Plane
OR Plane

bc

ac

ab

abc

abc

abc

abc

Fig 10.3 Dot diagram representation of PLA

10.1.1 Pseudo-nMOS PLA:
a
Most of PLA structures employ pseudo-NMOS NOR gates using P-channel
device in place load. Unlike complementary CMOS
of the NMOS depletion
power under static conditions (since the P
circuits, these gates will dissipate
device is always on).
must be ratioed in order to create the required low
* The P and N channel devices
slower a gate, although there is a trade-off
Output voltage. This ratioing results in
power dissipation.
between gate speed and static
pseudo-nMOS. NOR gate, Fig 10.4 shows the circuit diagram
PLA uses a
A
small
for the fulladder PLA.
Advantages
Simplicity and small size
Disadvantages:
NOR, gates.
(i) Static power
dissipation of the
(ii) Slow pullup
response, und
synthesis flowtoday.
into a conventional logic
(i) Itdoesn't fii
10.4 VLSI and Chip
Design

ANDPlane OR Plane

bc
HL. HLHH

ac
.........
HL
ab
H
abc
H HI
abc
HL HLHI
abc

abc
HE

a b C

Cout

Fig 10.4 Pseudo-nMOS PLA schematic

10.2 FIELD PROGRAMMABLE GATE ARRAY(FPGA)

10.2.1 Introduction
a Definition of FPGA
A
Field Programmable that
Gate Array (FPGA)
Supports animplementation is a programmable logic device
of relatively
large logic circuits. FPGAS can be used
to implement a logic
circuit with more than
20,000gates.
FPGAs are popular gap
with Microsystems
designers because they fill the
between TTL and PLD design
and also expensive ASICs.
 Implementation using Programmable Devices 10.5
Logie

FPGA is completely programmable logic device even after a

product :is delivered.
are constructed with high
These ICs circuit density processes. There are two
basic versions of FPGA. They are,

/) Antifuse based FPGA

An antifuse is normally high resistance (>100 M). On an application of

appropriate programming voltages, it is changed permanently to a low

resistance structure (200-500 S2).

Devices based on antifuse technology are one tine programmable. An antifuse

initially provides insulation between two conductors, but when the sufficient
programming voltage is applied across it, conducting path forms.
can not be
o II is one time programmable, once an antifuse is blown and it
removed. There aretwo classes of antifuse technology:

() Poly-diffusion antifuse.

(i) Metal-metal antifuse.

E Merits
(i) Highest density.
resistance.
(ii) Lowest switch
capacitance.
(ii) Very low
(iv) Non-volatile.
easy to place and route.
(v) Software is 2

(2) Static RAM (SRAM) based FPGA

The SRAM based FPGA uses SRAM cells, which
are used to customize the

routing and logic functions.

(or) 1.
Storing logic value either 0
-
Storing value of Look up Table (LUT) in logic
blocks
FPGA.
Toconfigure an interconnection of
Reprogramming of SRAM is possible.
10.6
VLSIand
Chip Design

Floor planning is the method of allocating resources in FPGA to me

requáred time constraintsthat is arrangingthe blocks of netlist on the chip.

a Characteristics of FPGA
are:
The important characteristics of FPGA

None of the mask layers are customized.

-
It is a method for programming the basic logic cells and I also an interconnect.

The core is array of programmable basic logic cells that

a regular cm

Implement combinational as well as sequential logic(Nip-flop).

A
matrix of programmable interconnect surrounds the basic-logic cells.

Programmable VO cells surround the core.

Design turn around time is about few hours.

10.2.2 General FPGA Architecture

4 The basic building blocks of FPGA are,

() Logic Cells (LCs):

Programmable Logic Cells (LC) grouped into Configurable Logic Blocks
(CLBS), which implement the logic functions.

(0) Programmable Interconnects:

Programmable routing that connects these logic
functions.

(0) VO Blocks:

I0 blocks that are connected to

logic blocks through the routing
interconnect

and that make-offchip connections.

An configured
FPGA chip consists of a
regular array of basic logic cells that are
using a programmable technology routing
that is surrounded by programmable
resourocs
functions.
Logic blocks can be configured
to perforn complex combinational
Ugually, the logic blocks consist
of flip-flops or other blocks of memory.
Logic.Implementation using Programmable Devices
10.7
The programming technology
in an FPGA determines the type
of basic logic cell
and an interconnect scheme.

blpck

Configurable Configurable
Logic
Configuráble
Logic Logic
Block:(CB) BIock(CLB Block-(CLB)

rnterconecta matriYd

Configurable Configurable Configurable.

Logic Logic Logic
Block (CLB) Block (CLB) Block (CLB)

|/Oblock

Fig10.5Architecture of FPGA

Programmable
Logic cel

LC| |LC LC

LC LC| LC|
Programmable
interconnect

LC| |LC| LC| LC|

Programmable
WO cells (or) blocks
LC| LC

Fig 10.6 Configurable logic blocks (CLBs)

 VLSIand
Chip Design
10.8|
are different
outputs use special VO logic cells that fromthe
The chip inputs and
very fast /Os and bidirectional data buses and
basic logic cells. FPGA employs
within the setup time and hold time
the valid data should be obtained
forms the wiring between thetwo types
programmable interconnects scheme
A

logic cells. Finally, the designer uses custom software,

to each programmi
of
technology and FPGA architecture, to design and implement the programmable
connections.

(1) Configurable Logic Block (CLB)

A
CLBisa basic component of a FPGA that provides the basic logic and

storage functionality for a target application design.

The CLB acts as the main logic resource for implementing logic circuits.
Generally, the CLBs contain RAM based LUTs to the implement logic and
storage elements that can be used as flip-flops (or) latches. CLBs can be
programmed to perform various logical functions as well as to store data.

Every CLBconsists of a configurable switch matrix

with 4 (or) 6 inputs, Some
selection circuitry (MUX etc), and flip-flops. The
switch matrix is higny
flexible and can be configured to handle
combinational logic, shift regs
(or) RAM.

(A) Logic Cells:

Each logic blocks a

is FPGA which typically inputs
and outputs. The most has a smaller number of
commonly used Table
(LUT), Which logic block is a Look- Up
contains storage cells
that are used implement a smalllogic
function. to
Each cell
is capableof holding a
singlelogic value, or 1.The
ctored value which is
either 00
is produced as an
output sizes
may be created, ofthe storage cell. LUTS of various
where the
size is defined by
the number of inputs.
 etton using Programmable
Devices

TwoInputLUT: |10.9
Figure 10.7 shows the structure
of a small LUT.
and one output, fj. It is capable It has two inputs, X1
of implementing
and x
variables. any logic
function of two
Since the two-variables truth
table has four rows,
cells. One cell this LUT has four storage
corresponds to the output
value in each row
of the truth table.
The input variables X]
and X2 are used as the
selective inputs of three
multiplexers, which
depending on the valuation
content of the
of x and x2, which select the
four storage cells as the output
of the LUT.

O/1
O/1
0
O/1 0 1
0
O/1 1

1 1 1

a)Circuit for a two - input LUT b) f = X1 X2

t X4 X2

c) Storage cell contents in the LUT

Fig 10.7 Circuits for a two-input LUT

 VLSI and Chip Design
|10.10

(2) i/0 Blocks

Each bank can be configured individually to support
a particular WOstandard

It allows the FPGA to work I/O standard FPGA

with device using multiple

can actually be used as an interface between different I/O standards.

Modern FPGA output signals with fast edge rates require termination t
prevent reflections and maintain signal integrity.

o High pin count package cannot accommodate external termination registere

Thus a Digitally Controlled Impedance (DC) is employed and it eliminates
the need for external register and also improves signal integrity.

(3) Programmable Interconnect

A programmable switch matrix forms the heart of interconnect in a FPGA.

The actual switching matrix employed a structure of six pass transistors per
cross point. Thus, the connectivity can be established by controlling the

transistors and the various type of connections used are:

() Single lines

Used to connect a CLB to another CLB which is one hop away. These
wires have
to gothrough a programmable switch hence add delay.

(ii) Double lines

These wires travel across past two CLB before

hitting the Switch, hence thney

provide shorter delays for longer connections.

(ii) Long lines

Wires in
long groups do not go through any instead
programmable switch at all,
they travel all the way across a
(or) down a row (or) column and can driven by
tri-state drivers.

(iv) Global clock lines

These lines are optimized the

providing the
for the case as clock inputs to CLB,
short delay and minimal skew. the
 plemetation using Programmable
Devices

TWO MARKS OUESTIONS 10.11

AND ANSWERS
Whatdo ean by PLA?
you mean
A Programmable Logic
Logic Array
implementing combinational
(PLA) provides
logic specified a regular structure
are fed back to inputs in sum-of-products for
If outputs
through canonical form.
State Machines (FSMs). registers, PLAs also can
form Finite
2 Define FPGA. (or)
What is the
significance of FPGA? (NOV/DEC-2020
AA
&APRMAY-2021]
Field Programmable Gate Array
supports (FPGA)
is a programmable
an implementation logic deviçe
to implement
of relatively large logic circuits. FPGAs can that
a logiccircuit with more than 20,000 gates. be used

3 What is an
antifuse? State its merits and demerits.
NOVDEC-2016]
An antifuse is normally high
resistance (> 100MQ). On an
application of
appropriate programming voltages,
it is changed permanently to a low-resistance
structure (200-500
).
Devices based on antifuse technology are one time programmable.
An antifuse
Initially provides insulation between two conductors, but when the sufficient
programming voltage is applied across it, conducting path forms. There are two
classes of antifuse technology:
i) Poly-diffusion antifuse.
(i) Metal-metal antifuse.
Merits:

() Highest density.
(ii) Lowest switch resistance.
(ii) Very low capacitance.
(iv) Non-volatile.

() Software is easy to place and route.

 VLSI and
Chip
10.12 Design

Demerits:
one time programmable, once an
antifuse is blown and it can
It is not be
removed.

4. Defnefloor planning.

Floor planning is the method of allocating resources in FPGA

to meet
the
required time constraints that is arranging the blocks of netlist on the chin

S. List the important characteristics of FPGA.

The important characteristics of FPGA are:

None of the mask layers are customized.
It -is a method for programming
the basic logic cells and also an
interconnect.
k.
The core is a regular
of programmable basic logic
implement combinational as
cells that can
well as sequential logic (flip-flop).
A matrix of programmable
interconnect surrounds
the basic-logic cells.
Programmable I/O cells
surround the core.
Design turn around
time is about few hours.
6. State the
three important blocks in FPGA
architecture.
(OR)
State the building
blocks ofFPGA.
The basic building [NOVDEC -2019)
blocks of FPGA are,
() Logic Cells
(LCs): Programmable
Configurable Logic Cells into
Logic Blocks (LCs) grouped
(CLBs), which
() Programmable implement the logic functions.
Interconnects:
logicfunctions. Programmable these
routing that connects
(tii) VOBlocks:
/O blocks that are
interconnect connected routing
andthatmake-off tologic blocks through the
chip connections.
 Implementation using
gie Programmable
Devices

What isCLB? 10.13|

Programmable Logic Cells
(LCs) grouped
(CLBS), which- implement
the logicfunctions.
into Configurable
Logic Blocks
that provides the basic It is a basic component a
logic and storage of FPGA
functionality a
design. for target application
Name the elements
8
in a configuration logic blocks(CLBs).
The CLB acts as [APRMAY-20177
the main logic resource
Generally, the for implementing logic
CLBs contain RAM circuits.
based LUTs (Look-Up
the logic and storage Tables) to implement
elements that can be used as
In CLBs, flip-flops (or) latches.
logic blocks also requires

i) JO blocks -Tointerface with external

signals.
() -
Routing channels To interconnect
logic blocks.
9. Write the advantages
of FPGA.
The advantages
of FPGA are:
(1) Very fast custom logic.
(ii) Massively parallel operation.
(ii) Reprogrammable at any time.
(iv) More flexible than dedicated chipsets.
10, What
are the two different types of
routing in VISI? [APR/MAY -2018]
The
two different types of routing in VLSI are,

) Global routing, and

(i) Detailed routing.
10.4
REVIEVW
QUESTIONS
Brief
about PLA.
2
Draw
and explain the building blocks ofFPGA.
[APRIMAy-2017. NOVDEC-2017, APR/MAY-2019, NOVDEC-2019)
3
Illustrate FPGA.
the base building block architecturè of

NOVDEC2020 & APRMAY-2021)

 UNIT -IV

Chapter 11

Designing Memory
Array Structures
andn
11.1 MEMORY CLASSIFICATION
4 Semiconductor memories are most
often classified on the basis of memory
functionality, access patterns, and the nature
of the storage mechanism.
& Most of memories belong to the random-access class, which means memory
locations canbe read (or) written in arandom order.

* Random Access Memory (RAM) is commonly classified as

Read-Only Memory
(ROM) and Read/Write Memory (RWM).

Ihe RWM structures have an advantage of offering both read and write
Junctionalities with comparable access times and the most flexible memories.
Datas are stored either in flip-flops (or) as a charge on acapacitor.

A more
useful classification of RAM is volatile and nonvolatile memory.
Volatile
memory can retains its data as long as power is applied, while
nonvolatile memory
will hold data indefinitely.
RWM
is Synonymous with volatile memory, while ROM is synonymnous with
nonvolatile
memory. Read only memory can encode the information into circuit
lopology
 LSIand Chip Design
11.2
Memory Arrays

+
Serial Access Memory
Content Addressable
Random Access Memory Memory (CAM)

Shift
ReadWrite Memory Read -Only Memory Queues
(RWM)(Volatile) (ROM) (Nonvolatile) Registers

Static Dynamic Serial In Parallel In First In Last In

RAM RAM Parallel Serial out First out First out
(SRAM) (DRAM) out (SIPO) (PISO) (FIFO) (LIFO)

Mask Programmable Erasable Electrically

ROM ROM
Flash
Programmable Erasable ROM
(PROM) ROM Programmable
(EPROM) ROM
(EEPROM)

Fig 11.1Classifications
ofmemory arrays
The volatile memories can
further be divided into
structures. The
static structures and dynamic
static will retain their
data as long as the supply
retained, while dynamic voltage 1s
need periodic refreshing to
compensate
loss caused by the leakage. for the charg
The members
of the nonvolatile family are
(PROM), Erasable mask ROM, Programmable ROM
.Programmable ROM
(EPROM) and
Programmable ROM (EEROM). Electrically Erasable
A
mask ROM are hardwired
during fabrication
can be programmed
once after
and cannot be changed. A PROM
fabrication by
special high programming blowing on-chip
voltage. fuses witn
Designing Memory andArray
Structures
PROM can be modified only once
11.3
by a user. The user a
énters thhe desired contents using a buys blank PROM and
PROM programmer.
4
Inside the
PROM chip there are
small fuses which are
burnt open during
programming. It can be programmed
only once and not
is erasable.
An EPROM
isprogrammed by storing charge on a floating gate.
It can be erased
byexposure to ultraviolet (U) light for several minutes toknock the charge
off
the gate and it can be reprogrammable.

A EEPROM are similar to EPROM, but can beerased in microseconds

with on
chip circuitry. Flash memories are a varjant of EEPROM that can erases
the
entire blocks rather than individual bits.

Some mnemory types restrict the order of access, which results in either faster
access times, smaller area and have a memory with a special functionality.
Examples of such are the serial memories: the FIFO (first-in ftrst-out), LIFO

(last-in frst-out), and the shift register.

A Contents - Addressable Memories (CAM)

represents non-random aCcess memories. It is also known as
CAM class of
Associativememory, in which the user supplies data word and associative

memory searches its entirememory.

returns the list of addresses where that data word
f the data word is found, it
Was located.

ARCHITECTURES AND BUILDING BLOCKS

2 MEMORY

Memory
11.2.1 Architectures For N- word is
implemented, then N-word memorywhere each word
When Nx M memory is
approach is to stack the
arranged using the most intuitive
M
bits wide are 11.2(a).
words in a linear fashion, as shown in Fig
subsequent memory
 VLSI and Chip Design
11,4|

o By using a one word is selected at a time either for reading

select bit (S, to S).
memory that is, only one
(or) writing. Assume that this module is a single -port
signal S, can be HIGH at any time.
M bits ih M bitsitj

So
So Word 0
Word 0
S Word 1 Ao Word 1

Storage
words S Word 2 Storage Decoder Word 2 cell
cell

SN-2
Word N-2
AK Word N-2
SN-1
Word N-1 Word N-1
K= log2N

Input-Output Input-Output
(M bits) (M bits)
(a) Intuitive architecture for (b)Decoder reduces the nunber of
Nx Mmemory address bits

Fig 11.2 Architectures for N-word memory

Each storage cellis D flip-flop and the select
signal is used to activate (clock) the
cell. This approach is actually simple
and can works welI for very small
memories.
Consider a large memory with an
assumption of 1Mword unit. In
implement this structure, we need
order to
about 1 million select signals.
are normally provided But these signals
from off-chip (or) from another part
leads to wiring (or) packaging of the chip. This may
problens.
A decoder is inserted
in order to reduce the number
(Fig 11.2 (b)). A memory of select signal
word is selected by providing a
address.word (Ao to AK-). binary encoded
Designing Memory and. Array Structures
11.5|
decoder can translate
The this address into N = 2
select lines, only one of which
at a time. For example,
is active case of
in 3 to &
decoder, if 3 inputs are given to
decoder,then we can get 8 select signals.

Advantages

This approach rèduces the nunber of external

address lines from l million to
0doga
20), which virtually eliminates the wiring and packaging problems.
.The decoder is typically designed so that its dimensions are matched to the size
of the storage cell and the connections between the two are in particular S?
signals in Fig 11.2 (b).
# By performing the pitch matching between decoder and memory core, the S

wires can be very short, and no large routing channel is required.

11.2.2 Array- Structured Menmory

B Drawbacks
square, then the design is
If the basic storage cell size is approximately
storage cells to the
extremely slow. The vertical wires connecting the
înput/outputs becomes excessively long.
In order to address the above problem,
the vertical and horizontal dimensions of
memory arrays are in the same order of
magnitude; thus, the aspect ratio
words are stored in a single row and are selected
approaches unity. Multiple
simultaneously.
correct word to the input/outputterminals, an extra piece of circuitry
* To route the as shown in Fig 11.3.
as column decoder circuit is needed
called
into a column address (Ao to Ax-1) and a row
The address word is partitioned
row address enables one row of the memory for R/W.
uadress (Ar to Ai-), The from the selected
row.
picks one particular word
Wile the column address
Word Line and Bit Line
(enable) a single row of cells
is
Ihe horizontal select line
which is used to select
connects the cells in a single column to the
that
called as word line The wire
line.
"putoutput circuitry is said to be bit
 VLSI and Chip Design
11.6|
memnory core.
The area of large memory modules is dominated by the size of the
So, it is crucial to keep the size of the basic storage cell
as small as possible.

Sense amplifiers are used for the amplification of

an internal swing to a full rail

to-rail amplitude. This architecture works well for memories upto a

range of

64 Kbits to 256 Kbits.

Bit line
DecoderA
Storage cell

AK
--
AK+1 -- Word line

Row

A-1

M.2K

Sensearmpliiers/Drivers Amplify Swing to

rail-to-rail amplitude

Ao
Columndecoder Selects appropriate
AK-1
Word

Input-Output
(M bits)

Fig l1.3 Array-structured memory organization

3 Drawbacks
Large memories suffer from a
serious speed degradation as the length,
capacitance, and resistance the
of word and bit lines becomes excessively large.
11.2.3 Hierarchical Memory Architecture
To overcome the above drawback,
the memory is partitioned into P smaller
blocks. The composition each of
of the individual blocks is identical as Fig 11.3
and one extra dimension to the address space
is added.
Designing Memory and Array Structures
11.7
A
Word is selected on the basis of
# the row and column addresses that are
broadcast to all the blocks. An extra address word
called the block address, can
alects one of theP blocks to be read (or)
written. The block selector enables a
a
single memory block at time.

Block 0 Block i

Block P-1
Row
address

Column
address
Block
address

Global data bus

Control. Block selector Global
circuitry amplifier/driver

Fig l1.4 Hierarclhical memory architecture

M Advantages

This approach has the following advantages:

() Faster access times.

the addressed block
1
() The block address can be used to activate only
sense amplifiers and the
Nonactive blocks are in power-saving mode with
power saving,
row and column decoders disabled. As result of desirable

11.2.4 Contents Addressable Memory (CAM) Architecture

memory architecture, which supports three
Fig 115 shows a 512-word CAM
Inodes of operation: read, write and match.
access and manipulate data in the CAM array in.
1 he read and writemodes allow
same way as in an ordinary memory. The match mode
is unique to associate
e
memories.
|11.8| VLSI and Chip Design

The comparand block is filled with the data pattern to match, and the mask word
indicates which bits are significant.

Buffers Data (64 bits)

/O
Commands

Comparand

Mask

Decoder
Bits Encoder

Validity

R/W Address (9 bits) CAM Array

Control Logic Address
29words x 64 bits Priority

29

Fig l1.5 Architecture of 512-word contents-addressable memory

For example, to find all the words in the CAM array which have the pattern
Ox123 in MSB. Then, comparand is filled with 0x12300000 and the mask with

0xFFFO0000.

rows of the CAM array then simultaneously compare

All512
the 12 MSBs of the
comparand with the data contained in that row. Every row
that matches the
pattern is passed to the validity block. Only the
valid rows that matches are
passed to the priority encoder.
In the event that two (or) more rows match the pattern,
the address of the row in
the CAM array is used to break the tie. To do
this, the priority encoder considers
all 512 match lines from the CAM array, select
the one with the highest address,
and encodes it in binary.
Since there are 512 rows in the CAM array,
9 bits are required to indicate
the
highest row that matched.
Dasigning Memory and, Array Structures
11.9
Finally, a component of
memory
design are input/output
Here, we will discuss
interface and control
circuitry. about Input/output
interface of DRAM and
SRAM memories andtheir impact on memory
control.

DRAM Timing
H

DRAM designers have opted for a multiplexed

addressing scheme. In this
model, the lower and upper halves of the address
words are presented
sequentially on a single address bus.

This approach reduces the number of package pins and has survived through
the subsequent memory generations.

Address
Row Address ColumnAddress
bus

RAS

CAS

RAS-CAS timing

Fig 11.6 DRAM timing

volumes. Lowering the pin count

DRAMs are generally produced in higher
expense of performance.
reduces the cost and size at the
by raising a number of strobe
The presence of a new address word is asserted
Signals which is shown in Fig 11.6.
part of the
RAS Row-Access Strobe) signal asserts that the MSB
Raising the can.
on address bus, and that the word-decoding process
address is present the
be initiated.
next, and the CAS (Column-Access
The LSB nart of the address is applied
Strobe) signal is asserted.
11.10 VLSI and Chip Design

To ensure the correct memory operation, a careful timing of the RAS-CAS

interval is necessary.
The RAS and CAS signals act as clock inputs to the memory module, and are
used to synchronize memory events, such as decoding, memory core access,
and sensing.

(2) SRAM Timing

The SRAM designers have chosen a self- timed approach which is shown in
Fig 11.7. The complete address word is presented at once, and circuitry is
provided to automatically detect any transitions on that bus.

Address
AddresS
Bus

Address transition
initiates memory operation

Fig 11.7 SRAM tining

No external timing signals are needed. All internal timing events, such as the
enabling of the decoders and sense amplifiers, are derived from the internally
generated transition signal.
This approach has an advantage that the cycle time of the SRAM is close or
equal to its access time.

11.3 MEMORY CORE

When designing the large memories, the major issue is to keep the size of the cell
as small as possible.

11.3.1 Read Only Memory (ROM)

Read-Only Memories are non-volatile. It will retain their contents even when the
power is removed. Mask-programmed ROMs use one transistor per bit. The
presence (or) absence was determined as either 1 (or) 0.
Designing' Memory and Array Structures 11.11
This memory processor mainly used in washing machines, calculators, and game
machines. The contents of a ROM celI are permanently fixed which considerably
simplifies its design.

ROM isrepresented with dot diagram. The dots indicate 1's in ROM. Fig 11.8
shows 4- word x 6 -bit ROM with an example.
Word
:010101
0

Word 1 :
011001
Word 2
:100101
Word
:101010
3

Fig 11.8Anexample of ROM storage

BL
BL
BL
op
WL
WL WL
1

BL BL |BL

WL WL WL

GND

(b) MOS ROM 1 (c) MOS ROM 2

(a) Diode ROM
0 and logic l in ROM cells
Pig l1.9 Different approaches to inplement logic
11.12| VLSI and Chip Design

.The ROM cell is designed in such a way that logic 0 (or) logic 1 is presented to
the bit line upon activation of its word line. Fig 11.9 shows several ways to
accomplish this.

(1) Diode ROM

(i) Logic - 0

Consider the diode-based ROM, which is the simplest cell and shown in
Fig 11.9(a). Assume that the bit line (BL) is resistively clamped to ground that
is, BL ispulled low through the resistor connected to ground and lacking any
other excitations or inputs. This is for logic 0 and no physical connection
between the word line WL and BL exists.
(i) Logic- 1
When a high voltage Vw is applied to the word line
of the 1 cell, the diode is
enabled, and the word line pulled up to
is Vw,- Vpion) , resulting in a 1 on the
bit line.
Simply, the presence of a diode between bit line and word line is considered
as logic
1' and its absence is considered as logic
0.
E Disadvantages
The disadvantages of diode
based ROM cell are,
) It does not isolate the bit
linefrom the word line.
(i) Allcurrents required to
charge the bit line capacitance,
large memories. So, is quite high jor
it is suitable only for smnall
memories.
(2) MOSROM 1
To overcome the
above drawbacks
approach is diode of diode based ROM
replaced by the cell, a better
transistor, whose gate-source connection of a NMOS
drain is onnected
to the supply
Ay
Fig 11.9(b). voltage and it is
shown 1
Designing. Memory and Array Structures
The operation is identical |11.13
to that ofthe diode
All the output driving cell with one major
current is difference:
provided by
"The word-line driver the MOS transistor in
is only responsible the cell.
word-line capacitance. for charging and discharging
the
An alternative
implementation is offered
by the MOScell and
Fig 11.9 (c). it is shown in.
In ROM, the supply
rail must be distributed
throughout the array.
of a 4x4 array is shown An example
in Fig 11.10.Here, the supply
sharing them between lines get reduced by
the neighboring cells.

BL (O]
BL [1] BL [2] BL [3]

WL [O]

VoD
WL [1]

WL (2]

VpD

WL [3]

Vbias

Pull - down loads

Fig l1.10 A 4 x4 OR ROM cell array

an
This requires mirroring of the odd cells around the horizontal axis,
cores of all styles.
approach that is extensively used in memory
 VLSI and Chip Design
11.14|

Memory: NOR ROM

(3) Programming the ROM VpD

Pull- up devices

WL [O]

GND

WL []

WL [2]

GND

WL [3]

BL [O] BL [1) BL [2] BL [3]

Fig l1.11 A
4x4 MOS NOR ROM cell array
An NxMROM memory can be considered as a
combination of 'M NOR
gates with atmost N° inputs.
It is therefore called a NOR ROM
which is
shown in Fig 11.11.
To be operational,
thiscell requires the bit line to be resistively clamped to
supply voltage, or equivalently, the
the default value at the output must
to 1.
be equal

The 0 cell is realized by providing a

MOS device between bit
line and ground.
Applying a high voltage on the
word line turns on the device,
which inturn
pulls down the bit line to GND.

A PMOS load is used to pull up the devices.

If there is no attached NMOS is
enabled, then PMOS is used to pull up the bit lines.

Fig 11.12 shows a 4x4 ROM array based on a

NAND configuration, All the
transistors constituting a column are connected in series.
 origning. Memory and. Array Structures
11.15|
Vop

Pull- up devices
BL [0) BL[1] BL [2] BL (3)

WL [O]

WL (1]

WL [2]

WL [3)

Fig 11.12 A 4 x4 MOS NAND ROM

0 A basicproperty of a NAND gate is that all transistors in the pull-down chain

must be ON to produce low value. The word lines must be operated in
reverse-logic mode to make this memory function.
row by
O Allword lines are high by default with an exception of the selected
Setting it to 0. Transistors on nonselected
rows are thus turned ON.

O. The main adyantage of the NAND structure is that the basic cell only
consists
Of a and that no connection to any of the supply voltages is needed.
transistor
ThisS might reduce the cell size substantially.
11.3.2
Nonvolatile Read-Write (NVRM) Memories
The
architecture of the NVRW memories is virtually identical the RAM
to

Structure. an array of transistors placed on a word-

The memory core consists of

line/bit
line grid.
The memory or enabling some of those
is programmed by selectively disabling
memory, a modified transistor that permits its thresholdto
devices.
In a
NVRW
altered electrically is used.
11.16| VLSIand Chip Design

This modified transistor is retained indefinitely even when the supply voltage is
turned off. To reprogram the memory, the programmed values must be erased.
after which a new programming round can be started.
The programming of the memory is typically an order of magnitude slower than
the reading operation.

(1)Floating- Gate Transistor (FAMOS)

The floating-gate transistor is the device at the heart
of the majority of the
reprogrammable memories. Fig 11.13 shows the FAMOS,
that forms the core
of virtually every NVRW memory built today.
The structure is similar to a traditional MOS
device, except that
polysilicon strip is inserted between the gate and
extra n
channel, which is called as
floating gate.

Floating gate
Gate
Source
Drain

nt nt
Substrate S

(a) Device cross section

(b) Schematic symbol

Fig 11.13 Floating-gate transistor

The impact of inserting this extra gate
is to double the gate oxide thickness,
tos Which results in a reduced device transconductance as
well as an increased
threshold voltage.

A Programmable Threshold Voltage

a
Applying high voltage (above 10V) between the source and gate-drain
terminals creates a high electric field and causes an avalanche injection to
OCCur.
 Memory and Array Structures
Memor 11.17|
ng acquire sufficient energy to become "hot" and transyerse though
Elecirons
oxide.insulator, sothat they get trapped on thefloating gat.
the first
phenomenon can occUr with oxides as thick as 100-nm, which
makes it
This

relatively easy to fabricate the device

is
n reference to the programming mechanism, the floating gate transistor
often called aflbatinggate avalanche-injection MOS,(or
FAMOS).

gate can.effectively drops the voltage

The trapping of electrons on the floating
on that gate (Fig 11.14 a). This
process is selflimiting that is, the negative
over the
charge accumulated on the floating gate reduces an electrical field
accelerating. any more hot
oxide so that ultimately it becoms ncapable of
electrons.
may. inducenegative charge in place, and results
Removing the voltage leaves.
gate (Fig 11.14 b).
negative voltage on intrmediate
an
in a
5V
20 V

5V
-5V 0V -2.5 V
10V-->5V 20V

D
S
D
See D
(c) Programming results
Removing programming
() Avalanche injection 6) in higher VT
voltages leaves charge
trapped

transistor.
Programming the floating-gate
Fig l1.14 an effective increase in
0 Fromn a of view, this:
translates into
device point
a higher voltage is needed to
on the device,
threshold voltage: To' turn
induced negative charge (Fig 11.14 c). Typically,
Ovefcome the effect of the
7V.
theresulting threshold voltage ís around
0 The onto the floating gate will effectively shifts the I-V curves
charge injected
in Fig. 11.15. Applying
a word-line voltage Vw.
the transistor. as shown
or not ("1" state).
results
in eithercurrent flow(“0* state),
to
 11.18 VLSI and Chip Design

"0 state 1" state

ON"

AV

"OFF"
VWL
VGs

Fig l1.15 ILV curve shift caused by

hot-electron programming
Curve A is for the "0" state, while curve
B stands for the transistor
shift and representing with the VT
the "1" state. The value of the V
expressed as, shift can be

AV, = -AQFo)/C ...(1)

where,
CFc Capacitance between
extenal gate contact and
floating gate, and
AQFG Charge injected onto
the floating gate.
The floating gate is surrounded
by SiO2, which is an
trapped charge can excellent insulator. The
be stored for many years, even
removed, by creating a when the supply voltage
nonvolatile storage is
mechanism.
(2) Erasable Programmable
Read-Only Memory
(EPROM)
An EPROM is programmed
by storing charge on a
erased by exposure an floating gate. It can
to ultraviolet (UV) be
the charge off the gate light for several minutes
and it can be reprogrammable. to knock
 Memoryand Array Structures
Dsigning 11.19|
Electrically Erasable Programmable Read-Only Memory (EEPROM or E'PROM)

memory must be removed from the

o In EPROM, board and placed in an
EPROM programmer for programming.

The EEPROM approach avoids this labor-intensive and annoying procedure

by using another mechanism to inject or remove charges from a floating gate,
called tunneling.

A modified floating-gate device called the FLOTOX (loating-gate tunneling

Oxide) transistor is used as a programmable device that supports an electrical

erasure procedure.

The cross section of the FLOTOX structure is shown in Fig 11.16(a). It

resembles the FAMOS device, except that a portion of the dielectric which is
used for separating the floatinggate from the channel and drain is reduced in
thickness to about 10nm or less.

0 When a voltage of approximately 10V is applied over the thin insulator,

a mechanism called
electrons travel to and from the floating gate through
Fowler - Nordheim tunneling. The -V characteristic of the
tunneling

junction is plotted in Fig 11.16 (b).

Floating gate Gate I

Drain
Source

2030nm -10V VGD

10 V
nt
nt Substrate

10nm
(b) Fowler-Nordheim
(a) FLOTOX transistor LVcharacteristic

programmable by using
Fig l1.16 FLOTOX transistor,
Fowler-Nordheim tunneling
|11.20 VLSI and Chip Design

ØAdvantage
The main advantage of this EEPROM programming approach, it is reversible
that is, erasing is simply achieved by reversing the voltage applied during the
writing process.

(4) Flash Electrically Erasable Programmable Read-Only

Memory (Flash)

Definition

Flash EEPROM isa combination of the EPROM

and EEPROM approaches.
Flash combines the density of the EPROM with the versatility
of the EEPROM
structures, with the cost and functionality
ranging somewhere between two.the
Most Flash EEPROM devices uses an avalanche
hot-electron -injection
approach to program the devices. Erasure is performed using Fowler
Nordheim tunneling, as for EEPROM cells.
Control gate

Floating gate

Erasure Thin tunneling oxide

nt source nt drain
Programming
p-substrate

Fig ll.17 ETOX device as used in Flash EEPROM memnories

Fig 11.17 shows the ETOX Flash cell introduced by Intel, which
resembles a
FAMOS gate, except that a very thin tunneling gate oxide is utilized (10 nm).

The different areas of the gate oxide are used for programming and erasure.
Programming is perforimed by applying a high voltage (12V) on gate and
drain terminals for a grounded source, while erasure occurs with the gate
grounded and the source at 12V.
 Designing. Memory and Array Structures
11.21|

11.3.3Read-Write (NVRWM) Memories

Providing a memory cell with
roughly equal read and write performance requires
a more complex cell structure.

The contents of the ROM and NVRWM memories are integrated in the cell
topology or programmed into the device
characteristics, storage in RAM
memories is based on either positive
feedback or the capacitive charge.
141 Static Random-Access Memory (SRAM)

a Definition of SRAM
SRAM means Static Random Access Memory. Random access means that
locations in the memory can be read (or) written from in any order, regardless of

the memory location that was last accessed.

SRAM uses a memory cell with an internal feedback which retains its value as
long as the power is applied.

A Properties of SRAM
The attractive properties of SRAM are
High density (high bits per area) than lip-flops.

(i) Compatible with standard CMOS processes.

(ii) Faster than DRAM.

(iv) Ease of use - n0 refresh is necessary.
SRAM cellcan be able to do the following three processes as long as the
A

power is applied.

) Read when the data has been requested.

(ii) Write - when updating the data.
(ii) Hold (or) standby-when the circuit is idle.
 VLSI and Chip Design
122
as small as possible to achieve the high
The SRAM cell should be sized
memory densities. Reliable operation of the cell, however, imposes some
sizing constraints.

a) Basic 6T SRAM Cell

Each bit in an SRAM is stored on four transistors that forms twO cross
coupled inverters. This storage cell has two stable states which are used to
denote 0 and 1.
Two additional access transistors serve to control the access to a storage cell
during the read and write operations. It thus typically takes six transistors to
store one memory bit. The basic SRAM cell uses six transistors
in the
as
configuration shown in the Fig 11.18.
All are CMOS transistor. Data is
stored in the latch made by the pair of
inverters ånd it is accessed by the NMOS transistors on
the left and right of
the cell.

WL

VD
M2 M4

Mg
M5

M3

BL BL

Fig 11.18 Six-transistor CMOS SRAM cell

Access to the cell is_enabled by the word line (WL),
which replaces the clock
and controls the two pass transistors Ms and M6, shared
between the read and
write operation.
) WL = 0, hold operation,
(ii) WL= 1, read (or) write operation.
Qrtgming Memory and Array Structures

11.23|
o) Read Operation
The read cycle is started by asserting
the word line (WL), which
the pass transistors Ms and M6 enables both
after the initial word-line
delay.
uring the correct read operation,
the values stored in O and Q are
transferred
tothe bit lines by leaving BL at its precharge
value and by discharging BL
through M,-Ms.

The difference between BL and BL builds up that the sense

amplifier is
activated to accelerate the reading process.

WL

Vpo

BL Ma
BL
Q=0 Me
Ms
Q=1

M1 VoD
VoD VpD

Cbit
Cbit

and Vprecharge
=
Vop)
V

(Q=1

of CMOSSRAM cell during read operation

Fig 11.19 Simplified model
) Write Operation
M and M4 stay at VpD and
During
this write operation, the gate of transistors
GND, respectively.
cell (or
Q =
1). A 0 is written in the cell by
Assume that a 1 is stored in the
a
which is identical for applying a reset pulse to
Setting BL to and BL 1 tó 0,
causes flip-flop to change state if the devices are sized
DR latch. This the
properly.
 11.24| VLSI and Chip Design

WL

Vop
M4
Q=0
M5

Q=1
M1
VoD
BL= 1
BL = 0

Fig l1.20 Simplified model of CMOS SRAM

cell during write operation
(d) SRAM Active Power Reduction

(i) Low voltage swing

To obtain a fast read, the voltage

swing on the bit line is made as
possible, typically between. 0.1 V small as
and 0.3 V. The resulting signal
transmitted to the sense amplifier for is then
the process of restoration.
(iü) Turning off unused memory blocks

Memory functions such as caches

do not fully use the available capacity
of the for most
time. Disconnecting unused blocks
from the supply rails using high
threshold switches may reduces their leakage to a very
low values,
(iii) Increasing the thresholds
by using body biasing, either at process
time (or) at run
time is an essential in low voltage operation mode.
(iv) Inserting extra low-threshold switch
(resistance) in the leakage path may reduce
the leakage current, which is used to maintain the state
of the memory.
Designing Memory and Array Structures 11.25

VpD

low-threshold transistor
sleep

VoD, int

SRAM SRAM SRAM

cell cell cell

Vss, int
sleep

Fig l1.21I Inserting of low-threshold transistor

(v) Lowering the supplyvoltage

The leakage function is a strong function of supply voltage Vpp. By reducing

the leakage, during the standby mode is mainly to lower the supply rails to a
value that keeps the leakage within the bounds, while ensuring data retention.
in a
A supply voltage as low as 100mV is sufficient to maintain the retention
standard 0.13 um CMOS process.
VoD VDDL

sleep p4
VDD, int

SRAM SRAM SRAM

cell cell cell

Fig 11.22 Lowering the supply oltage

11.26 VLSI and Chip Design

(2) Dynamic Random-Access Memory (DRAM)

Definition

Dynamic` RAM is a type of RAM that holds its data and must be constantly
refreshed otherwise; it will lose all its contents.
DRAM stores their contents as charge on a capacitor rather than in a feedback
loop. Thus, the basic cell is substantially smaller than SRAM. DRAMS are built in
a specialized processes optimized fordense capacitor structures.

(a) Three- Transistor (3T)- DRAM,Cell

BL1 BL2
wWL

RWL WWL

RWL
M

X
M BL1 VDD
Vop-V

BL2 Vpp- V

Figl1.23 Three-transistor (3T) dynamic memory

cell
Fig 11.23 shows three-transistor dynamic memory
cell. The cell is written by
placing the appropriate data value on BL1 and asserting
the Write Word Line
(WWL). The data is retained as charge on
the capacitance Cs once WWL is
lowered.

When reading the cell, the Read-Vord Line (RWL)

is raised. The storage
transistor M, is either ON (or) OFF dependingupon the stored
value.
The bit line BL2 is precharged to either VDD
(or) Vpp -VT. The series
connection of M, and M3 pulls BL2 LOW when a 1 is stored and it remains
HIGH in an opposite case.
Digning Memory and. Array Structures
|11.27|
Properties
Attractive properties ofthe 3T DRAM Cell are,
A. In DRAM, n0 constraints exists on
the device ratios. The choice
sizes is solely based on of device
theperformance and the reliability
considerations.
G) Reading the 3T contents is nondestructive
that is the data value stored in
the cell is not affected by a read.

(iü) No special process steps are needed. This property

makes the 3T cell
attractive for an embedded memory applications.
(b) One- Transistor (1T) Dynamic RAM Cell
Toreducethe cell complexity, one-transistor DRAM cell (1T) are used in the
commercial memory design. A schematic diagram of 1T-DRAM shown in
is
Fig 11.24.

BL
WL
1
Write Read 1

WL
M

C X
GND
VoD -V
VoD
BL
Vpy'2 isensing Vop2
CeL

i sbo Fig l1.24 One- transistor DRAM.

During a write cycle, the data value is placed on the bit line (BL), and the
Word line (WL)is raised. Depending on the data value, the cell capacitance is
either chargedI(or) discharged. i
 VLSI and Chip Design
11.28|

Before a read operation is performed, the bit line is precharged to a voltage

VPRE. When asserting the word line, a charge redistribution takes place

between the bit line and storage capacitance.

This results in a voltage change on the bit line, the direction of which
determines the value of the data stored. The magnitude of the voltage swing is
given as,
AV= VBI- VpRE
Cg . (2)
(VgIT -VpRE)
Cgt CpL

where, CBL, is the bit line capacitance.

VBL is the potential of the bit line after the charge redistribution.
VBT is the initial voltage over the cell capacitance Cs.

As the cell capacitance is normally one (or) two orders of magnitude smaller
than the bit line capacitance, this voltage change is very small, typically
around
250 mV for state-of-the art memories.

The ratio Cç/(C + CBL) is called the charge - transfer ratio and ranges
.between 1% and 10%.

Differences
The major differences between 1T and 3T, as well as other, DRAM cells are,
) A 1T DRAM requires the presence of a sense amplifier for each bit line
to be functional. This is a result of the clharge -redistribution based
readout. A sense amplifier is only needed to speed up the readout, not for
functionality considerations.
DRAM memory cells are single ended in contrast to the SRAM cells,
which presents both the data value and its complement on the bit lines.
This complicates the design of the sense amplifier.
 Memory and Array Structures
11.29
The readout of
the lT
DRAM ccll is destructive.
(ü) This means that the
nount of
charge stored in the cell is modified
during the read
operation.
Afer a successtul read operation, the
originalvalue must be restored.
Unlike the 3T ccll that relies on
(m) charge storage on a gate capacitance, the
1T cell requires the presence
of an extra capacitance that must be
explicitly included in the design.
Fitting that large ofa capacitance as small as an area as
possible is one of
the key challenges in DRAM designs.

When writing a l into the cell, a

threshold voltage is lost, which reduces
the available charge. This charge loss can be circumvented by
bootstrapping the word lines toa value higher than VDD.

1.3.4 Contents-Addressable or Associative memory (CAM)

Definition

A CAM is a special ype of memory device that stores data, but also has the
ability to compare all the stored data in parallel with an incoming data in an
efficient manner.
-Transistor (9T) CAM cell

Bit Bit Bit

Bit
Word Bit Bit

M4 M5 H
CAM CAM

s
Word
int
CAM CAM
M

Match

Wired-NOR Match Line

Fig 11.25 9- transistor CAM cell

 VLSI and Chip Design
|11.30

a implementation of a CAM array using the 9

o Fig 11.25 shows possible
storage cell (M4- M9) with
transistors. The cell combines a traditional 6T RAM
M3).
additional circuitry toperform a 1-bit digital comparison (M1-

When the cell is to be written, complementary data is forced onto the bit lines,
while the word line is enabled as in a standard SRAM cell.

In the compare mode, the stored data (S and its complement S) are compared to

the incoming data, which is provided on the complementary bit lines (Bit and

Bit).
The Match line is tied to all the CAM cells in a given row, and is initially
precharged to VpD. If S and Bit matches, an internal node int is discharged, and
MIis turned off, by keeping the match line HIGH.

If the stored and incoming bit are different, int is charged to Vpp - V, causing
the match line to discharge.

For example, if Bit = VDp and S =0, int charges up through the M3. It is easily
verified that the circuit performs nothing other than an XNOR function (or
comparator).
The pul-down device in the comparator is connected to each of the CAM cells in
a row in a
wired-OR fashion. That is, even if only one of the bits in a given row
mismatches, the match line is pulled LOW.
For a memory with N rows, most rows (mismatches) will be pulled low in a
given cycle.

Drawbacks of CAM
The drawbacks of CAM are,
() CAMs are typically not very power efficient.

(i) It is possibleto re-arrange the logicsuch that only the match line switches.
causes a significant degradation in performance.
 gming Memory and Array Structures

M
11.31|
Usage ofAAssociate Memory
in Cache Applications

Decoder

Logic

CAM
Address
ARRAY SRAM
Hit ARRAY

Input Drivers
Sense Amps / Input Drivers

Address Tag Hit RW Data

Fig 11.26
Application of CAM cell: High -performance on-chip
cache memory

4 MEMORY PERIPHERAL CIRCUITRY

l4.1 The Address
Decoders
Whenever a
memory allows for random address-based access, an address
decoders
must be needed at that time.
The design
of these decoders has a
substantial impact on both the speed and
Power onsunptión
of the memory.
Two
types of decoders are,
() Row decoders -It is to enable one memory row out of 2M

(ii)
Column - can be described as 2K
and block decoders It -input
multiplexers.
Where, M
and K are the widths of the respective fields in the address word.
|11.32 VLSI and Chip Design

(1) Row Decoders

A l-out of 2™ decoder is nothing less than a collection of 2M complex

M-input, logic gates. Considera 8-bit address decoder and each of the output
WL, is a logic function
of the 8 input address signals (A to A).
For example, the rows with addresses 0 and 127 are
enabled by the following
logic functions:

WLo = Ag A,A, Ag A, A A, Ag
A

WL127 = A, A, A,
A, A, A, Ag Ay
A, ... (1)
This function can be implemented
normally in two stages,
input NANDgate and an using a single 8
inverter. For a single-stage
transformed into a wide
implementation, it can be
NOR using Demorgan's
rules:
WL, =
At Aj + A, +
A, + A,tAt
At A

WLj27 =
At A, t A, + Az + A,+ As+
Açt Ay ... (2)
To implement this
logic function, a 8-input
can face the following NOR gate is needed per row
challenges: and it
() The layout
of the wide-NOR gate must
fit within the word-line
(i) Thelarge fan-in pitch.
of the gate has a negative
impact in its
performance.
(iii) The propagation
delay of the decoder
to both the read-and is important, as it
write-access times. adds directly
(iv) Finally, the power dissipation
of the decoder has to be kept
in check.
(2) Static Decoder Design
g Drawback
Implementing awide-NOR
functionin complementary CMOS
is impractical.
 Array, Structures
wgnting Memory and |11.33

One possible solution is to use a pseudo-NMOS design style, which allows for
implementation of wide NORS.
anefficient
an

Splitting a complexX gate into two or more logic layers most often produces
both a faster and a cheaper implementation.

Segments of are a
first logic layer called the
the address decoded in
word
nredecoder. A second layer of the logic gates then produces the final
line signals.

Predecoder Word driver

15
o
Word line
Address
input
(WL)

of an eight-bit decoder
Fig 11.27 Logic path
decoder and the expression for WLo can be
0 Consider a 8-input NAND
way:
regrouped in the following

As A, A,
WL, = Ag A, A, A, A,

+ (AtA,) ...(3)
(AgtA,) + (A,tA,) + (AtA,)
that
address is partitioned into sections of 2 bits
case, the
ror this particular
can be decoded in advance.
NAND gates to
combined using 4-input
0 The resulting signals
are then in
array word-line signals. This is illustrated
Produce the fully decoded
of
Fig 11.28.
 11.34 VLSI and Chip Design

b- WLy

WLo

A, A|ApA,AA |AzAg|AAs |AzAs| AgAs

A1 Ao Ag A1 Ag A2 Ag Ag

Fig 11.28 A NAND decoder using 2-input

predecoders
Advantages
Theuse of a predecoder can be advantageous
in many ways:
(i) It reduces the number of transistors equired.
(ii) As the number
of inputs
to the NAND gates is
halved, the
delay is reduced by, approximately a propagation
factor of 4. That is, squared
dependency between delay andfan-in.
(3) Column and Block Decoders

oColumn decoders should match the bit line pitch of the memory array.
functionality of a column and The
block decoder is best described
multiplexer, where K stands for as'á 2-input
the size of the address word.
j g
For read-write arrays, these
multiplexers can be either separate or
between read and write operations. shared

During the read operation, they have

toprovide the discharge path from the
pre charged bit lines to the sense
amplifier.
Deigning. Memory and. Array Structures

When performing aa write

11.35
operation a memory
in array, they have
drive the bit line low to write a 0
inthe memory cell.
to be able to

BLo BL
BL2 BL3

Ao So

S1

S2

A1
S3

Fig l1.29 Four-input pass-ransistor based column decoder

using aNOR predecoder
o The schematic of a 4-to-1 column decoder, using only NMOS transistors is
shown in Fig 11.29. The complementary transmission gates must be used
when these multiplexers are shared between the read and write operations
which is to be provide a full swing in both directions.

Only a single pass transistor is inserted in the signal path, which introduces
only a minimal extra resistance.

0 The column decoding is one of the last actions to be performed in the read

Sequence, so that the predecoding can be executed in parallel with other

as
Operations, such as the memory access and sensing, and can be performed
SOon as the column address is available.

E Drawbacks
The drawbacks of column decodes are,
(i) This structure needs a large transistor count. (K + 1) 2k+ 2* devices are
needed for a 2*-input decoder. For example, a 1024 tol column decoder
requires 12,288 transistors.
 VLSI and Chip Design
11.36

(iü) The transient response at node D is proportional to the number of inpute

of the multiplexer.

(a) Tree -Based Column Decoder

A more efficient implementation is offered by a tree decoder that uses a binary

reduction scheme, as shown in Fig 11.30.

BLo BL4 BL2 BL3

Ap

A1

Ag

A3

Fig 11.30 A 4-to-I tree based

column decoder
Here, no predecoder
is required and the
number of devices is
reduced as per the following drastically
equation fora2^
-input decoder:
Ngye =
2+2k-+...... +4+2 = 2x (2^-1)
(4)
Using this equation
for a 1024 to
1 decoder
devices and the reduction requires only about
2046 active
is by a factor of 6.
transistor count Thus, this can reduces
and the propagation both the
delay.
11.4.2 Sense Amplifiers
Sense amplifiers
plays a major role
in the functionality,
reliability the of memory circuits. performance and
 Arnyruchures
Acons 11.37

kprnms the followingfunctions:

Amplification

batin memorystructures such as the 1T

DRAM,amplification
i proer fncionality since the typical circuit swing isrequired
is limited to 100
-livols
.a othet memoies, it allows resolving data with small bit-line swings that
eshles the reduced power dissipation and delay.
Delay Reduction

The amplifier compensates for the restricted fan-out driving capability of the
memory cell by accelerating the bit line transition.

Power Reduction

Reducing the signal swing on the bit lines can eliminate substantial part of
a

discharging the bit lines.

the power dissipation related to both charging and

Sianal Restoration
are intrinsically linked in 1T DRAMS.
Because the read and refresh functions
range after sensing.
necessary to drive the bit lines to the full signal
Iis
4 Diferential Voltage Sensing Amplifiers
bit-line
small-signal differential inputs (i.e., the
takes
A differential amplifier single -ended output.
to a large -signal
Foltages), and amplifies them equally
an amplifier is rejecting noise that is
rejection in
Ihe common- mode especially attractive in memories
where the
This is
injected toboth the inputs. die to die and even for
different
signal varies from
€xact value of the bit line
locations on a single die.
 VLSI and Chip Design
11.38

The effectiveness of a differential amplifier is characterized by its ability to

reject the common noise and amplify the true difference between the signals

The signals common to both inputs are suppressed at the output of the
amplifier by a ratio called the Common- Mode Rejection Ratio (CMRR).

o The spikes on the power supply are suppressed by a ratio called the Power
Supply Rejection Ratio (PSRR).

The differential approach is only directly applicable to SRAM memories,

because it only offers a true differential output. Fig 11.31 shows the most
basic differential sense amplifier.

M3 M4

Out

Bit M1 M Bit

SE Ms

Fig 11.3I Basic differential sense amplifier

circuit
Here, the amplification is accomplished
with a single stage, based on the
current mirroring concept. The
input signals (bit and bit ) are heavily loaded
and be driven by the SRAM memory cell.

The swing on those lines is small as

the small memory cell drives a larg
capacitive load. The inputs are
are fed to the differential
input devices (M1
M.). and transistors M3 and M4 acts as an ad
active current mirror load.
 Davigning. Memory and Array Structures 11.39

The amplifier is conditioned by the

amplifier enable signal, SE. Initially,
be inputs are preCharged and was equalized to a common value, while SE 1S

LOW and it disables the sensing circuit.

Once the read operation is initiated, one of the bit lines drops. SE is enabled
when a sufficient differential signal has been
established, and the amplifier
evaluates.

The gain of such the differential -to-single ended amplifier is

expressed as,

Asense -8mi (roz llr) ..(6)

where, gm is the transconductance of the input transistors.

ro is the small-signal device resistance of the transistor.

la) DifferentialTwo- Stage Sensing Approach

Fig 11.32 shows a fully differential two-stage sensing approach along with the

SRAM bit column structure. The bit lines are connected to the inputs x and x
of the two-stage differential amplifier.
A read cycle proceeds as follows:

() In the first step, the bit lines are precharged toVDp by pulling PC LOW.
Simultaneously, the EQ-PMOS transistor (Equalization transistor) is
are identical.
turned ON, ensuring that the initial voltages on both bit lines
This operation is called as an equalization which is necessary to prevent
the sense amplifier from making erroneous exxcursions when turned ON.
In practice, every differential signal in the
memory is equalized before

performing a read.
(1) The read operation is started by disabling the precharge and equalization
devices and enabling one of the word lines. One of the bit lines is pulled
lowby the selected memory cell. A grounded PMOS load is placed in
parallel with the precharge transistor that limits the bit line swing and
Speeding up the next precharge cycle.
 VISI and Chip Design
el
up (typically around 0.5 V), the se
(iii) Once a sufficient signal is built
on tha
amplifier is turned ON by raising SE. The differential input signal
bit lines is amplified by the two stage amplifier and eventually a rail to :

rail outputis produced at the output of the inverter.

VoD
PC

Vop Vop
BL BL
EQ

WLi

SE -
SE

SRAM cell i
ASE
Diff.
VoD
X Sense x
Amp
- Output

Output
SE

(a) SRAM sensing scheme

(b) Two-stage differential amplifier
Fig 11.32 Differential sensing as applied
to a SRAM memory column
The two-stage sense amplifier circuit
is shown Fig 11.32 (b). These
use PMOS loads cirCus
and NMOS input devices,
The dual configurations Wu
PMOS input devices and
NMOS loads are also regularly
upon the biasing conditions. used, dependms

By
pulsing the SE control
signal to be active for periods, then
the static power short evaluation
in the amplifier can be reduced.
single sense amplifier shared
A

is between
multiple columns by inserting the
column decoder pass
transistors between the
memory cells and an amplifier.
This results in both area
savings and power
reduction.
 Memory and. Array Structures
iening
-Coupled CMOS Inverter 11.41|
Cross Latch

Fig 11.33 shows a

cross-coupled CMOS
A inverter latch
sense amplifier. CMOS inverter which
is used as the
exhibits a high
transient region. gin when positioned in its
To act as the sense
amplifier, the flip-flop
hy equalizing is initialized in its metastable
the bit lines. A voltage difference point
is built over the bit lines
course of the
read process. in the
Once a large enough
voltage gap is created, the sense
raising SE. Depending upon amplifier is enabled by
the input, the cross-coupled pair traverses
of its stable operating points. to one
The transition is swift as a result
feedback. of the positive

EQ

BL
BL

VDD

SE

SE

Fig l1.33 Cross-coupled CMOS inverter latch

When the flip-flop sense amplifier is simple and fast, it has the property that
nputs and outputs are merged. So that a full rail-to-rail transition is enforoed
 VLSI and Chip Design
11.42

on the bit lines, which is exactly needed for a 1T DRAM." Therefore. tha
Cross-coupled cell is, almost universally used in DRAM designs.

11.4.3 Voltage References

Most of the memories require some form of on-chip voltage generation. The
operation of a sophisticated memory requires a number of voltage references and
supply levels, which includes the followings:

(O) Boosted -Word-line Voltage

In a conventional 1T DRAM cell which uses a NMOS pass transistor, the

maximum voltage level that can be written onto a cellequals Vpp - V, that
negatively impacts the reliability of the memory.

By raising he word-line voltage above VbD (more specifically to Vop + Vr.

then a full-scale signal can be written. This is called "boosted word-line"
approach which typically uses a charge pump to generate the elevated
voltages.

(ii) Half -VpD

DRAM bit lines. are precharged to VDp/2. This voltage nust be

generated on
chip.

(iii) Reduced Internal Supply

Most memory circuits can operate at a lower supply than an

external supply.
DRAM use internal voltage regulators to generate
the required voltages, while
being compliant with standard interface voltages,

(iv) Negative Substrate Bias

To control the threshold voltages within a memory
it is to apply negative
substrate biasing, augmented with a control loop. This
efective approach has
heen used for allrecent generation of DRAMmemories.
pustgning. Memory and Array Structures
11.43

Voltage Down Converters

Voltage down converters are used to create low internal
supplies that allows
ihe interface circuits to operate at higher
voltages.
Regulators serves toset a stable internal voltage while accepting a broad range
on an unregulated input voltages
in battery-operated systems.

VoD

Mdrive
VREF J Marive

VREF VDL

VoL
Voles

representation
Fig 11.34A voltage regulator and its equivalent
a voltage down converter. It is also
Fig l1.34 shows the basic structure of
on an operational amplifier.
called linear regulator as based
output driver transistor to drive the load of the
0 The circuit uses a large PMOS
to set an output voltage
memory circuit. This circuit uses negative feedback
VDL to the reference voltage.
operating
converter must offer a voltage that is immune to variations in
O The
as temperature changes can be compensated
conditions, Slow variations, such
by the feedback loop.
can unstable if improperly designed. The load current
This feedback circuit be
designed
load wildly over time, and the coverter must be
Can be drawn bythe
accommodate these wide variations.
O

14 Charge
Pumpsh techniques often needs voltage
sources
Word-line boosting and well biasing
current. A
charge pump
voltage, but do not draw much
that exceeds the supply
task.
is an ideal generator for this
 VLSI and Chip Design
11.44|

VpD 2VDD-V
VB

Mq VDp-VT
CLK 0V
Cpump

M
Vload

Cload Vioad

OV

Fig l1.35 simple charge pump and its signal wavefornms

Fig 11.35 shows a simple charge pump and its signal
waveforms. Transistors
MIand M2 are connected in
diode style.
Initially, assume that the clock CLK is
HIGH. During this phase, node A is at
GND and node B at Vpn -
V. The charge stored in the capacitor is then
given by,

Q Cpump
(VDD-V) .(6)
During the second phase,
CLK goes LOW and
raising node A to Vpp. Node B
rises in concert and
effectively shutting
off M1.
When B
is one threshold
above Vload, starts to conduct and.
M

transferred to Cload
During consecutive
charge is
deliver charge clock cycles,
Vload
ntil the maximum the pump continuous to
the output. voltage of 2
(Vpp- VT) is reached at
The amnount
of current
determined
that can be drawn
bythe capacitor's from the generator is primarily
size andthe clock
The efficiency frequency.
of the generator,
during every pump which measures
cycle, is between how much Current is wasted
30% and 50%.
 Memoryand Array Structures 11.45
iging
pumps are used for generators that draw little current. Á wide range of
Charge
ore complex charge pumps have been devised for larger the voltage ranges
efficiency.
and improved

Voltage Reference

acCurate and stable voltage reference is an important component of the

0 An
voltage down converter.

over power supply

The reference voltage is assumed to be relatively constant
and temperature variations,

X R1
M5
M1

VREF

R2
M

M4
M3

reference generator
Fig l1.36A simple V
0 reference generator.
The bottom devices (M, and M)
Fig 11.36 shows a VT

drain of and M

as a current mirror to force the same current through the

vS
the resistor
R.
0 By making and keeping the current small
enough, the
the device M large
can approximately equal to
V
and
urce-to-gate voltage for M; be made

itis expressed as,

 VLSI and Chip Design
11.46|

Vas, MI
2 IM1
n. (7)
| |= |Vr,I+
current of M.
The currents which are going through the resistor and the drain
both equals
|R and M, acts as a biasing transistor.

M and M experience the same gate-to-source voltage, then the drain current
of M
is mirrored to Ms. The reference voltage is expressed as,
R2 . (8)
VREF
|Vpl'R
(4) Drivers/ Buffers
A
major part of memory-periphery area is allocated to the drivers and it is in
particular to the address buffers and the /O drivers.

11.5 TWO MARKS QUESTIONS AND ANSWERS

1. List the categories of memory array. [NOVDEC-2020 & APR/IMAY-2021/
The main categories of memory array are,

() Random Access Memory.

(ii) Serial Access Memory.

(ii) Content Addressable Memory.

2. What is RAM?
Most of
memories belong to the random-access class, which means memory
Jocations can be read (or) written in a random order.
Random Áccess Memory
(RAM) is commony classified as Read-Only Memory (ROM)
and Read/Write
Memory (RWM).
3. Differentiate between volatile and nonvolatile memory.
more useful classification
nonvolatile memory.
A
of RAM is volatile and
Volatile memory can retains its data as applied, while
long as power is
1s
nonvolatile memory will hold data indefinitely.
 Memory andIArray Structures

11.47|
static and dynamic memory.
memories can further
volatile
The be divided into
static structures and i dynamic
structures, The static will retain
their data as long as
the supply voltage is-
retained, while dynamic need periodic
refreshing to compensate
for the chage
lsS Caused by the leakage.

What do yOu mean by EEROM?

Erasable Programmable ROM
An
(EPROM) is programmed by storing charge on
Aoating gate. It can be erased by exposure
toultraviolet (UV)light for several
ainutes to knock the charge
off the gate and it can be reprogrammable.
Define CAM.

Contents-Addressable Memories (CAM) represents class of non-random access

memories. It is also known as Associative memory, in
which the user supplies
data word and associative memory searches its entire memory.
If the data word isfound, it returns the list of addresses where that data word was
located.

What is meant by word line and bit line?

The horizontal select line which is used to select (enable) a single row of cells is
called as word line. The wire that connects the cells in a single column to the

hput/output circuitry is said to be bit line.

List the advantages of
hierarchical memory architecture.
Ihis approach has the following advantages
( Faster access times.

(u) -The block address can be used to activate

only the addressed block.
sense amplifiers and
Nonactive blocks are in power-saving mode with
power saving,
row and column decoders disabled. As result of desirable
9, Write
the disadvantages of diode based ROM cell.
The are,
disadvantages of diode based ROM cell

It does not isolate the bit line from

the word line.
9
 VLSI and Chip
11.48 Design

s
(ii) required to charge the bit lihe capacitance, is quite hich
All currents

large memories. So, it is suitable only for small memories.

10. How FAMOS s programmed?

In floating- gate transistor, applying a high voltage (above 10 V) between the
source and gate-drain terminals creates a high electric field and causes an

avalanche injection to occur.

Electrons acquire sufficient energy to becomne "hot" and transverse through the
first oxide insulator, so that they get trapped on the floating gate. This
phenomnenon can occur with oxides as thick as 100 nm, which makes it relatively
easy to fabricate the device.

In reference to the programming mechanism, the floating gate transistor is often

called a floating-gate avalanche-injection MOS (or FAMOS).
I1. Define flash EEPROM.
Flash EEPROM is a combination of the EPROM and EEPROM approaches. It
combines the density of the EPROM with the versatility of the EEPROM
structures, with the cost and functionality ranging somewhere between the two.
12. Define SRAM.

SRAM means Static Random Access Memory. Random access means that
locations in the memory can be read (or) written from in any order, regardless of
the memory location that was last accessed.
SRAM uses a memory cell with an internal feedback which retains its value as
long as the power is applied.
13. Listthe properties of
SRAM.

The attractive properties of SRAM are:

(i) High density (high bits per area) than flip-flops.

(i) Compatible with standard CMOS processes.

(iii) Faster than DRAM.

(iv) Ease of use - no refresh is necessary.
 Memory and. Array Structures
Joigming
11.49
WhatisDRAM?

RAM (DRAM)
Dynamic
is a type of RAM that holds its data and must be
constantly.refreshed. Otherwise, it will
lose all its contents.
DRAM stores their contents as charge on a
capacitor rather than in a feedback
Thus, the basic cell is substantially smaller
Joop. than SRAM. DRAMs are built
specialized processes optimized for dense capacitor structures.
in a
K Write the properties of 3T DRAM.

Atractive properties of the 3T DRAM Cell are.

) In DRAM, no constraints exists on the device ratios. The choice of
device sizes is solely based on, the performance and the reliability
considerations.
(ii) Reading the 3T contents is nondestructive that is the data value stored in
the cell is not affected by a read.
(iü) No special process steps are needed. This property makes the 3T cell

attractive for an embedded memory applications.

16. Draw a l- transistor Dynamic RAM cell. [APR/MAY-2019)
BL

WL

CeL=

11. List 3TDRAM over IDRAM.

the advantages and limitations
of
out
[NOVDEC -2018]
Advantages
of 3T DRAM3 sl
on the device ratios. The choice of
) In DRAM, no constraint exists
reliability
device sizes is solely. based on the performance and the
considerations.
 VLSI and Chip Design
11,50

(i) Reading the 3T contents are nondestructive that is the data value storod
in the cell is not affected by a read.
(iii) No special process steps are needed. This property makes the 3T cell
attractive for embedded memory applications.
Limitations of 3T DRAM over 1T DRAM
Toreduce the cellcomplexity of 3T DRAM, one-transistor DRAM cell
(1T) are used in the commercial memory design.

18. Write the major differences between 1 and 3T, as well as other, DRAM cels.
The major differences between 1T and 3T, as well as other, DRAM cellsare,

() A 1T DRAM requires the presence of a sense amplifier for each bit line
to be functional. This is a result of the charge -redistribution based
readout. A sense amplifier is only needed to speed up the readout, not
for functionality considerations.

DRAM memory cells are single ended in contrast to the SRAM cells,
which presents both the data value and its complement on the bit lines.
This complicates the design of the sense amplifier.
(ii) The readout of the 1T DRAM cell is destructive. This means that the
amount of charge stored in the cell is modified during the read
operation.

After a successful read operation, the original value must be restored.

(iiüi) Unlike the 3T cell that relies on charge storage on a gate capacitan
the 1T cell requires the presence of án extra capacitance that must be
explicitly included in the design.
Fitting that large of a
capacitance as small as in an area as possible is
one of the key challenges
in DRAM designs.
(iv) When writing a
l into the cell, a threshold voltage is lost, which reduces
by
the available charge. This charge loss can be circumvented
bootstrapping the word lines to a value higher
than Vpp
 Daigning. Memory and Array Structures 11.51

drawbacks of CAM.
B Litthe, are
The drawbacks of CAM
CAMs are typically not very power efficient.

(6) It is possible to re-arrange the logic such tht only the match line
switches, causes a significant degradation in performance.

Write the advantages of predecoder in static decoder design.

The use ofa predecoder can be advantageous in many ways
() It reduces the number of transistors required.

(i) As the number of inputs to the NAND gates is halved, the propagation
delay is reduced by approximately a factor of 4. That is, squared
dependency between delay and fan-in.
21. List the drawbacks of column decoder.
The drawbacks of column decodes are,
) This structure needs a large transistor count. (K+ 1)
2 + 2
devices are
needed for a 2K-input decoder. For example, a 1024 tol column decoder
requires 12,288 transistors.
(i) The transient response at node D is proportional to the number of inputs
of the multiplexer.
2. Mention the functions of senseamplifiers.

Sense amplifier performs the following functions:

() Amplification,

(i) Delay reduction,

(iii) Power reduction,
(iv) Signal restoration.

11.6 REVIEW
QUESTIONS

Write a note on memory classifications.

Lxplain the architectures of a memory chip with necessary iagrams.

 VLSI and Chip Design
|11.52

with neat
3. Discuss in detail about the Contents Addressable Memory (CAM)
sketch.

4. Write note on
() Read Only Memory(ROM)
(ii) Nonvolatile Read -Write (NVRM) memories.

S. Discuss in detail about the memory core with neat sketches.

6. Elucidate in detail the design of lowpower SRAM memory circuits.
NOVDEC -2019)
7. Discuss in detail about 3T DRAM and 1T DRAM cell with neat sketches.
8. Explain in detail about memory peripheral circuitry with neat diagrans.
9. Discuss in detail about the address decoders.
10. Write a note on sense amplifiers.
11. With neat diagrams, explain about voltage references.
12. IMustrate the building blocks of Memory architectures and memory peripheral
circuitry adapted to operate for non-volatile memory.
[NOVIDEC-2020 & APRMAY-2021
 UNIT ASICDESIGN
V AND TESTING

Chapter 12
ASIC DESIGN

12.1 INTRODUCTION TO WAFER TO CHIP FABRICATION PROCESs

FLOW (OR) SEMICONDUCTOR MANUFACTURING PROCESS

12.1.1 Introduction
The manufacture of each semiconductor components products requires hundreds
of processes. After sorting, the entire manufacturing process is divided into eight
steps

() Wafer processing.
(ii) Oxidation,

(i) Photolithography,
(iy) Etching,

() Deposition and ion implementation,

(vi) Metal wiring,

(vi) Testing, and

(vii) Packaging.

Silicon Wafer Chip.

Sand

process
Fig 12.1 Semiconductor manufacturing
 VLSI and Chip Design
12.2

Step # Process What happens

1. |Wafer Foundation for semiconductor
2. Oxidation Create Oxide film on wafer surface

3. Photolithography Draw circuit design of wafer

4
Etching Remove unnecessary materials
5. Deposition and ion implementation Coating thin flm at a desired
molecular or atomic level onto a
wafer
6. Metal wiringAllows electricity to flow by
depositing a thin metal film
7. EDS Process of testing to ensure
flawless semiconductor chips
8. Packaging Final wafer are cut into individual
semiconductor chips

Table 12.1 Steps involved in chip fabricationprocess

12.1.2 Steps
(1)Silicon Wafer Manufacturing
All semiconductor processes start with a grain of sand. Because
the silicon
contained in sand is the raw material needed to produce wafers, A wafer is a
round slice formed by cutting a single crystal column made silicon
of (Si) or
gallium arsenide (GaAs).

Fig 12.2 Silicon Wafer

ASIC Design
12.3
o
To extract high-purity silicon materials, silica
sand is required, a special
material with a silicon dioxide content of up to 95%,
which is also the main
raw material for making wafers.
Wafer processing is the process making of
and obtaining wafers.

(2) Oxidation
The silicon wafer manufactured in step 1 is not yet conductive. It has to go
through a process to make the wafers semiconductive.
o First, wafers go through the oxidation process. Oxygen or water vapor is
sprayed on the wafer surface to form a uniform oxide film.

Remove Thermal Oxide film

impurities oxidation test

Fig 12.3 Oxidation

This oxide film protécts the wafer surface during the subsequent processes and
also blocks current leakage between circuits. The film acts as a strong
protective shield.

WetOxidation Method
Dry Oxidation Method
Use oxygen Use water vapor

Slow speed and thin oxide Fast speed and thick oxide

layer layer

wet oxidation nethod

Fig 12.4 Dry oxidation and
 VLSl and Chip Design
12.4
(3) Pholithography: Photomask
a wafer
Photomask is the use of light to "print" circuit patterns onto i.
semiconductor parts drawing on the surface of the wafer.
a
In order to draw the circuit on the wafer, the photoresist is material that

responds to light is applied thinly and evenly on the Oxide film previously
placed on the wafer.

Now, when light transfers the pattermed photo mask, the circuit is drawn on
the wafer surface. Just like developing a photo, a circuit pattern is imprinted
on the wafer by spraying, developer and removing unlit areas from the areas

that are exposed to light.

After an inspection of the wafer to check whether the pattern is drawn well
and it moves on to the next step. Photomask can be divided into three steps

(i) Photoresist coating,

(ii) Exposure, and

(üi) Development.

According to the difference of UV light reactivity, photoresist can be divided

into two types: positive glue and negative glue. The former will decompose
and disappear after being exposed to light, leaving a pattern
of unreceived
areas, while the latter will polymerize
after being exposed to light to let the
pattern of the light-receiving part appear.

Photoresist
DE
Oxide layer
Wafer

Positive Photoresist
Negative Photoresist
Fig 12.5 Coating photoresist
AJC Design.
12.5
(4) Etching
Now it is time to remove unnecessary
materials from the wafer surface so
only the design pattern that
remains. This is done using a
liquid or gas etching
technique. All unnecessary materials are
selectively removed to draw the
desired design.

(i) Wet Etchingt

When chemical solutions are used for
etching then it is called wet etching.

(ii) Dry Etching

When gas or plasma is used then it is

called ry etching.

Mask
Materialto etch
Si-substrate.

No
Undercut Undercut

Isotropic: etches equally in all directions Anisotropic: etches at different rates in

different directions

t Fig 12.6 Wafer Etching process

The photolithography process and the etching process are repeated several
times on the wafer layer by layer. Here, an insulating ilm that separates and
process is
protects the stacked circuits is required. It is called a thin film. The
very similar to manufacturing a Multilayer PCB.

>) Deposition and lon Implementation: lon implantation

or atomic level onto a wafer is
Coating the thin film at a desired molecular
so thin, precise and sophisticated
called deposition. Since the coating is
on a wafer to give the
technology is required to uniformly apply the thin film
Lon implementation / Ion
semiconductor electrical characteristics.
implantation is also required.
 VLSI and Chip Destign
12.6
electricity but addi
semiconductor made of silicon does not conduct
A
It conducts current and has conductive properties.
impurities.
introduction of
implantation is a low-temperature technique for the
lon
offers more flexibility than
impurities (dopants) into semiconductors and
implantation can be used to
diffusion. For instance, in MOS transistors, ion
accurately adjust the threshold voltage. In ion
implantation, dopant atoms are
ratios, and
volatilized, ionized, accelerated, separated by the mass-to-charge
directed at a target that is typically a silicon substrate.
Doped Region

siO2 PR.

Si

Diffusion lon Implantation

Junction depth

Fig 12.7 Siliconion inplantation process

(6) Metal Wiring
Now, in order for this circuit to work, an electrical signal must be applied. It is
necessary to create a path for electricity to pass through according to the
circuit pattern. This process is called the metal wiring process.

Barrier Metal

Aluminium

Oxide filim

nplant

Wafer

Fig 12.8 Metal interconnect in semiconductor

ASICDesign

12.7
It is a process that allows electricity
to flow by depositing a
nsing materials such as thin metal film
aluminum, titanium or tungsten so
pass through that electricity can
the semiconductor wells.,

) Testing - Energy Dispersive Spectroscopy (EDS)

o
EDS is the process of testing to ensure flawless semiconductor chips. In
other
words, it is a testing step to sort out
defective chips.
Yield is a percentage of prime chips relative to
the maximum chip count on a
single wafer. The semiconductor chips selected
through the EDS process are
made ina formsuitable for devices.

3) Packaging

This is the last process, the packaging process. The wafer completed through
the previous steps are cut into individual semiconductor chips that can be
loaded on an electronic semiconductor device.
An individual chip must have a path to exchange electrical signals with the
outside and havea form to protect it from various external elements.

Wafer Oxidation Photolithography Etching

Metal lon
Testing Deposition
wiring implantation

Packaging

process flow chart

Fig 12.9 Semiconductor manufacturing
on
diced or saw chips are placed
The wafer is cut into individual chips and the
step, the contact point of the semiconductor
the PCB board. In the bonding
 VLSI and Chip Design
12.8
the contactpoint of the substrate
r chip placed on a substrate is connected with
Then molding fnishes the chip package to its desired shape.lt stt
name, the semiconductor chin
After final test, sealing and labeling the product
we commonly see is
completed.6thsgeoviet 1iizsi
IN TEST AND
12.2 MICROCHIP DESIGN PROCESS AND ISSUES
VERIFICATION OF COMPLEX CHIPS

12.2.1 Introduction
a Definition
A
microchip is also called a
chip, computer chip or Integrated Circuit (1C)
which is a unit of integrated circuitry that is manufactured at a microscopic
scale using a semiconductor material, such as silicon or, to a lesser degree,
germanium.

Electronic components, such as transistors and resistors, are etched into the
material along with intricate connections that link the components
in layers,
together andfacilitate the flow of electric signals.

Microchip components are so small and are measured in nanometers (nm). Some
components are now under 10 nm, making it possible to fit billions of
components on a single chip.

a Chip Design

Chip design is a process of designing a chip and is an essential part of

electronics engineering. This process of chip designinvolves the knowledge of
circuit design and its logic formation.

Allchips are made using basic elements which are known as transistors. The
Metal Oxide Silicon Field Efect Transistor (MOSFET) is the basic building
block of digital chips which isused to imakecomplex circuits.
 ODesgn,
12.9
12.2.2 Trends in Chip Design
he modern trends in chip design together with
advance EDA tools have
dhe design made
of chips more scalable and more reliable than ever
before.
The nhysical size
of transistors has decreased enormously over
past decade. This
led to both very large chip and also a low voltage
chip design which mean's that
chips consume very less power, even a
few micro-watts of power. This allowed
high scalability of chips in various
markets and industries both in terms chip
of
size and market penetration,

The other important trend in the chips

design is the use of co-simulation
(hardware and software) design. In this way, the
whole algorithm is divided in
twosub-blocks:
i) Sub modules which require intensive computation are taken to hardware
iLe. chips, and

(i) Complex modules which are dependent on the data and are involved in
decision making are processed on the software.
Finally, IP cores are very .important for chip design process. If whenever a
&

designer has to implement a complex design, he can use IP cores save time and
reduce development risk.

12.2.3 Chip Design Flow

* Chip design process is very similar to the FPGA design flow. There is only One
diference: chips are manufactured or fabricated after the design is finalized. The
chipdesign flow is.shownin Fig 12.10.

) System Specifications
The first and most important step of the chip design
process is defining and
CTeating the specification of the system.
2) Architecture
Design
we decide which
ne next step is to. design the architecture of the system where
blocks are system is going to operate.
going to be used and what hierarchy level this
 VLSIand Chip Destgn
J12.10

System Specifications

Architecture Design

Basic Logic Design

Modification
Required

Logic
Verification

Physical Design

Modification
Required
Physical
Verification

Chip Fabrication

Fig 12.10 Chip design

flows
(3) Basic Logic Design
A
fterthe architecture design, the basic logic system is designed.

(4)Logic Verification
When the schematic design of
the system is complete, the next step isto verify
the system functionality. This can be done using
the simulations in sametool.
ASICDesign
12.11
This step is important, as
it will help to verify at the initial
level and if any
issue is found in the functionality
of the system, it can be removed in the start.
Tf any issue is
found, then one has to go back to the
schematic design level and
debug for issues and come up
with the updated schematic. The verification
waveforms for the above system are
shown. In complex systems, the
simulation and verification the systems
of will be a tougherjob.
s)
Physical Design Layoutos
istetsttar bra 3 s
bait
The next and most important step is to translate the system to. physical level.
At
this level, the
schematic is converted into physical layout using basic building blocks.
(6)
Physical Design Verification
Before going to fabrication facility, the verification of physical layout is required.
For that multiple verification
techniques are used as follows
(i) Design Rule Check (DRC) where the designing tool checks for any
violations in the design rules, like metal spacing, contact sizes etc,
(ii) LayoutVs Schematic (LVS) check is used to verify if the layout designed
is similar to the schematic design, and checks all the connections and
verifies them, and
(iii) Timing and Power Analysis is used to verify if the layout made violates
any timing issue and adds unnecessary delays, if there is any violation,
this can be removed by adding inverters and buffers, where required.
so this
Poor planningof timing delays results in lower frequency of operation,
validation and correction of timing delays is important for any designer.

power analysis shows that how much power the system is going to consume
The

and also it tells at what voltage the system is going to operate.

) Fabrication and Final Testing

Whiledesigning
The final step is the fabrication of the physical layout design.
System on the tools, all the libraries and layer
information is provided by the
system is designed and
Toundry which is going to fabricate the chip. After the
Verified, a.GDS file is sent to foundry for fabrication.
 VLSI and Chip Design
12.12|
on hardware, for that a prototype PCB can be made
The final testing is done are added onto tha
all necessary interfaces
on which the chip is mounted, and
another important step is to add internal test
testing,
PCB for testing. For final testing
system which are critical to debug the system while
nodes within the
on actual PCB.
Verification
12.2.4 Issues in Test and are as follows
verification of complex chips
The issues identified in test and

() Specification Problems.
Insufficient definition.
Lack of necessary conditions.
Misunderstandings between people.
(ii) Implementation Problems.
Insufficient performance.
Improper block partitioning.
Block interface mismatching.
Excessive power consumption.
(iii)Verification Problems.
Slow software simulation.
Problems with the hardware -software interface.
System function verification.

12.3 EMBEDDED CORES AND SOCS

12.3.1 Embedded Cores
A Definition
Embedded systems are domain and application specific and are built arouna
centralcore is called as embedded core.

Embedded hardware/software systems are basically designed to regulate a

physical variable or to manipulate the state of some devices bysending some
 Design 12.13
C
control signalsto the Actuators or devices connected to the ports of the
O/P

System, in response to the input signals provided by the end users or Sensors
swhich are connected to the input ports.

Memory

P System O/P
Ports Core Ports

Other supporting
Integrated circuits
and Subsystems

Embedded System

Fig 12.1l Overview of Embedded Core

algorithm and
The memory of the system is responsible for holding the controi
core falls into any one of the following
other important configuration details. The
categories:
Processors.
(i) General Purpose and Domain specific
-Microprocessors.

- Microcontrollers.

- Digital Signal Processors.

(ASICs).
() Application Specific Integrated Circuits
(ii) Programmable LogicDevices(PLDs).
(iv) Commercial off-the-shelf Components
(COTs).

12.3.2
General Purpose and Domain specific
Processors
purpose domain specification processors, almost 80% of the
n general and
Gmbedded systems are processor/ controller based.
The processor may be
 VLSI and Chip Destgn

12.14 processor, depending onthe

microcontroller or digital signal
a
microprocessor.or
domain and application.

(1)Microprocessor
representing a central processing unit It
A microprocessor is a silicon
chip
requires the combination of other hardware lie
which
is a dependent unit etc. jor proper functioning.
memory, timer unit, and interrupts controller,
are available
we have two ifferent system architectures
To design up,
memory.
Harvard -Contains Separate buses for data and program
()
Von-Neumann- Shared
a Single bus for both.
(iü)
are available
Two Instruction set Architecture

(i) Reduces Instruction Set Computing (RISC).

(ii) Complex Instruction Set Computing (CISC).

(2) Microcontroller

A microcontroller is integrated chip that contains a CPU, scratch

a highly

arrays, on chip ROM/FLASH

pad RAM, special and general purpose register
memory for program storage, timer and interrupt control units and dedicated

IOports.
Some embedded system application require only 8 bit controllers wherets
some requiring superior performance and computational needs demand 1632
bit controllers. The instruction set of a microcontroller can be RISC or CISG
application
Microcontrollers are designed for either general purpoSe
requirement or domain specific application requirement.

(3) Digital Signal Processors

DSP are powerful special purpose 8/16/32 bit
designed to
microprocessor
meet the
embedded
computational demands and power constraints of today''s
audio,video and communication applications.
ASICDesign 12.15
DSP are 2 to times faster than general purpose microprocessors in signal
3

processing applications. This is because of the architectural difference

hetween DSP and general purposemicroprocessors.
DSPs implement algorithms in hardware which speeds up the execution
whereas general purpose processor implement the algorithm in software and
the speed of execution depends primarily on the clock for the processors.

12.3.3 Application Specific Integrated Circuits (ASIC)

4 ASIC is a microchip design to perform specific and unique applications. Because
of using single chip for integrates several functions there by reduces the system
development cost.
As a single chip ASICconsumes a very small area in the total system. Thereby
helps in the design of smaller system with high capabilities or functionalities.

12,3.4 Programmable Logic Devices (PLDS)

are
A PLD is an electronic component that is used to build digital circuits which
a
reconfigurable. A logic gate has a fixed function but PLD does not have
a

defined function at the time of manufacture.

PLDs offer customers wide range of logic capacity, features, speed, voltage
a
*
at any
characteristics. It can be reconfigured to perforim any number of functions
time.
are inexpensive
A. variety of tools are available for the designers of PLDs which
two
and help to develop, simulate and test the designs. PLDs having following
major types:
(CPLD)
0) Complex Programmable Logic Device

CPLDs offer much smaller amount of logic up to 1000gates.

() Field Programmable Gate Arrays (FPGA)

It offers highest amount of performance as well as highest logic density and the
most features.
 VLSI and Chip
Design
12.16|

Advantages of
PLDs

The advantages of PLDs are,

more flexibility during the design cycle
() PLDs offer customer much
prototypes or production parts
(i) PLDs do not require long lead times for
shipment
because PLDs are already on distributors shelf and ready for
even after a piece of equipment is shipped to
(ii) PLDs can be reprogrammed
a customer.

12.3.5 Commercial off-the-shelf components (COTs)

easy integration and
COTS products are designed in such a way to provide
interoperability with existing system components.
a general purpose or
The COTS components itself may be develop around
domain specific processor or ASICs or a PLDs.
are readily available in the
The major advantage of using COTS is that they
a extent
market, and a developer can cut down his/her development time to great
the
The major drawback of using COTS components in embedded design is that
manufacturer of the COTS component may withdraw the product or discontinue
the production of the COTS at any time if rapid change in technology occurs.

Ø Advantages of COTS
(1) Ready to use.

(i) Easy to integrate.

(ii) Reduces development time.

12.3.6 System On Chips(SOCs)

a Definition

System on chip (S0C) is an integrated circuit where all the functional elements
peripherals are
such as dedicated hardware, processo, memory, VO, and
embedded onto a requirements.
single platform chip to meet
the product design
ASICDesign |12.17

Dedicated /O and
Hardware Processor Memory
Peripheral

Computer Network

Fig 12.12 System on chip

4 A current-day system on a chip (SoC) consists of several different compönents of
a system such as the CPU (a microprocessor or microcontroller), memory,
input/output (/0) interface and wireless blocks, on a single silicon substrate.
4 Most SoCs also use various pre-designed hardware block which is called as IP
cores, to improve design time to market.

12.3.7 Design Flow of SOCs

SOC design flow works on multiple optimization goals and constraints and
therefore requires various SOC development skills and EDA tools. SOC
as illustrated in the
development process can be broken into multiple stages
following Fig 12.13.

(1) SOC Specification

For any SOC development, the first step is to specify the requirements. The
as well as the software
specifications are required for both the hardware
portions of the design.
interfaces between the
The specifications must completely describe all the
design and its environment.
The Hardware Specifications includes the functionality,
various hardware
to other hardware
components (processors, memories etc), external interfaces
components, interface
(pins, buses etc), internal interfaces between hardware
details such as
to Software, timing, performance and otaer physical design
area and power.
structure.
General Software Specifications includes the functionality, software
design.
interface to hardware components, timing and performance of the
 VLSI and Chip Design
12.18|
Soc Design Flow

Soc Specification

Architecture Design
(Hardware/ Software
Partioning)

High Level Modeling

Softwáre Development

RTL Design

Front-End HWISW
Design Cosimulation
Functional Simulation Software Testingand
and Verification J
Refinement

RTL Synthesis and DFT

Final code

Gate Level Netlist

Place and Route

Physical
Design Timing Verification
(Back-End) and Signoff

Physical \Verification

Design GDSI

Manufacturing

Post-Silicon Validation
and Integration

Mass Production

a
Fig 12.13 SoCDevelopment Overvieyl oe!
 12.19
ASICDesign

SOC Architecture Design

(2)
After gathering all the SOC specifications comes the architecture design.
Architecture design consists of behavioral and functional modeling of the
specifications.
The architecture is specified in terms of combinational logic blocks, data
finite state
registers, buses,- on-chip and off-chip memories, switches, and
machines. The optimal architecture development in terms of appropriate
a number of
balance between cost, power, area, and performance involves
as deciding which softvware and
complex decisions and tradeoffs, such
memory architecture
hardware components, processor(s), bus architecture and
to be used.
hardware and software
In this stage the design is partitioned into the
components.

(3) Software Development

developed and tested
Both the hardware as well as the software for the SoC is
concurrently in the design process.

(4) SOC Hardware Development

software, the hardware
After the design is partitioned into hardware and
these stages
components go through various stages of development. At each of
on a number of design constraints.
the hardware is optimized based
and refined after each
Furthermore, the design is simulated, tested, analyzed
requirements.
stage toensure that it is meeting the design

(i) High Level Modeling

description of varioushardware
High level modeling is the abstract algorithmic
system C or other high level
components. This modeling is generally done in C,
languages.
(i) RTL Design

The term RTL refers to Register Transfer

Level. This level of design
circuit and a
abstraction lies between behavioral description of the desired
 VLSI and Chip Design
12.20
as a set of registers and a set of
structural onc. The RTL describes the circuit
transfer functions describing the flow of
data between the registers.

The commonly used languages for RTL

development are Verilog and VHDL

(iii) Functional Simulation and Verification

functional correctness
The developed RTL code needs to be verified for
before moving to further stages of design. All the
bugs found in the
to fix the issues.
verification stage are reported back and the code is refined
the
This step makes sure that the RTL code is logically correct and matches
behavioral model of the design.

(iv) Logic Synthesis

Logic synthesis is the process which transforms RTL (verilog or VHDL)code
into a gate level netlist that describes the hardware (logic gates and the wires
connectivity). Synthesis process involves three steps:

(a) Translation,

(b) Mapping,and

(c) Optimization.

(5) Physical Design Implementation

Physical Design is the process of translating the gate level netlist into a
physical layout. This physical layout consists of various metal shapes and
sizes which can be drawn onto masks and manufactured on the silicon wafer.

The Physical Design process can be broken down into multiple stages as
illustrated in Fig 12.14.

() Floor planning
Floorplanning is the first step of physical design. The design is s
partitioned into various smaller subsystems based on the system
architectuv
and design requirements.
ASICDesign

Eloor planning determines

12.21|
the aspect ratio and area
create the placement rows of the layout. Here we
for standard cells and fix
around the boundary. Any macros the placement of I/Os
in the design are also placed
floorplan stage. during the

Power planning is also typically

done during floor planning.

Floor planning
Implementation

Logic Placement

Clock Tree Synthesis

Design

Physical
Routing

Timing Analysis &

Signoff

PhysicalVerification &

Signoff

Fig 12.14 Physical design implementation

(ii) Logic Placement
In this stage all the standard cells in the design are placed and assigned a legal
location. After the placement EDA tools performs a number of optimizations
toimprove placement and congestion.
EDA tools also use timing driven placement algorithms to optimize the
placement while considering the timing requirements of the design.
(ii) Clock Tree Synthesis
considered as an
During the Floorplanning & placement stage, the clock is
are performed based
ideal network. The optimizations in the placement stage
same time. In
on the assumption of an ideal clock reaching to all flops at the
to all flops.
CTS, a clock network is created to distribute the clock
 VLSI and Chip Design
12.22
A good quality clock network is very crucial to meet the timing requirements
of the design.
(iv) Routing

Once all the standard cells are legally placed and the clock network is
synthesized, all the connecting data nets neced to be laid out on the metal
layers. This is done during the routing stage.

After routing all the nets, a number of optimizations are performed based on
the design timing requirements and analysis.
(v) Timing Analysis & Signoff
After the design routing, static timing analysis
is performed on the design.
This step is critical to analyze the performance
of the design.
The timing signoff ensures that all
the design elements are meeting the
specified timing requirements and
the design is working at the desired
frequency.
(vi) Physical Verification & Signoff
After the routing is completed,
the layout must be completely
ensure its correct verified to
electrical and logical functionality.
The physical verification
signoff ensures that the
fabrication specified rules design meets all the
and can be easily manufactured.
(6) Design for Manufacturing

o At the end
of the physical design process,
simulation and other the design is analyzed
tools to make sure with
that it meets the specified
parameters such as operational
frequency, power consumption,
electrical integrity. functional integrity and

When all physical

design checks are
rectified and re-verified, done and the known
bugs have been
the design GDSII
semiconductor fabrication fle is sent to the specialized
plants, also called
foundries or fabs.
SICDesign

Graphic Design System 12:23

(GDS)
of
the design. The foundry uses
II file in VLSI contains
tains physical information
thisinformation to create
The manufacturing
process largely the SoC chip.
consists of two steps:
(a) Wafer fabrication.

(6) Assembly, is the

precise and automated process
functionalsilicon chips. of packaging the fully
The packaged chips are
again tested to ensure that
during the packaging process. they were not damaged

7)Post-Silicon
Validation and Integration
The post-silicon validation offers
the benefit of running at real system
(range of GH), as the tests are performed on speeds
the manufactured silicon chips.
But it is more complex due to the physical nature
of the validation target. In
addition, post-silicon validation is usually done on a
strict schedule, in order
to meet the time-to-market requirements.

12.3.8 Advantages of SOCs

SOCs offer several advantages over traditional ICs as follows:
) Compact size
By integrating all the components of a system onto a single chip, SOCs can
Significantly reduce the size of electronic devices.

(0) Low power consumption

SOCs can operate at lower power levels due to their high degree of integration and
efficient design.

(i) Cost-effectiveness
SOCs can be more cost-effective than traditional ICs due to their high degree of
Miegration and the use of standard cell-based design techniques.
(") Improved performance
SOCs can design and the use of
offer improved performance due to their efficient
high-performance
components.
 VLSI and Chip Design

12.24

(v) Flexibility different electron!

specific requirements of
. SOCs can be customized to meet the
flexible and adaptable.
systems, making them highly

(vi) Reliability
and the
improved reliability due to their high level of integration
SOCs can offer process.
testing and validation techniques during the design
use of advanced

(vi) Integration of advanced features

can enable the integration of advanced features such as Artificial
SOCs
development
Intelligence (AI) and machine learning capabilities, enabling the
intelligent electronic systenm

12.4 TWO MARKS QUESTIONS AND ANSWERS

1. List out the steps involved wafer to chip fabrication process.

The steps involyed wafer to chip fabrication process are,

() Wafer processing,

(i) Oxidation,
(ii) Photolithography,
(tv) Etching,

() Deposition and ion implementation,

(vi) Metal wiring,

(vii) Testing,
and.Ta eot aa als
(vii) Packaging.
2. Define Ion implantation.
Ion implantation is a low-temperature
technique for the
introduction ofimpuriu
(dopants) intto semiconductors
and offers-more
instance, in MOS transistors, flexibility than diffusion. For
ion imnplantation can be
the threshold voltage. used to accurately adjust
 ASIC
Design

,What is microchip? 12.25

A microchip is also called a
chip, computer
which is a unit chip or Integrated Circuit (1C)
of integrated circuitry that
I1sing a semiconductor is manufactured at a microscopic
material, such as silicon or, scale
a
to lesser degree, germanium.
What do youmean by
chip design?
Chipdesign is a process
of designing a chip and is an essential
engineering. This process part electronics
of chip design involves the knowledge of
and its logic formation: of circuit design
5.
Define embedded core.
Embedded systems are domain
and application specific and are
central core is called as embedded core. built around a
Embedded hardware/software
systems are basically designed
to regulate a
physical variable or to manipulate
the state of some devices by sending some
control signals to the Actuators or
devices connected to the O/P ports
system, in response to the input signals of the
provided by the end users or Sensors
which are connected to the input ports.
. What you mean
do by PLD?
A Programmable Logic Device (PLD) is an electronic
component that is used to
build digital circuits which are reconfigurable.
A logic gate has a fixed function
but a PLD does not have a defined function at the time
of manufacture.
PLDs offer customers a wide range
of logic capacity, features, speed, voltage
characteristics. It can be reconfigured to perform any number
of functions at any
time.

Write the advantages of PLD.

The advantages of PLDs are,

() PLDs offer customer much more flexibility during the design cycle.
(1) PLDs do not require long lead times for prototypes or production parts
because PILDs are already on distributors shelf and ready for shipment.

() PLDs can be reprogrammed even after a piece of equipment is shipped to

a customer.
 VLSI and Chip Design
12.26

8. Define SOC.
System on chip (SOC) is an integrated circuit where
all the functional elemant.
are
such as dedicated hardware, processor, memory, VO, and peripherals
embeddedonto a single platform chip to meetthe product design requirements.
9. List out the advantages of SOCover traditional ICs
as follows:
SOCs offer several advantages over traditional ICs
() Compact size
can
By integrating all the components of a system onto a single chip, SOCs
significantly reduce the size of electronic devices.

(ii) Low power consumption

SOCs can operate at lower power levels due to their high degree of integration
and efficient design.

(iii) Cost-effectiveness
SOCscan be more cost-effective than traditional ICs due to their high degree of
integration and the use of standard cell-based design techniques.
(iv) Improved performance
SOCs can offer improved performance due to their efficient design and the use of
high-performance components.

12.5 REVIEW QUESTIONS

1. With neat sketches, explain in detail about the wafer to chip fabrication
process flow.

2. Explain in detail about microchip design process.

3. Brief about enbedded core.
4. Write note on System On Chip.
5. Illustrate the design flow of SOC.
6. List out the advantages of SOCover traditional ICs,
 UNIT-V
Chapter 13
TEST BENCHES
13.1 FAULT MODELS

13.1.1 Introduction
Definition

In order to evaluate the effectiveness of a test approach

and the concept of a
good or bad circuit, we must relate these faults to the circuit model or
derive a
fault model which is a model for how faults occur and their impact on circuits.
The most popular model is called the Stuck-At model and the Short Circuit/Open
Circuit model can be a closer fit to reality, but it is harder to incorporate into
logic simulation tools.

Effectiveness of a fault model:

The effectiveness of test patterns generated using the fault model in
detecting defective parts.
The accuracy with which it represents the effects failures.
of

Its tractability as a design tool.

v
Scalability of its complexity with the increasing size of VLSI circuits.
Its usefulness in determining the location ofa defect on a chip.

13.1.2 Stuck-At Faults

Fault is a Functional Fault on
a
Boolean (Logic) Function
Stuck-at
Implementation.
 VLSI and Chip Design
|13.2|

Itis not a physical defect model:

»,

Stuck-atl does not mean line is shortedto

VDD.

Stuck-at 0does not mean line is grounded.

It is an abstract faultmodel:
means when the line is applied a logic 0 and it
A logic stuck-at l
produces a logical error.
,
- A logic error means0becomes
1 or vice versa.

With a stuck at fault model you are applying a structural test approach. Instead of
testing all combination of 1's and 0's to a VLSI device, you will test witha
reduced set of test vectors. Stuck at Fault Models operate at the logic model of
digital circuits. An input or an output can be Stuck at Zero (S@0) or Stuck at
One (S@l).
13.1.3 Examples

Input
utput

(a) Inverter

A D

(b) Inverter Logic Table

Inverter stuck faults list: A S@0, A

S@1,D S@0, D S@I
Fig 13.1
With a stuck at fault you apply a pattern (set
of1's and 0's) to the inputs of the
you get a faulty response.
logic gate such that Suppose A is S@1. Easy test, you
need to apply
a 0. Now lets look at
the output D stuck at 0, you need to apply a 0
to A. Table 13.1 tabulates the test pattern per Sa@ fault.
TestBenches 13.3

S@ Fault Test A Pass D Failing D

A S@1 1

A S@0 0 1

D S@1 1 1

D S@0 1

Tab 13.1 Inverter S@ Fault and Testtable

# Now while you there exist 4 faults to test you only need 2 tests as shown in the
table below. This is commonly called fault collapsing.
A Stuck @ Faults Detected
1
A- S@0, D - S @1
-
A-S@1, D
S@0

Tab 13.2 Inverter S @ Fault coverage of tests

Fault Excitation
1 ERROR
A 1/0
ERROR
1/0
C

E
B

Fig 13.2 A logic defect circuit

output of AND at point G will be but due to
1, logic
3 In example Fig 13.2, at the
on line G by applying a logic value 1 in
defect it is 0. Activates the fault S-A-0
we get the logic error as 0 instead of 1.
line G and will
Model
3.1,4 Switch Level Fault
a
circuit is specified at the transistor level. For example, netlist of
Here, the
are considered as ideal switches in this model.
CMOS gates. MOS transistors
13.4| VLSI and Chip Design

Two types of switch level fault models are common:

(i) Stuck-Open Fault.
(ii) Stuck-Short Fault.

(1) Stuck-Open Fault Model

In this fault type, a transistor becomes permanently non-conducting due to
some defect. The gate output may depend on its previous state.

0 A M1
Hh stuck Open

M2

Test Vector

M3 M4

Fig 13.3 2-input WOR gates in CMOS in stuck-open

The load capacitance CL is shown in Fig 13.3.
MOS M, is stuck open which
means Vdd is disconnected
from the CMOS logic. Due to the fault, no current
flow is allowed in pull-up logic. Hence, we
must apply a test vector that must
result in the flow of current in pull-up
logic (in the non-faulty circuit).
o Only this test will differentiate between
the results in faulty and non-faulty
operations so that we could examine the output
F and decide whether this fault
or
has occurred not.

The only test vector possible is AB = 00.

This input makes both M, and M2
conducting, and Vdd is connected to the output.
Pull-up logic willcharge tng
load capacitor, and we will observe logic-1 at output
if the circuit is not faulty.
D.t cince it is defective, it will not be connected to Vad
and it show logic U.
TestBenches 13.5

We additionally apply an initial test vector AB =

10to first discharge the load
into a known state logiC-0. So, we need .to apply a
pair of vectors in a
particular sequence. In this case, the test pattern is AB = {10; 00}. This
experiment is also known as the Two-pattern test.
3UCOc
(2) Stuck-Short Fault Model
Here a transistor is permanently conducting (i.e., source-drain shorted) in the
presence of a fault.

Both pull-up(pMOS) may

and pull-down(nMOS) networks become
conducting. This condition behaves like a oltage divider, thereby causing the
output to reach some indeterminate level.

M. )Stuck-Short

B M2

Test Pattern

Mg M4

High Current
Flowing

Fig 13.4 2-input NOR gates in CMOS in stuck- short

Due to this, high current will be flowing from Vàd to GND. It will eventually
increase the static power dissipation. Ideally, CMOS logic considerably
consumes zero static power. Hence, we can detect this type of fault by
measuring static power dissipation.
presence of a
Test vector causes a conducting path from Vàd to GND in the
fault.
 VLSI and Chip Design
13.6
= 10. In anon-faulty circuit, this should
turn off the
We apply test vector AB
on, resulting in
logic. But the fault will cause the pull-up logic to turh
Sipull-up
a heavy static current.

90hd oclt 21.l03tT2

13.2 INTRODUCTION TO ASICS

a Definition

An Application Specific Integrated Circuits (ASIC) is an integrated circuit

designed for performing a particular operation,, instead of general-purpose
operation. The chips may also be designed for the own applications.

d ASIC design methodology uses chips with an array of prefabricated gates (gate
arrays) or chips based on libraries of standard function cells (standard cell
design).

ASIC is not generally software programmable to perform a

wide variety of
different tasks. A silicon chip (or) Integrated
Circuit (1C) is more properly called
a die.

Silicon
die

(a)
0.1 inch (b)
utey12 Fig 13.5 A silicon chip
An ASIC will have an
embedded CPU manage
may be implemented as to the suitalble tasks, An
an FPGA..
It ASI
implemented using maybe considered separately (OL)
hybrid technique with
programmable lopgic
specific blocks. and application
Modern ASICs often
include 32-bit processors,
RAM, EEPROM, memory
flash memory. Such an blocks such as ROM,
ASIC is called as
Svstem on Chp
TestBenches
13.7
(SoC). Hardware Description Language
(HDL) such as Verilog (or) VHDL is
used for implementing ASICs.

Advantages *oi3inn
Someof the important advantages
of ASICs are:
(i) Better performance due to the customized
design.: o22299
(ii) High reliability.
(ii) More secure for the design circuit.
(iv) Cheaper cost.
h(v) Lower power dissipation. 2utob lams3
(vi) Faster turn-around time.
E Disadvantages

() ASIC cannot be easily replaced when there is a damaged in the product.

tectiss (ii) Testing and debugging are very difficult on an ASIC.ussd
13.2.1 Types of ASICs

ASIC implementation choice

Full - custom Semi - custom Programmable

Standard cell Gate Array PLDs FPGAs

based based

Chanelled gate Chanelless gate Structured gate

Array Array
Array

Fig 13.6 Types

of
ASICs
 VLSI and Chip Design
|13.8

(1) Full-Custom ASICs

Definition

In full custom ASIC, some (or) all of the logic cells, circuits (or) layout
a

specifically for one ASIC are customized by the designer. In this design, every
transistor is designed and drawn by hand.
Here, the circuit is partitioned into sub-blockS and each block can be of any
size/shape. Placement on any location is allowed in fullcustom design style.

Example: Microprocessor designers get the solutions

for their problems by
writing suitable codes by hand.

The analog circuits, optimized memory cells, mechanical

structures may be
included in this design.

The predesigned (or) pretested cells cannot

be used in this design. i.e., if suitable
existing cell libraries are not available,
then we can use the full customn design.
The existing cell libraries have
less speed, and consumes more power.

Specification

System
Architecture

Logicdesign

Circuit design

Logout

Fig 13.7 Fullcustom

design flow
Test
Benches 13.9

Advantages

) Custom design at the physical level.

(ii) Smallest, fastest, and lowest power circuit.

(ii) High degree of optimization in performance and area.

(iv) Substantial reduction in die (chip) area.

() Ability to integrate analog component and pre-designed component.

g Disadvantages

(1) Increase design time.

(ii) Custom mask set is expensive

(ii) Economical only for High volume.

(iv) Complexity and highest risk.

(2) Semicustom Design

a Definition

Semi-custom IC design is a methodology for making an integrated circuit in

which a portion of the circuit function is predefined and unalterable, while other
portions can be configured to meet the design 's specifc needs.
are
The predesigned cells from a cell library are used by the designers. There
two types of semicustom ASICs.
(a) Standard-cell based ASICs.
(b) Gate-Aray based ASICs.

(A)Standard CellBased ASIC

cost and the

idea behind "cell based" design is to reduce the design
The
library.
design time by reusing the library of cells called standard cell

The standard cell methodology is a method of designing ASICs with mostly

digital - logic features.
 VLSIand ChipDesign
13.10

Standard - celi
area

Fixed
blocks

OODD

0.02 in
500 um

Fig 13.8 Cell based ASICs (CBIC)

Figure 13.8 shows a cell -based
area (a flexible
ASIC(CBIC)die with a single -
standard cell
block) together with four
fixed blocks. The small squares
around the edge of the die are
bonding pads that are connected
the ASIC package: to the pins of

The assembling process

of an ASIC can be automated
design. A flexible using standard-cell
block can be built from
several rows of standard
which can also be connected cells,
to' other standard cell
blocks. blocks (or) full custom

Cell Based Integrated

Circuit (CBIC)
A
Cell Based
IntegratedCircuit (CBIC) uses
standard cells. The predesigned logic cells known as
standard cells ar custom
library. These cells are designed and
then used in the design then inserted intoa
wired together using by placing ihem in rows and
'place and route' tools.
 Benches
Test
13.11
The standard
cell area is the rows of standard cells. For example,
OR gates, flip-flops, AND gates,
multiplexers are known as
standard cells.
Logic cell

Rows of Routing chainel

cells Feed through cell
(or)
cell area
Functionalg
module
(RAM) a9govbA
|multiplers

f1g 13.9 Standard cell structureieh t.)

The designer specifies the placement of standard cells and
interconnects on
CBIC.The standard cells can be placed anywhere on
the silicon chip that isall
the mask layers of a CBICare customized and are unique to a
particular user.
The main features of standard cell ASIC are:

(i) such as transistors and interconnect are customized.

Allmask layers

(i) Custom blocks can be embedded.

(ii) The manfacturing lead time is about eight weeks. 2992Isvhsaia
Standard cells can fit together like bricksin awall. The simple standard cell is
shown in Figure 13.9, power line (Vpp) and ground line (GND) run
horizontally on metal lines inside the cells.l:a
The interconnections between logic cells use spaces between rows of cells
called channels. The width of each row of standard cells is adjusted such that
they are aligned with spacer cells.

Ihe Fig 13.10 illustrates the standard cell library which is used in the semi

Custom design flow to shorten the design process.

 VLSI and Chip Design
13.12

Design Entry/ Analysis

Design Optimization

Standard
cells
Layout

Fig 13.10 Semi-custom design flow

MAdvantages
The main advantages of standard cell based ASIC are

() Cell based design has smaller, faster and lower power chips than gate
arrays.
(i) Higher productivity due to theuse of predefinedcells.
(ii) High performance and flexibility.
(iv) Less design time.
(v) Minimum risk.
(vi) More flexible to include digital as well as analog functions.

(vii) Good for bottom up design.

Disadvantages

() High expense of buying standard cell library.

(ii) Requires more time for fabrication due to prefabriçated cells.

(iii) Wasted chip area will be high due to the area occupied
by the wiring
channels can exceed 50% of the internal chip,

(B)GATE- ARRAY BASED ASIC

a Definition

In a
gate array (or) gate-array
based ASIC, the transistors masks are
compietely predefined on the silicon wafer. The predefined pattern of transistors
on a gate array is the base array.
 Benches
fest |13.13
The smallest element which is replicated to form the
base array are called
base cell (or) primitive cell.

The designers define the interconnect between transistors using custom

masks
to distinguish this type of gate array from other gate array, is
of it often called
Masked Gate Array (MGA)

Macro

Thedesigner selects the predesigned and pre-characterized logic cells from a

gate-array library. The logic cells in a gate irray library are called macros.
The base cell layout is same for each logic cell and only the interconnect is
customized. Thus the gate-array macro is similar to a software macro. TBM
calls the gate-array macros as books.

Both the cell-based and gate-array ASICs use predefined cells. In standard
cel, the fransistor sizes change in order to optimize speed and performance,
we can complete the
whereas the gate array use fixed size of transistors. Here,
diffusion steps that form the transistors and then stockpile wafer. Hence,
gate
array is called prediffused array. The tradeoff between areas and
performance should bemade in a standard cell
ASIC.

time and
Prediffused array uses macros (books) to reduce turnaround
gate-array is classified into
comprises a base array made from a base cell. The
three different types.

) Channeled gate arrays.

(ii) Channelless gate arrays.
(iii) Structured gate arrays
(a) Channeled
Gate Array
the
a channeled gate array architecture, the gate array is channeled that is
In
the rows oftransistors are wired. The important features of this
Space between
channeled gate array are as:
customized.
() Only the interconnect is
 VLSIand Chip Design
13.14|
spaces between rows of base cells
(i1) The interconnect uses predefined
221t
(ii) Manufacturing lead time isbetween 2. days and 2.weeks.

base cell

Fig 13.1l Channeled gate array

Figure 13.11 shows a channeled gate array. Rows of cells are separated using
interconnect. This structure is similar to CBIC except that the space for
interconnect between rows are fixed in height in a Channeled gate array, while
3the space between rows of cells can be adjusted
in CBIC.T
(b) Channelless Gate Array
The salient features of the channelless gate array
(channel-free gate array,
bt atsea-of-gates array, or SOG array) are as follows: h

S
io () Only some mnask layers are customized such as
interconnect.
(i) Manufacturing lead time is between two days
and two weeks.
There is nopredefined area for routing between
the cells on a channelless gate
array. Routing is done over
the top of the gate array devices as the first layer
of metal defining the connections between
metal is customized.
When an area of transistors is used
for routing, the transistors are left unus
k
inspite of connecting the devices
using contacts.t oin.
leigoust?
Customizing the contact
layer in a channelless gate array allows us to increase
the density of gate-array cells because
we can route over the top of unused
contact sities.
 Benches
Tst 13.15

base cell

array of.
base cells

Fig 13.12Channelless gate-array (or) Sea of gates (SOG)

() Structured Gate Array

A structured gate array utilizes some of the features of cell-based ASICs

(CBIC) and Masked Gate Array (MGA). It is otherwise known as `an
embedded gate array(or) master slice (or) master image.
We know that, the MGA uses fixed gate-array base celI. This is the main
disadvantage as it makes the memory implementation difficult and inefficient.
So, some of the IC area is dedicated to a specific function in an embedded
gate array.
This embedded area either contains a different base cell that is more suitable
for building memory cells, or it can contain a complete circuit block, such as a
microcontroller.
OdNDODOOODO0OD

embedded
block

array of. OODODOD

base cells

Fig 13.13 Embedded gate array

 VLSI and Chip Design
13.16|
gate array. The important features of thie
Figure 13.13 shows an embedded
structured Gate array are :
customized.
Only the interconnect is
can be embedded
Custom blocks (the same for each design)
two weeks.
Manufacturing lead time is between two days and

13.3 ASIC DESIGN FLOW

as
Fig 13.14 shows the sequence of steps to design an ASICwhich is also called
design flow.

(a) Design Entry

Enter the design into an ASIC design system, either using a Hardware
Description Language (HDL) Or schematic entry.

(b) Logic Synthesis

R
Use an HDL (VHDL or Verilog) and a logic synthesis tool to produce a netlist
which is a description of the logic cells and their connections.

(c) System Partitioning:

Divide a large system into ASIC-sized pieces.

(d) Pre layout Simulation:

Check if the design functions correctly.

(e) Floor planning:

Arrange the blocks of the netlist on the chip.

() Placement:
Decide the locations of cells in blocks.

(e) Routing:
Make the connections between cells and blocks.
 Test Benches |13.17

h) Extraction:
Determine the resistance and capacitance of the interconnect.
) Post layout Simulation:
Check the design still works with the added loads of the
interconnect.srtu2

prelayout design entry logical

simulation design

VHDLVeilog

logic synthesis netlist

A B

system
partitioning

hnnnnnn
postlayout floorplanning
simulation
chip

placement
block

physical
circuit routing design
extraction 8

IIogic cells
back-annotated
netlist finish

Fig 13.14ASIC design flow

In the above steps, a to d are part of logical design and the steps e to iare part
of physical design.
 VLSI and Chip Design
13.18
BENCHES
INTRODUCTION OF TEST
13.4
Definition non
stimulus block, output checker and the DUT The
Test benches consist of
design and checks
synthesizable verilog code test
of
bench generates inputs to the
stimulus block generates the inpuis to our FPGA
that the outputs are
correct. The
correct
output checker tests the outputs to ensure they have the
design and the
values.

Testbench

Design Under Output

Stimulus Test (DUT) Checker

Fig 13.15 Architecture

of a
simple test bench

13.4.1 Components of Simulation

once it has been completed. The design block's
4 A design block must be tested
This
functionality can be tested by applying stimulus and observing the results.
as a
type of block is known as a stimulus block, and it can be written in Verilog
test bench. To completely test the design block, many test benches might be
employed.
(Stimulus Block)
CIk reset

(Design Block)
Ripple Carry
Counter

Fig 13.16 Stimulus block instantiates design block

TestBenches
|13.19
to the Fig 13.16, the stimulus block becomes the top-level block.
It manipulates
sionals clock and reset(rsi), and checks
it and displays output signal q.
The second method of applying stimulus is to use a top-level dummy module to
instantiate both the stimulus and design blocks. The
interface is the only way for
the stimulus block to communicate with the
design block. This style applyingof
stimulus is shown in Fig 13.17.

Top-Level Block

d_clk clk
Stimulus Block
Design Block
d_reset reset Ripple Carry
Countera
C_9

Fig 13.17 Stimulus and Design blocks instantiated in a dummytop-level module

The stimulus module derives the signals d clk and d reset, which are connected
to the signals clk and reset in the design block. It also checks and displays signal
cq, which is connected to the signal g in the design block.
4 The function of top-level block is simply to instantiate the design and stimulus
blocks.

13.5 WRITINGTEST BENCHES IN VERILOG HDL

4 We can write test bench using a variety of languages such as VHDL, Verilog and
System Verilog being the most popular. System Verilog is widely adopted in
industry and is probably the most common language to use.

3.5.1 Instantiating the DUT

as
The first step in writing a test bench is creating a verilog module which acts
the top level of the test. First want to create a module which has
no inputs or
Outputs in this case. This is because we want the testbench module to be totally
self- contained.
 VLSI and Chip Destgn

13.20|
use as our test bench are given
which we can
an empty module
The syntax for
as.
name> 0;
module <module
1

2
goes there
// our testbench code

4
name>
endmodule : <module
5
design
module, we must then instantiate the
we
have created a testbench
After
us connect signals to the design in order to
allows to
which we are testing. This
stimulate the code.
1 <module_name> # (
herel
module uses parameters they are connected
2 // If the
<parameter_name> (<parameter_value>)
3

4
5 <instance_name>
6 1/ collection to the module parts
7 <port_name> (<signal_name>),
<port_name) (Signal_name>)

Once we have done this, we are ready to start writing our stimulus to the FPGA.
This includes generating the clock and reset, as well creating test data to send to

the FPGA.

13.5.2 Modeling Time in Verilog

model
the time units to
#
In verilog, we use character followed by a
number of

delays. As an example, the verilog code below shows an example of using tne
delay operator to wait for 10 time units.
1 #10
 Benches
Tst 13.21
Thiseffectively
acts as a scheduler that is the change
in signal is scheduled to
take place after the delay time.

1
|/A is set to 1 after 10 time units
2 #10 a =
1' b1;

13.5.3 Timescale Compiler Directive

In order to specify the time units that we use during simulation, we use a verilog

compiler directive which specifies the time unit and resolution. We only need to
do thísonce in our testbench and it should be done outside of a module.

The code snippet below shows the compiler directive we use to specify the time
units in verilog.
1
timescale <unit time> /<Kresolution>

We use the <unit time> field to specify the main time unit of our testbench and
the <resolution> field to define the resolution of the time units in our
simulation.

13.5.4 Verilog Initial Block

Anycode which we write inside an initial block is executed once, and only once,

at the beginning of a simulation.

1 initial1 begin
2 I/ Our code goes here
3 end

13.5.5 Example
a gate. To do this,
For example, imagine that we want to test basic two inputs and
we would need code which generates cach of the four possible input

combinations.
 VLSI and Chip Design
13.22

In addition, we would also need to use the delay operator in order to wait for
some time between generating the inputs. This is important as it allows time for

the signals to propagate through our design.

use to write this test within
4 The verilog code below shows the method we would
an initial block.

1 initial begin
an
2 I/ Generate each input to AND gate
3 I/ Waiting 10 time units between each
=
4 and_in 2b'00;
5 #10
=
6 and_in 2b'01;
7 #10
8 and in = 2b10;
9 #10
and in =
10 2b'11;
11 end.

13.6 TWO MARKS QUESTIONS AND ANSWERS

1. What is fault model?
In order to evaluate the effectiveness of a test approach
and the concept of a good
or bad circuit, we must relate these faults to the circuit
model or derive a fault
model which is a model for how faults occur and their impact on
circuits.
2. Give the classification of
ASIC.

The IC design style can be classified as

(1) Full custom Design ASICs
(2) Semi custom Design ASICs
(a) Standard CellDesign
Test
Benches
13.23
(b) Gate Array Design
) Channeled Gate Array
(ii) Channel less Gate Array
(3) Programmable ASICS
(a) PLDs

(b) FPGA

3. What is ASIC?
An Application Specific Integrated Circuits (ASIC) is an integtated circuit
designed- for performing a particular operation, instead of general-purpose
operation. The chips may also be designed for the own applications.

4. What are the special features of

ASICs?

Some of the important advantages of ASICs are:

(i) Better performnance due tothe customized design.

(ii) High reliability.
(iii) More secure for the design circuit.
(iv) Cheaper cost.
(v) Lower power dissipation.
(vi) Faster turn-around time.
5. What is meant by full-custom ASIC? (or) Write the features of full-custom
ASIC design.
In a full custom ASIC, some (or) all of the logic cells, circuits (or) layout
every
specifically for one ASIC are customized by the designer. In this design,
transistor is designed and drawn by hand.
can be of any
Here, the circuit is partitioned into sub-blocks and each block
size/shape. Placement on any location is allowed in full custom design style.
The predesigned (or) pretested cells cannot be used in this design. i.e., if
suitable
can use the full customn design.
existing cell libraries are not available, then we
The existing cell libraries have less speed, and
consumes more power.
 VLSI and Chip Design
13.24|

6. List the advantages offull-custom ASIC.

Advantages
(i) Custom design at the physical level.
power circuit. l
() Smallest, fastest, and lowest
area.
(iii) High degree ofoptimization in performance and

(iv) Substantial reduction in die (chip) area.

() Ability to integrate analog component and pre-designed component.

7. Define semi-custom design.

Semi-custom IC design is a methodology for making an integrated circuit in
which a portion of the circuit function is predefined and unalterable, while other
portions can be configured to meet the design's specific needs.
8. What is mneant by CBIC? (or)

What is the standard cell-based ASIC design.

A Cell Based Integrated Circuit (CBIC) uses predesigned logic cells known as
standard cells. The standard cells are custom designed and then inserted into a
library. These cells are then used in the design by placing them in rows and wired
together using 'place and route' tools.

9. What are the features of

standardcell ASIC:?
The main features of standard cell ASIC are:
(i) Allmasklayers such as transistors and interconnect are customized.
(ii) Custom blocks can be embedded.
(iii) The manufacturing lead time is about eight weeks.

10. Define macrocell. a

The designer selects the predesigned and pre-characterized logicicells from a

gate- array library. The logiccells
ina gate array library are called macros.
 Benches
Test |13.25

.What is meant by gate-array based ASIC?

In agate array (or) gate-array - based ASIC, the transistors masks are completely
nredefined on the Silicon wafer. The predefined pattern of transistors on a gate
array isthe base array.

The smallest element which is replicated to form the base array are called base
cell (or) primitive cell.

12. Define channeled gate array and its features.

In a channeled gate array architecture, the gate array is channeled that is the
space between the rows of transistors are wired. The important features of this.
channeled gate array are as:
(i) Only the interconnect is customized.
(ii) The interconnect uses predefined spaces between rows of base cells.
(iii) Manufacturing lead time is between 2 days and 2 weeks.

13. What is meant by standard cell library?

The standard cell library contains of logic gates over a range of fan-in and fan
out. Besides the basic logic functions, such as inverter, NAND, NOR, XOR and
as
flip flops. A typical library also contains more complex functions such
multiplexers, full adder, comparator etc.

14. Differentiatebetween channeled and channelless gate array.

Channel Gate Array Channelless Gate Array

Only the interconnect is Only the top few mask layers are
customized. customized.

The interconnect uses predefined No predefined areas are set aside

Spaces between rows of base cells. for routing between cells.
Routing is done using the area of
Routing is dong using spaces. transistor unused.

Logic density is less. Logic density is higher.

 13.26| VLSI and Chip Design

s
15. Give the steps in ASIC design flow. kogt
The basic steps in ASIC design flow are as follows:
Design entry.
Logic synthesis.

System partitioning.
Pre layout simulation.
Floor planning.
Placement.
Routing.
Extraction.

Post layout simulation.

16. Give the comparisons between ASIC and FPGA.
Sr.No ASIC FPGA
An ASIC is a unique type of
An FPGA is programnmable
1
integrated circuit meant for a integrated ircuit.
specific application.
AnASIC can no longer be altered FPGA is alterable.
2.
once created.

An ASIC wastesvery little FPGA is not efficient in terms of

3. material, recurring costs are low. use of materials. A certain number
of components are always wasted.
Cost of ASIC is low only when it FPGA is better than an ASIC when
4. is produced in large quantity. building low volume production
circuits.
ASICs can't be used to test ASICs are tested on FPGA
5.
before
FPGAs. implementing.
Test
Benches |13.27

ASICs are not suitable for research FPGAS are useful for research and
and development purposes, as they development activities. Prototype
6. are not reconfigurable. fabrication using FPGA is
affordable and fast.
17. Define test benches.
non
Test benches consist of stimulus block, output checker and the DUT. The
checks
synthesizable verilog code of test bench generates inputs to the design and
generates the inputs to our FPGA
that the outputs are correct. The stimulus block
outputs to ensure they have the correct
design and the output checker tests the
values.

13.7 REVIEW QUESTIONS

1. Discuss in detail about fuultmodels
with examples.
types of ASIC with neat diagrams.
2. Give a detailed note on diferent
custom design.
3. Write a short note on full
4. Demnonstrate semi custom design with the
required diagrams.
diagrams.
based ASIC's design with neat
5. Describe briefly about Gate-Array
with neat sketclt.
6. Illustrate the ASIC design flow
7. abouttest benches.
Brief
Verilog HDL.
explain about writing test benches in
8. With evample,
 UNIT -V
Chapter 14
TESTING
14.1 AUTOMATICTEST-PATTERN GENERATION (ATPG)
A Definition
The task of the Automatic Test-Pattern Generation (4TPG) process is to
determine a minimum set of excitation vectors that cover a sufficient portion
of
the fault set as defined by the adopted
fuult model.
One possible approach is to start from a random set of test patterns. Fault
simulation then determines how many of the potential faults are detected. With
the obtained results as guidance, extra vectors can be added or removed
iteratively.
4 An alternative and potentially more attractive approach relies on the knowledge
of the functionality of a Boolean network to derive a suitable test vector for a
given fault.
U
A

Y.

Fig 14.1 Simple logic network, with sab fault at node U

 VLSI and Chip Design
14.2

Consider an example, illustrate in Fig 14.1,the goal is to determine the input

excitation that exposes an sa0 fault occurring at node U at the output of
the

network Z

In this case, U
to be 1
under normal circumstances that is A = l and B =1. Next
the faulty signal has to propagate to output node Z, So that it
can be observed,

This phase is called path sensitizing.

It is necessary for node X to be set to 1

and note E to 0. Then the (unique) test
vector for Usa0
(TA) 01 A
=B=C=D= 1, E=0

14.2 DESIGN OF TESTABILITY

14.2.1 Introduction
The key is todesigning the circuits that are testable for both controllability and
observability of a net determine whether a fault at that net can be detected.
Controllability is the ability to set (to 1) and reset (io 0) every node internal to
the circuit.

Observability is the ability to observe, either directly or indirectly, the state of

any node in the circuit.

Definition of DFT

The best way to facilitate the testability a

logic circuit is to increase the
of
controllability and observability of the logic circuit by adding it some extra logic
circuits or modifying its structure appropriately. Such an approach by adding
extra logic circuits to reduce the test difficulty is known as a testable circuit
design or Design of Testability (DFT).
Good observability and controllability reduces the cost of manufacturing testing
because they allow high faultcoverage with relatively few test vectors.
Testing
14.3
The Design For Testability (DFT)may be categorized as follows
() Adhoc testing,
(ii) Scan-based approaches, and
(ii) Built-in Self Test (BIST).

14.2.2 Ad Hoc Testing

4 Ad hoc test techniques are collections of ideas aimed at reducing the
combinational explosion of testing. They are only useful for small designs where
scan, ATPG (Automatic Test Pattern Generation), and
BIST are not available.
It is a complete scan-based testing methodology useful for all digital circuits.
The basic principles behind the ad hoc approach are to increase both the
controllability and observability of the logic circuits by using some of following
common techniques:

() Partitioning large sequential circuits,

(ii) Adding test points,

(ii) Adding multiplexers, and

(iv) Providing for easy state reset.

This technique is used for the bus in a bus-oriented system for the test purposes.
Each register has been made loadable from the bus and capable of being driven
onto the bus.
& Here, an internal logic values that exist on a data bus are enabled onto the bus for
the testing purposes. Frequently, multiplexers can be used to provide alternative
signal paths during testing.

4 In CMOS, transmission gate multiplexers provide a low area and delay overhead.
Any design should always have a method of resetting the internal state of the
chip within a single cycle of atmost a few cycles.
This makes the testing easier and also makes simulation faster as only a few
cycles are required to initialize the chip.
 VLSI and Chip Design
14.4

14.2.3 Scan Design and

strategy for testing has evolved to provide observability
The scan-design one of
the. registers operate in
controllability at each register. In thisscan-design,
two modes:
) Normal mode, and
(ii) Scan mode.
to form a giant shift register called
a scan
In scan mode, registers are connected
chain, which spanning the whole chip.
pulses in scan mode, all N bits of state in the system can be
o By applying N clock
scan mode gives
shifted out and new N bits of state can be shifted in. Therefore,
easy observability and controllability of every register in the system.

Scan-in Scan-in

Flop Flop Flop

Flop Flop Flop

Logic Logic
Inputs Outputs
Cloud Cloud
Flop Flop Flop

Flop Flop Flop

CLK
SCAN
Scan-out
Flop

Fig 14.2 Scan-based testing

Modern scan is based on the use of scan registers, as shown in Fig 14.2. The scan
register is a D flip-flop preceded by a multiplexer. When the SCAN signal is
deasserted, the register behaves as a conventional register and storing the data on
the D input.
 Testingg 14,5

When SCAN is asserted, the data is loaded from the SI

(Scan-In) pin, which is
connected in shift register fashion to the previous register Q.output scan
in the
chain.

For the circuit to load the scan chain, SCAN is asserted and CLK is pulsed eight
times to load the first two ranks of 4-bit registers with data

4 SCAN is deasserted and CLK is asserted for one cycle to operate the Circuit
normally with predefined inputs.

SCAN is then reasserted and CLK asserted eight times to read the stored data
out. Atthe same time, the new register conterts can be shifted in for the next test.

Testing proceeds by serially clocking the data through the scan register to the
right point in the circuit, running a single- system clock cycle and serially
clocking the data out for observation.
o In this scheme, every input to the combinational block can be controlled and
every output can be observed. Test generation for this type of test architecture
can be highly automated.

(1) Parallel Scan

Drawbacks
The serial scan becomes quite long, and the loading and unloading can dominate
t the testing time.

Toovercome the-above drawbacks, splitting the chains into smaller segments.

This can be done on amodule-by-module basis or completed automatically to
some specified scan length.

Extending this with the serial scan process is called as random access scan,
which is similar to that used inside FPGAs to load read the control RAM.

Fig 14.3 shows a two-by-two register section. Each register receives a column
(column <m>) and row (row <n>) access signal along with a row data line
(data < n >).
 VLSIand Chip Design
14.6

column <m+1>
column <m>

write
row<n+1> CLK
CLK
dala<n+1>
Ho Flop
Flop write.
column

data
row
Logio CLK
Cloud
write D

row<n> CLK
data<n>

Fiop HFiop
Customized Register

Fig 14.3 Parallel scan-basic structure

A global write signal (write) is connected to all registers. By asserting the row
and column access signals in conjunction with the write signal, any register
can be read or written in exactly the same method as a conventional RAM.

(2) Scannable Register Design

An ordinary flip-flop can be made scannable by adding a multiplexer on the
data înput, as shown in Figl4.4 (a). Fig 14.4 (b) shows a circuit design for
such a scan register using a transmission -gate multiplexer.

The setup time increases by the delay of the extra transmission gate series
in
with the input as compared to the ordinary static flip-flop.
D

Fig 14:4 (c) shows a circuit using clock gating to obtain nearly
the same setup
time as the ordinary flip-flop.

In either design, if a clock enable is used to stop

the clock to an unused
portions of the chip, care mst be taken that ¢ always toggles
during the sCan
mode.
festing 14.7
SCAN

SCAN CLK

Flop

(a) (b)

D
SCAN X

s
SI T

(c) (d)

Fig 14.4 Scannable flip-flops

14.2.4 Built -In Self -Test (BIST)
Definition of BIST

The Built-In Self-Test (BIST) relies on augmenting logic circuits to allow them
0
to carry out operations upon themselves that prove the correct operations of
the logic'circuit.i
These technique add an area to the chip for the test logic, but reduces' the test
timerequired and thus can lower the overall system cost.
One method of testing a module is to use signatire analysis or Cyclic
Redundancy Checking (CRC). Both involvès using Pseudo-Random
Sequence Generator (PRSG) to produce the input signals for. a section of.
combinational circuitry and a signature analyzer to observe the output signals.
 VLSI and Chip Design
14.8

CLK

Q{1) Q[2]
Flop Flop Flop
(a)

f(x)= 1
+x+x³
CLK

Q[oj Q[1] Q[2]

Flop Flop Flop

(b)

Fig 14.5 Pseudo-random sequence generator

A PRSG of length n is constructed from a Linear Feedback Shift Register
(LFSR), which in turn is made up of n flip-flops connected in a serial fashion, as
shown in Fig 14.5 (a).

The XOR of particular outputs are fed back to the input of the LFSR. An n-bit
LFSR will cycle through 2"
-1 states before repeating the sequence. They are
described by a characteristics polynomial indicating which bits are fed back.

* A Complete Feedback Shift Register (CFSR) is shown in Fig 14.5 (b), includes
the zero state that may be required in some test situations.

A n-bit LFSR is converted to a

n-bit CFSR by adding a n-1 input NOR gate
connected to all but the last bit.

When in state 0...01,the next state is 0..00. When in state 0...00, the next state
is 10...0. Otherwise, the sequence is the same.
Testing |14.9|

4 Alternatively, the bottom n bits of n+1 bit LFSR can be used to cycle through
all zeros state without the delay of the NOR gate.

A signature analyzer receives successive outputs of a combinational logic block

and produces a syndrome that is the function of these outputs.

The syndrome is reset to 0 and then XORed with an output on each cycle. The
syndrome isswizzled at each cycle so that a fault in one bit is unlikely to cancel
itself out.
At the end of a test sequence, the LFSR contains the syndrome that is a function
of all previous outputs. This can be compared with the correct syndrome (derived
by running a test program on the good logic) to determine whether the circuit is
good or bad.

If the syndrome contains enough bits,it is an improbable that a defective circuit

will produce the correct syndrome.

(1) BIST
of signature analysis and the scan technique creates known
The combination
as Built -In Self -Test (BIST) or Built-In Logic Block Observation
(BILBO).

The 3-bit BIST register is shown in Fig 14.6, which is a scannable, resettable
register that also can serve as a pattern generator and signature analyzer.
the mode of operation. In the reset mode (10), all the flip
C[1:0] specifies

flops are synchronously initialized to 0. In the normal mode (11), the flip
flops behave normally with their D input and Q output.

In scan mode (00), the flip-flops are configured as a 3-bit shift register
between SI and SO. In test mode (01), the register behaves as a pseudo
random sequence generator or signature analyzer.

If allthe D inputs are held LOW, the Q outputs loop through a pseudo-random
bit sequence, which can serve as an input to the combinational logic.
 VLSI and Chip Design
14.10

D[1] DI2)
D[O)

C{1]

|Q2]/ so
SI1
Jooj
D Flop
Q1].

(a)

MODE C[1] Cto]

Scan 00
Signature
PRSG Test 1

loud Analyzer
1 0
Reset
Normal 1 1

(6)

Fig 14.6 BIST () 3-bit register (b) use in a system.

If the D inputs are taken from the combinational logic output, they are.

swizzled with an existing state toproduce the syndrome.

The overall summary of BIST, initially BIST is performed by first setting the
syndrome in the output register. Then both registers are placed in the test
mode to produce the pseudo-random inputs and calculates the syndrome.
o. Finally, the syndrome is shifted out through the scan chain.

(2)Memory BIST

InMBIST scheme, multiplexers are placed on the address, data, and control
inputs for the memory to allow direct access duringtest.

During testing, a state machine uses these multiplexers to directly write a

checkerboard pattern of alternating ls and Os.
Testing |14.11|

The data is read back, checked, then the inverse pattern is also applied and
checked.

ROM testing is even simpler: the contents are read out toa signature analyzer
to produce a
syndrome.

(3) Other On-Chip Test Strategies

o On-chip speeds are usually so high tht is directly observing an internal
behavior for testing can be dificult or impossible. Designers have included
on-chip logic analyzers and oscilloscopes to deal with this problem.
Also, on-chip scopes have been used to characterize power supply noise and
clock jitter.

Analog/Digital converter testing requires real-time access to the digital output

of the ADC. Providing parallel digital test ports by reassigning pins on the
chip /O can facilitate this testing.

If this is impossible, a "capture RAM" on chip can be used to capture results

in real-time and then contents can be transferred off-chip at a slower rate for

analysis.

If both ADCS and DACS are present, a loopback strategy can then be
employed, which is shown in Fig 14.7.

Data
DAC
Test

Digital Analog
Loopback Loopback

To wrapper ADC

Fig 14.7Analog and digital loopback

 VLSI and Chip Design
14.12
can be loop back. Communication and
Both analog and digital signals
systems that can be configured as
graphics systems frequently have I/O
a an
shown. Then, add a DAC and an ADC to system to allow level of
a

analog self-test.

a Defensive Design

Providing on-chip debug circuitry involves quite a bit of imagination and

forethough in terms of what might go wrong. It is ofien called "defensive
design".

14.2.5 IDDQ Testing

4 A method of testing for bridging faults is called IDDQ test (VDD Supply current
Quiescent) or supply current monitoring.
This relies on the fact that when a CMOS logic gate is not switching, it draws no
DC current except for leakage.

When a bridging fault occurs, then for some combination of an input conditions,
a measurable DC Ipp will flow.

Testing consists of applying the normal vectors, allowing the signals to settle,
and then measuring Ipp.

As potentially only one gate is affected, the IDDQ test has to be very sensitive. In
addition, to be effective any circuits that draw DC power such as pseudo-nMOS
gates or analog circuits have to be disabled.

As the current measuring is slow, the tests must be run slower than normal,
which increases the test time.

IDDQ testing can be completed externally to the chip by measuring the current
drawn on the Vpp line or internally using specially constructed testcircuits. This
technique gives a form of indirect massive observability at the little circuit
overhead.
Testing 14.13

A As subthreshold leakage current increases, IDDQ testing ceases to be effective

because variations in subthreshold leakage exceed the currents caused by the
faults.

14.2.6 Designfor Manufacturability

4 Circuits can be optimized for manufacturability in order to increase their yield.
This can be done in a number of following different ways:

(1) Physical
At the physical level (i.e., mask level), the yield and hence the
manufacturability can be improved by reducing the effect of process defects.

The design rules for particular processes will frequently have guidelines for
the improving yield. The following list is representative

() Increase the spacing between wires wherever possible

This can reduces the chance of a defect causing a short circuit.
(ii) Increase the overlap of
layers around contacts and vias

This reduces the chance that a misalignment will cause an aberration in the
contact structure.
(iü) Increase the number of vias at wire intersections beyond one ifpossible:

This reduces the chance of a defect causing an open circuit.

Increasingly, design tools are dealing with these kinds of optimizations

automatically.

(2) Redundancy
The redundant structures can be used to compensate the defective components
on a chip.

For example, memory arrays are commonly built with extra rows. During the
manufacturing test, if one of the words is found to be defective, the memory
can be reconfigured to access the spare rovw instead.
 VLSI and Chip Design
14.14|

can be used for

Laser-cut wires or electrically programmable fuses
one or more are
configuration. Similarly, if the memory has many banks and
even under the software
found to be defective, they can be disabled, possibly
control.

(3) Power
excess current in wires, which in
The elevated power can cause failure due to
turn can cause metl migration failures.
High-power devices raises the die temperature, that degrades the device
performance and at the same time, causing device parameter shifts.
The method of dealing with this component of manufacturability is to
minimize power through the design techniques. A suitable package and heat
sink should be chosen to remove an excess heat.
(4) Process Spread
Process simulations can be carried out at different process corners. Monte
Carlo analysis can provide better modeling for process spread and can help
with centering a design within the process variations.

(5)Yield Analysis
When a chip has poor yield or will be manufacturedin high volume, dice that
fails the manufacturing test can be taken to a laboratory for yield analysis to
locate the root cause of the failure.
If particular structures are determined to many of the failures, the layout of the
structures can be redesigned.

14.3SCAN TEST
Many system defects occur at the board level, including open or shorted printed
circuit board traces and incomplete solder joints.
At the board level, "bed-of-nails" testers historically were used to test the
boards. In this type of a tester, the board-under -test is lowered onto a set of test
points (nails) that probe points of interest on the board.
Testing
|14.15|

These can be sensed (the observable points)and driven (the controllable points)
totest the complete board. At the chassis level, software programs are frequently
used to test a complete board set.

When a computer boots, it might run a memory test on the installed memory to
detect the possible faults.
The increasing complexity of boards and the movement to technologies such as
surface mount technologies, the boundary scan is used for testing chips at the
board (and system) level.
Boundary scan was originally developed by the Joint Test Access Group (JTAG)
and has become a popular standard interface for controlling BIST features as
well.
The IEEE 1149 boundary scan architecture is shown in Fig 14.8. All of the I/O
pins of cach ICon the board are connected serially in a standardized scan chain
accessed through the Test Access Port (TAP), so that every pin card can be
observed and controlled remotely through the scan chain.

Package Interconnect

D
CHIP B CHIP c

Serial Data Out

CHIPA CHIP D

/O Pad and Serial Data In

Boundary Scan

Fig 14.8 Boundary Scan Architecture

 VLSI and Chip Design
|14.16

can be connected in series to

At the board level, ICs are in standard form that
form a scan chain spanning the entire board.
Connections between ICs are tested by the scanning values into the outputs of
chips
each chip and checking that those values are received at the inputs of the
they drive.