ARUNAI ENGINEERING COLLEGE

(An Autonomous Institution)

Velu Nagar, Tiruvannamalai-606 603

EC 3561- VLSI LABORATORY

RECORD
REGULATION 2021

NAME :……………………………..
REGISTER NO :……………………………...
YEAR/SEM : III / V
ACADEMIC YEAR : 2024-2025
 ARUNAI ENGINEERING COLLEGE
(An Autonomous Institution)
Velu Nagar, Tiruvannamalai-606 603

CERTIFICATE

Certified that this is a bonafide record of work done by

NAME :
REGISTER NUMBER :
SEMESTER :
BRANCH :
YEAR :

LAB-IN-CHARGE HEAD OF THE DEPARTMENT

Submitted for the Laboratory course titled “EC3561-VLSI

LABORATORY RECORD”.

Practical Examination held on ……………

INTERNAL EXAMINER EXTERNAL EXAMINER

 TABLE OF CONTENTS

EXP. PAGE
DATE NAME OF THE EXPERIMENT
NO NO. REMARKS
1. DESIGN OF FPGA BASED CMOS BASIC
GATES
2. DESIGN OF FPGA BASED INVERTER,
BUFFER AND TRANSMISSION GATE
3. DESIGN OF HALF ADDER AND FULL
ADDER
4. DESIGN OF FPGA BASED FLIP- FLOP

5. DESIGN OF FPGA BASED RIPPLE CARRY

ADDER

DESIGN OF FPGA BASED CARRY SAVE

6. ADDER
7. DESIGN OF FPGA BASED CARRY SELECT
ADDER
8. DESIGN OF FPGA BASED 4 INPUTS AND 8
OUTPUT MULTIPLIER
9. DESIGN OF FPGA BASED UNIVERSAL SHIFT
REGISTER
DESIGN OF FPGA BASED
10. MEMORIES (ACCUMULATOR)
11. DESIGN OF FPGA BASED FINITE STATE
MACHINE
12. DESIGN OF FPGA BASED 4 BIT
SYNCHRONOUS COUNTER USING FLIPFLOP

13. DESIGN OF CMOS INVERTER USING S-EDIT

14 a. DESIGN OF COMMON SOURCE AMPLIFIER

USING S-EDIT
14 b. DESIGN OF COMMON DRAIN AMPLIFIER
USING S-EDIT
15. DESIGN AND SIMULATION OF A
DIFFERENTIAL AMPLIFIER.
MEASURE GAIN,ICMR,ANDCMRR
CIRCUIT DIAGRAM
AND GATE

OR GATE

NOT GATE

EXOR GATE

EXNOR GATE
PROGRAM
module gates(a,b, y1,y2,y3,y4,y5,y6,y7);
input a,b;
output y1,y2,y3,y4,y5,y6,y7;
assign y1=~a;
assign y2=a&b;
assign y3=a|b;
assign y4=~(a&b);
assign y5=~(a|b);
assign y6 =a^b;
assign y7=~(a^b);
endmodule

TEST BENCH
initial
begin
#100 a=0; b=0;
#100 a=0; b=1;
#100 a=1; b=0;
#100 a=1; b=1;
end
endmodule
OUTPUT
CIRCUIT DIAGRAM
INVERTER

BUFFER

TRANSMISSION GATE
PROGRAM
INVERTER
TEST BENCH
module inv(a, b); initial
input a; begin
output b; a=1'b0;
assign b=~a; #100 a=1'b1;
endmodule #100 a=1'b0;
end
endmodule
BUFFER
TEST BENCH
module buff(a, b); initial
input a; begin
output b; a=1'b0;
assign b=a; #100 a=1'b1;
endmodule #100 a=0'b0;
#100 a=1'b1;
end
endmodule
TRANSMISSION
module tr(i,s, y); GATE

input i,s; TEST BENCH

output y; initial

reg y; begin

always@(i,s) #100 i=0; s=0;

begin #100 i=1; s=1;

if(s==1) #100 i=0; s=1;

y=i; #100 i=1; s=1;

else #100 i=0; s=1;

y=1'bz; #100 i=1; s=0;
end end
endmodule endmodule
OUTPUT:
INVERTER

BUFFER

TRANSMISSION
GATE
CIRCUIT DIAGRAM

Half Adder

Truth Table

Full Adder
PROGRAM: HALF ADDER

// Module Name: HalfAddr Module

HalfAddr(sum, c_out, il, 12);

output sum;

output c_out;

input il;

input 12:

xor(sum.i1,12);

and(c_out.i1,12):

endmodule
OUTPUT :
PROGRAM: FULL ADDER:

// Module Name: FullAddr

module FullAddr(il, i2, c_in, c_out, sum);

input il;

input 12:

input c_in;

output c_out;

output sum;

wire s1.cl.c2;

xorn1(s1.1.2);

and n2(cl.i1.12);

xor n3(sum.s1.c_in);

and n4(c2.s1.c_in);

or n5(c_out,cl.c2);

endmodule
OUTPUT:
CIRCUIT DIAGRAM
SR FLIP FLOP

D FLIP FLOP

T FLIP FLOP

JK FLIP FLOP
PROGRAM:
SR FLIP FLOP
module srf(s,r,clk, q,qb);
input s,r,clk;
output q,qb;
reg q,qb; TEST BENCH:
always @(posedge clk) initial
begin begin
if(s==0 & r==1) #100 s=0; r=0; clk=0;
q=0; #100 s=0; r=0; clk=1;
else if(s==1 &r==0) #100 s=0; r=1; clk=0;
q=1; #100 s=0; r=1; clk=1;
else if(s==0 & r==0) #100 s=1; r=0; clk=0;
q=q; #100 s=1; r=0; clk=1;
else if (s==1 &r==1) #100 s=1; r=1; clk=0;
q=1'bz; #100 s=1; r=1; clk=1;
qb=~q; end
end endmodule
endmodule
D FLIP FLOP
module dff(clk,d,q,qbar);
input clk;
input d; output
q,qbar;
reg temp,q,qbar; always TEST BENCH
@(posedge clk) begin initial
if (d==0) begin
temp = 1'b0; #100 clk=0;d=0;
else #100 clk=1;d=0;
temp = 1'b1; #100 clk=0;d=0;
end #100 clk=1;d=0;
assign q = temp; #100 clk=0;d=0;
assign qbar = ~q; end
endmodule endmodule
 T FLIP FLOP
module tff(t,clk, q,qb);
input t,clk;
output q,qb;
reg qb;
reg q; TEST BENCH
initial q=0; initial begin #100
always@(posedge clk) t=0; clk=0;
begin #100 t=0; clk=1;
if(t==0) #100 t=1; clk=0;
q=q; #100 t=1; clk=1;
else #100 t=0; clk=0;
q=~q; #100 t=1; clk=1;
qb=~q; end
end endmodule
endmodule
JK FLIP FLOP
module jkflip(j, k, clk, q, z);
input j;
input k;
input clk;
output q;
TEST BENCH
output z;
reg q,z; initial
always@(posedge clk) begin
begin j=0; k=0; clk=0; #100;
if(j==0 & k==1) j=0; k=0; clk=1; #100;
q=0; j=0; k=1; clk=0; #100;
else if(j==1 & k==0)
j=0; k=1; clk=1;
q=1;
#100; j=1; k=0; clk=0;
else if(j==0 & k==0)
q=q; #100; j=1; k=0; clk=1;
else if(j==1 & k==1) #100; j=1; k=1; clk=0;
q=~q; #100; j=1; k=1; clk=1;
z=~q; end
end
endmodule
endmodule
OUTPUT
: SR FLIP FLOP

D FLIP FLOP

T FLIP FLOP

JK FLIP FLOP
CIRCUIT DIAGRAM
PROGRAM

Module ripplecarryadder(s,cout,a,b,cin);
output[7:0]s;
outputcout;
input[7:0]a,b;
inputcin;
wire c1,c2,c3,c4,c5,c6,c7;
fulladd fa0(s[0],c1,a[0],b[0],cin);
fulladd fa1(s[1],c2,a[1],b[1],c1);
fulladd fa2(s[2],c3,a[2],b[2],c2);
fulladd fa3(s[3],c4,a[3],b[3],c3);
fulladd fa4(s[4],c5,a[4],b[4],c4);
fulladd fa5(s[5],c6,a[5],b[5],c5);
fulladd fa6(s[6],c7,a[6],b[6],c6);
fulladd fa7(s[7],cout,a[7],b[7],c7);
endmodule modulefulladd(s,cout,a,b,cin);
outputs,cout;
inputa,b,cin;
wire s1,c1,c2;
xor(s1,a,b);
xor(s,s1,cin);
and(c1,a,b);
and(c2,s1,cin);
xor(cout,c2,c1);
endmodule

TEST BENCH
initial
begin
#100 a=8’b00000000; b=8’b00000000; cin=1’b0;
#100 a=8’b00001000; b=8’b00000001; cin=1’b0;
#100 a=8’b01000000; b=8’b00001000; cin=1’b0;
#100 a=8’b00001110; b=8’b01111000; cin=1’b0;
#100 a=8’b10101010; b=8’b01010100; cin=1’b1;
#100 a=8’b00010010; b=8’b11000000; cin=1’b1;
#100 a=8’b11110000; b=8’b00111100; cin=1’b1;
#100 a=8’b00001111; b=8’b11000011; cin=1’b1;
#100 a=8’b11111111; b=8’b11111111; cin=1’b1;
end
endmodule
OUTPUT
CIRCUIT DIAGRAM
PROGRAM

modulecarrysaveadder(d,a,b,e); output
[4:0]d;
input e;
input [3:0]a,b;
wire s1,s2,s3,c0,c1,c2,c3,c4,c5,c6,c7;
fulladder a1(d[0],c7,a[0],b[0],e);
fulladder a2(s3,c6,a[1],b[1],e);
fulladder a3(s2,c5,a[2],b[2],e);
fulladder a4(s1,c4,a[3],b[3],e);
fulladder a5(d[1],c3,c7,s3,e);
fulladder a6(d[2],c2,c6,c3,s2);
fulladder a7(d[3],c1,c5,s1,c2);
fulladder a8(d[4],c0,c4,c1,e);
endmodule
modulefulladder(s,c, x,y,z);
outputs,c;
inputx,y,z;
xor (s,x,y,z);
assign c = ((x & y )|(y & z)|( z & x)) ;
endmodule

TEST BENCH
initial
begin
#100 a=4’b0000; b=4’b0000; e=1’b0;
#100 a=4’b0001; b=4’b0010; e=1’b0;
#100 a=4’b1110; b=4’b0011; e=1’b0;
#100 a=4’b0110; b=4’b0101; e=1’b0;
#100 a=4’b1100; b=4’b0011; e=1’b1;
#100 a=4’b0110; b=4’b1010; e=1’b1;
#100 a=4’b1111; b=4’b1111; e=1’b1;
end
endmodule
OUTPUT
CIRCUIT DIAGRAM
PROGRAM
muxer mu1(m[1],s4,s8,c3);
module project2(s, m, x, y, z); muxer mu2(m[2],s5,s9,c3);
output [0:3]s; muxer mu3(m[3],s6,s10,c3);
output [1:5]m; muxer mu4(m[4],s7,s11,c3);
input [0:11]x; muxer mu5(m[5],c7,c11,c3);
input [0:11]y; endmodule
input z; modulefulladder (s,c,x,y,z);
wire outputs,c;
c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11 inputx,y,z;
,s4,s5,s6,s7,s8,s9,s10,s11; xor (s,x,y,z);
fulladder f1(s[0],c0,x[0],y[0],z); assign c = ((x & y) | (y & z) | (z & x));
fulladder f2(s[1],c1,x[1],y[1],c0); endmodule
fulladder f3(s[2],c2,x[2],y[2],c1); modulemuxer (m,s1,s2,c);
fulladder f4(s[3],c3,x[3],y[3],c2); output m;
fulladder f5(s4,c4,x[4],y[4],c3); input s1,s2,c;
fulladder f6(s5,c5,x[5],y[5],c4); wiref,g,h; not
fulladder f7(s6,c6,x[6],y[6],c5); (f,c);
fulladder f8(s7,c7,x[7],y[7],c6); and (g,s1,c);
fulladder f9(s8,c8,x[8],y[8],~c3); and (h,s2,f);
fulladder f10(s9,c9,x[9],y[9],c8); or (m,g,h);
fulladder endmodule
f11(s10,c10,x[10],y[10],c9);
fulladder
f12(s11,c11,x[11],y[11],c10);

TEST BENCH
initial
begin
#100 x=12’b000000000000;y=12’b000000000000; z=1’b0;
#100 x=12’b000000001111;y=12’b111110000000; z=1’b0;
#100 x=12’b000011110000;y=12’b000000011111; z=1’b0;
#100 x=12’b111100001111;y=12’b011111100000; z=1’b1;
#100 x=12’b000111001111;y=12’b111111100000; z=1’b1;
#100 x=12’b111111111111;y=12’b111111111111; z=1’b1;
end
endmodule
OUTPUT
CIRCUIT DIAGRAM
PROGRAM
Module mmmm(m,a,b); full fa7(s[7],c[7],p[8],s[3],c[2]);
input [3:0]a; full fa8(s[8],c[8],p[12],s[4],c[7]);
input [3:0]b; full fa9(s[9],c[9],p[9],s[7],c[6]);
output [7:0]m; half ha10(s[10],c[10],s[8],c[9]);
wire [15:0]p; full fa11(s[11],c[11],s[5],c[8],c[10]);
wire [12:1]s; full fa12(s[12],c[12],p[15],s[5],c[11]);
wire [12:1]c; buf(m[0],p[0]);
and(p[0],a[0],b[0]); buf(m[1],s[1]);
and(p[1],a[1],b[0]); buf(m[2],s[6]);
and(p[2],a[0],b[1]); buf(m[3],s[9]);
and(p[3],a[2],b[0]); buf(m[4],s[10]);
and(p[4],a[1],b[1]); buf(m[5],s[11]);
and(p[5],a[0],b[2]); buf(m[6],s[12]);
and(p[6],a[3],b[0]); buf(m[7],c[12]);
and(p[7],a[2],b[1]); endmodule
and(p[8],a[1],b[2]); module half(s,co,x,y);
and(p[9],a[0],b[3]); inputx,y;
and(p[10],a[3],b[1]); outputs,co;
and(p[11],a[2],b[2]); xor (s,x,y);
and(p[12],a[1],b[3]); and (co,x,y);
and(p[13],a[3],b[2]); endmodule
and(p[14],a[2],b[3]); module full(s,co,x,y,ci);
and(p[15],a[3],b[3]); inputx,y,ci;
half ha1(s[1],c[1],p[1],p[2]); outputs,co;
half ha2(s[2],c[2],p[4],p[3]); wire s1,d1,d2;
half ha3(s[3],c[3],p[7],p[6]); half ha_1(s1,d1,x,y);
full fa4(s[4],c[4],p[11],p[10],c[3]); half ha_2(s,d2,s1,ci);
full fa5(s[5],c[5],p[14],p[13],c[4]); oror_gate(co,d2,d1);
full fa6(s[6],c[6],p[5],s[2],c[1]); endmodule
TEST BENCH

initial
begin
#100 a=4’b0000; b=4’b0000;
#100 a=4’b0001; b=4’b1100;
#100 a=4’b1100; b=4’b0011;
#100 a=4’b1111; b=4’b1111;
end
endmodule
OUTPUT
CIRCUIT DIAGRAM

TABLE:
MODE CONTROL REGISTE
S1 S0 R
OPERATIO
N
0 0 NO CHANGE
0 1 SHIFT LEFT
1 0 SHIFT RIGHT
1 1 PARALLEL
LOAD
PROGRAM

module usr (O, I, clk, reset, s, SINR,

SINL); wire [3:0] w;
input [3:0] I;
input [1:0] s;
input clk;
input reset, SINR, SINL;
output [3:0] O; reg[27:0]
count = 0;
mux _4_1 m1(w[0], s[1], s[0], I[0], SINL, O[1], O[0]);
mux _4_1 m2(w[1], s[1], s[0], I[1], O[0], O[2], O[1]);
mux _4_1 m3(w[2], s[1], s[0], I[2], O[1], O[3], O[2]);
mux _4_1 m4(w[3], s[1], s[0], I[3], O[2], SINR, O[3]);
D_FF d1(O[0],w[0],clk,reset);
D_FF d2(O[1],w[1],clk,reset);
D_FF d3(O[2],w[2],clk,reset);
D_FF d4(O[3],w[3],clk,reset);
Endmodule
module D_FF(q, d, clk, reset);
output reg q;
input d, clk, reset;
always @ (posedge clk)
if (reset == 1’b1)
q<=1’b0;
else
q<=d;
endmodule
module mux_4_1(y,s1,s0,i3,i2,i1,i0);
output reg y;
input i3,i2,i1,i0;
input s1,s0;
always@(s1,s0,i3,i2,i1,i0)
begin
if(s0==0 & s1==0)
y=i0
 elseif(s0==0 & s1==1)
y=i1
elseif(s0==1 & s1==0)
y=i2
elseif(s0==1 & s1==1)
y=i3
end
endmodule

TEST BENCH
//initialize inputs
//I=4’b0000;
clk=1’b1;
reset=1’b1;
SINR=1’b1
;
SINL=1’b0
; S=2’b00;
#100 reset= 1’b1; s=2’b00;
#100 I=4’b0101; reset=2’b10;
#100 s=2’b11;
#100 s=2’b01;
#100 s=2’b10;
#100 s=2’b00;
//wait 100ns for global reset to finish
#100;
//add stimulus here
#100 I=4’b1010; reset=2’b10;
#100 s=2’b11;
#100 s=2’b01;
#100 s=2’b10;
#100 s=2’b00;
end
always #50 clk=~clk;
endmodule
OUTPUT
CIRCUIT DIAGRAM

MOORE MACHINE: STATE DIAGRAM

MEALY MACHINE: STATE DIAGRAM

PROGRAM
Moore State Machine
module moore( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedge clk, posedge rst )
begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10; end
2'b01:
begin
if( inp ) state <= 2'b11;
else state <= 2'b10; end
2'b10:
begin
if( inp ) state <= 2'b01;
else state <= 2'b11; end
2'b11:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10; end
endcase
end
end
always @(posedge clk, posedge rst)
begin
if( rst ) outp
<= 0;
 else if( state == 2'b11 )
outp <= 1;
else outp <= 0;
end endmodule

Mealy State Machine

module mealy( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedge clk, posedge rst ) begin
if( rst ) begin
state <= 2'b00;
outp <= 0;
end
else begin case(
state ) 2'b00:
begin if( inp )
begin state <=
2'b01; outp <=
0; end
else begin state
<= 2'b10; outp
<= 0;
end
end
2'b01: begin if(
inp ) begin
state <= 2'b00;
outp <= 1; end
else begin state
<= 2'b10; outp
<= 0;
end
end
2'b10: begin
if( inp ) begin
state <= 2'b01;
outp <= 0; end
else begin state
<= 2'b00; outp
<= 1;
end
end
default: begin
state <= 2'b00;
outp <= 0;
end
endcase
end
end
endmodule
OUTPUT
Moore State Machine

Mealy State Machine:

CIRCUIT DIAGRAM
PROGRAM
module accu (in, acc, clk, reset);
input [7:0] in;
input clk, reset;
output [7:0] acc;
reg [7:0] acc;
always@(clk) begin
if(reset)
acc <= 8'b00000000;
else
acc <= acc + in;
end endmodule
OUTPUT
CIRCUIT DIAGRAM
PROGRAM
module syn(m,clk, z); TEST BENCH
input m,clk; initial
output [3:0] z; begin
#100 clk=0; m=1;
reg[3:0] z;
#100 clk=1; m=1;
initial begin #100 clk=0; m=1;
z=4'b0000; #100 clk=1; m=1;
end #100 clk=0; m=1;
always@(posedge clk) #100 clk=1; m=1;
begin #100 clk=0; m=0;
#100 clk=1; m=0;
if(m==1)
#100 clk=0; m=0;
z=z+1;
#100 clk=1; m=0;
else #100 clk=0; m=0;
z=z-1; #100 clk=1; m=0;
end #100 clk=0; m=0;
endmodule #100 clk=1; m=1;
#100 clk=0; m=1;
end
endmodule
OUTPUT
SCHEMATIC DIAGRAM
OUTPUT
CIRCUIT DIAGRAM

SCHEMATIC DIAGRAM
OUTPUT
SCHEMATIC DIAGRAM
OUTPUT