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Radiant 2023-2-1 Block Based Tutorial

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Radiant 2023-2-1 Block Based Tutorial

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hemantkolipc
Copyright
© © All Rights Reserved
Available Formats
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Lattice Radiant Block-Based

Design Tutorial

November 20, 2023


Copyright
Copyright © 2023 Lattice Semiconductor Corporation. All rights reserved. This
document may not, in whole or part, be reproduced, modified, distributed, or publicly
displayed without prior written consent from Lattice Semiconductor Corporation
(“Lattice”).

Trademarks
All Lattice trademarks are as listed at www.latticesemi.com/legal. Synopsys and
Synplify Pro are trademarks of Synopsys, Inc. Aldec and Active-HDL are trademarks
of Aldec, Inc. Modelsim and Questa are trademarks or registered trademarks of
Siemens Industry Software Inc. or its subsidiaries in the United States or other
countries. All other trademarks are the property of their respective owners.

Disclaimers
NO WARRANTIES: THE INFORMATION PROVIDED IN THIS DOCUMENT IS “AS IS”
WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY KIND INCLUDING
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LIABLE FOR ANY DAMAGES WHATSOEVER (WHETHER DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, OR CONSEQUENTIAL, INCLUDING, WITHOUT
LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR
LOSS OF INFORMATION) ARISING OUT OF THE USE OF OR INABILITY TO USE
THE INFORMATION PROVIDED IN THIS DOCUMENT, EVEN IF LATTICE HAS
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LIABILITY, SOME OF THE ABOVE LIMITATIONS MAY NOT APPLY TO YOU.

Lattice may make changes to these materials, specifications, or information, or to the


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Lattice Radiant Block-Based Design Tutorial 2


Type Conventions Used in This Document
Convention Meaning or Use

Bold Items in the user interface that you select or click. Text that you type
into the user interface.

<Italic> Variables in commands, code syntax, and path names.

Ctrl+L Press the two keys at the same time.

Courier Code examples. Messages, reports, and prompts from the software.

... Omitted material in a line of code.

. Omitted lines in code and report examples.


.
.

[ ] Optional items in syntax descriptions. In bus specifications, the


brackets are required.

( ) Grouped items in syntax descriptions.

{ } Repeatable items in syntax descriptions.

| A choice between items in syntax descriptions.

Lattice Radiant Block-Based Design Tutorial 3


Contents

Lattice Radiant Block-Based Design Tutorial 5


About the Tutorial 5
About the Tutorial Data Flow 6
Task 1: Create a New Macro Project 8
Opening the Project 9
Task 2: Set Macro Region 11
Task 3: Run PAR to Complete Macro Creation 14
Task 4: Export Macro 14
Task 5: Reusing an Exported Macro 16
Summary of Accomplishments 20
Recommended References 20

Revision History 22

Lattice Radiant Block-Based Design Tutorial 4


Lattice Radiant Block-Based
Design Tutorial

The Block-Based Design (Macro) tool is used to create design blocks from
implemented module of a device family. This tutorial leads you through all the
basic steps of creating, reusing, and exporting a macro block.

A macro block is a portion of an FPGA design that can be preserved for reuse
afterwards. Some of the benefits of implementing macros in a design include
the ability to reuse blocks in other designs and the ability to design more
effectively as a team.

About the Tutorial


When you have completed this tutorial, you should be able to do the following:
 Macro Creation
 Create a Macro for your design.
 Use Physical Designer to set placement and routing physical
constraints (optional).
 Export Macro using three preservation levels:
 Logical (Logic Macro)
 Logical & Physical with Place Info (Firm Macro)
 Logic & Physical with Placement & Routing Info (Hard Macro)
 View macro .ipm package:
 <macro_name>.mac
 <macro_name>_bb.v
 <macro_name>_bb_extra.v
 <macro_name>_sim.vo

Lattice Radiant Block-Based Design Tutorial 5


About the Tutorial

 <macro_name>.mdb
 Macro Reuse
 Import macro (.ipm) package as a design source into existing or new
project for reuse.
 Loaded macro content into the design:
 Logic Macro will be included in the post-synthesis netlist.
 Firm/Physical Macro will be included in the post-MAP netlist.
 Run Place & Route to recognize macro physical constraint if it is in the
macro package.

Time to Complete

About 45 minutes.

System Requirements
 The Lattice Radiant software is required to complete the tutorial.

About the Tutorial Data Flow


The following figures illustrate the tutorial data flow of macro creation and
reuse.

Lattice Radiant Block-Based Design Tutorial 6


About the Tutorial

This diagram shows the steps for the macro creation process. First, a design
is made using a new or existing project. Then, a logical macro is created in
the Pre-Synthesis Constraint Editor, where the macro is defined. Once
changes are made in the Pre-Synthesis Constraint Editor, the defined macro
is saved in a.sdc file containing the ldc_create_macro constraint.

The next step is creating a macro region in Physical Designer (optional).


When you save your changes in Physical Designer, a .pdc file will be
generated containing the ldc_create_region constraint.

The next stage is exporting the macro using Logic, Firm, and Hard
preservation levels after macro has been defined. The macro package
generated by this export contains a number of files, including.mac, bb.v,
bb_extra.v, sim.vo, and.mdb files. These files provide the information you
need to use the macro and incorporate it into other designs or projects.

Lattice Radiant Block-Based Design Tutorial 7


Task 1: Create a New Macro Project

This diagram shows the steps for the macro reuse process. First, the macro
.ipm files are imported and the content is loaded into the design. The Post-
synthesis Logic Macro is merged into the design, ensuring that the macro
constraint is honored. A region with or without a buffer constraint can be
specified if the .pdc file exists.

In Map Design, Firm Macro is merged into the design, incorporating the post-
MAP macro design with a placement constraint. Hard Macro is also integrated
into the design with both placement & route constraints.

In Place & Route Design stage, the Logic Macro undergoes place & route with
a region constraint, while the Firm Macro goes through place & route with a
placement constraint. Finally, the Hard Macro goes through place & route with
both placement and routing constraints.

Task 1: Create a New Macro Project


We will start by launching the Radiant software.

Lattice Radiant Block-Based Design Tutorial 8


Task 1: Create a New Macro Project

Opening the Project


To create a macro instance using a new project:
1. In the Radiant software, choose File > New Project.
 If you have an existing project, steps 1 through 4 are optional. You can
proceed to step 5.
2. In the Add Source dialog box, click Add Source...
3. Browse to: <Radiant_install_path>/docs/tutorial/block_based_tutorial/
macro_create and select the top.v file.
Click Next.
4. In the Select Device dialog box, select a device family and choose the
options that you want for that device.
 The iCE40UP device is not supported.
Click Next.
5. In the Select Synthesis Tool dialog box, choose Synplify Pro.

Note:
The Lattice Synthesis Engine (LSE) tool is currently not available for macro creation.

6. Click Tools > Pre-Synthesis Constraint Editor.


Synthesize Design runs when you open the Pre-Synthesis Constraint
Editor tool.
7. Click the button in the Object Clock column to add clock constraints
(optional).
If clock constraints are added, the create_clock constraint will be shown
in the command line.

8. In Pre-Synthesis Constraint Editor, click the Macro tab.

a. Click the button in the Instance column to add shift registers.

Lattice Radiant Block-Based Design Tutorial 9


Task 1: Create a New Macro Project

In the example above, shift1, shift2, shift3, and shift4 are Instance
Names. The command is get_cells as shown in the Object Command
pane.
b. In the Macro Name column, the name is automatically set for the
macro instance.
You can also edit the name by double-clicking a cell under the Macro
Name column.
c. In the Use PIO column, you can select the ports of the module to
include the device pins inside the macro (optional).
d. In the Disable column, you can click on the checkbox if you do not
want to use the macro.

e. Click File > Save or the Save icon.


The defined macro will be saved as a synthesis constraint (.sdc) file.

Lattice Radiant Block-Based Design Tutorial 10


Task 2: Set Macro Region

You can also directly add ldc_create_macro constraint to the .sdc


file.

Note:
The default hierarchy separator for Synplify Pro is a “.” (period), while Radiant tools
use “/” (forward slash). If you create a sub-module under more than two hierarchy
levels, you need to manually add the set_hierarchy_separator {/} line or change the
separator from “/” to “.” in the .sdc file.

9. Run Synthesize Design.

Task 2: Set Macro Region


After running Synthesize Design, you can set a macro region in Physical
Designer (optional).

To create a Macro Region in Physical Designer:


1. Open Physical Designer.
2. Right-click on the floorplan layout and select the Create MACRO
REGION… option.
The mouse pointer changes from an arrow to a cross symbol.
3. Draw a rectangle around the sites where you want to place the macro.
Create New MACRO REGION... dialog box opens.

4. In the Create New MACRO REGION dialog box:

Lattice Radiant Block-Based Design Tutorial 11


Task 2: Set Macro Region

a. Enter the Macro Region Name (mandatory).


Below the Macro Region Name field, the macro resource is displayed
as a guide for the BBox size (LUTs, REGs, and EBRs).

To get an idea of what the minimum macro region size should be, you
can check the logic resource usage in the MAP Report (.mrp) file.
Calculating the region resources to compare macro resource usage is
different for each device family.
For example:
One PFU has 4 SLICEs (=8 LUTs + 8 REGs) for most devices, but 6
SLICEs (=12 LUTs + 12 REGs) per PFU for Avant.
You may also want to check non-SLICE type resource usage (e.g.,
EBR and DSP). These two blocks only appear at one out of multiple
rows, and the resources covered by region also depend on the anchor
location.
b. Enter your desired values for the Anchor and BBox fields.
You must enter a value within range.
c. In the Macro dropdown menu, you can select the predefined macro
instance from the pre-synthesis macro creation.
d. Enter your desired value for the Buffer Size field (optional).

Lattice Radiant Block-Based Design Tutorial 12


Task 2: Set Macro Region

Buffer Size gives PAR an extra room to do the routing. The routing is
confined within the macro region plus its surrounding ring. The top,
bottom, right, and left buffer size could be set differently.

Note:
The current buffer cannot be used to place and route other logic during
“reuse” if you select the “Exclusive” option.

The Buffer Size range is device density dependent. You must enter a
value within the range.
e. Click the Color option to change the color of the macro region
(optional).

5. Click OK.
6. Click the Save icon in Physical Designer.
The created macro regions are saved into a post-synthesis constraint
(.pdc) file.
The .pdc file contains the following information:
 ldc_create_region – defines the placement region.
 buffer_left/-buffer_right/-buffer_top/-buffer_bottom (optional) –
defines routing region.

7. Run Map Design


8. Click the Reports tab and expand Map Reports in the Project Summary
pane.

Lattice Radiant Block-Based Design Tutorial 13


Task 3: Run PAR to Complete Macro Creation

This section lists the macros you have created and the total number of
resources used.

Task 3: Run PAR to Complete Macro Creation


After creating a macro region in the current project, run Place & Route
Design.

If you want to import an existing .pdc file, do the following:


1. In File List view, right-click on Post-Synthesis Constraints Files folder.
2. Click Add > Existing File.
Browse to where your existing .pdc file is located and click Add.
3. Run Place & Route Design.

Task 4: Export Macro


1. Choose Tools > Export Macro
The Export Macro dialog box opens.
The macro data can be exported according to a specified preservation
level. You can also lower the preservation level of an exported macro after
importing it to a design.
 Logical (Logic Macro)
 After running Synthesize Design and Map Design, you can only
export to Logical preservation level.
 Logical & Physical with Place Info (Firm Macro)

Lattice Radiant Block-Based Design Tutorial 14


Task 4: Export Macro

 For Firm Macro, you can only export to Logical and Logical &
Physical with Place Info preservation levels after running Place
& Route Design.
 Logic & Physical with Placement & Routing Info (Hard Macro)
 After running Place & Route Design, you can export to Logical,
Logical & Physical with Place Info, and Logic & Physical with
Placement & Routing Info preservation levels.

You can also see the following fields in the Export Macro dialog box:
 Macro Name – displays the name of the selected macro from the
Macro column in the left-hand pane.
 Vendor – displays the vendor name.
 Version – displays the Macro IP version, the default is always 1.0.
 Support Radiant from Version to Version – displays the supported
maximum and minimum Radiant version. The maximum version could
be empty, but the minimum is the same as the current Radiant
version.
 Testbench File – contains testbenches that allow you to do simulation
or evaluate the macro.
 Document File – contains any document such as help, user guide, or
introduction file included in the macro.
 Other Files – additional files to be exported with the macro.
 Export to – default path where the macro package will be saved.
2. Choose the preservation level for each instance then click Export.
The exported Macros are saved as .ipm package files.
The macro .ipm package contains the following:
 <macro_name>_.mac – contains general information of the macro
project.
 <macro_name>_bb.v – synthesis header file of the macro project. It
is exported to define module interface for synthesis.
 <macro_name>_bb_extra.v – synthesis header file exported with
additional information.

Lattice Radiant Block-Based Design Tutorial 15


Task 5: Reusing an Exported Macro

 <macro_name>_sim.vo – exported for macro simulation. The file is


generated based on logic macro.
 <macro_name>.mdb – exported Macro in unified constraints
database (.udb) format. Modules representing macros will be
extracted from design and exported to .mdb files. The macro will be
the top module in .mdb file. The name specified in ldc_create_macro
constraint will be used as the name of the top module.

Task 5: Reusing an Exported Macro


To add a Macro Block file in a new project:
1. In the Radiant software, choose File > New Project.
 If you have an existing project, steps 1 through 4 are optional. You can
proceed to step 5.
2. In the Add Source dialog box, click Add Source...
a. Add the following files from the <Radiant_install_path>/docs/tutorial/
block_based_tutorial/macro_reuse directory.
 top.v
 macro_reuse.sdc
b. Click Next.
3. In the Select Device dialog box, select the following options:
 Family: CrossLink-NX (LIFCL)
 Device: LIFCL-40
Since LIFCL-40 was used to create the.ipm files in this example, it is
recommended to use this device. In this case, other devices will not work.
Click Next.
4. Select Synplify Pro as the synthesis tool.

Note:
Currently, the Lattice Synthesis Engine (LSE) tool is not available for macro reuse.

5. In the File List view, right-click Input Files.


6. Click Add > Existing File.
In the Add Existing File dialog box, browse to: <Radiant_install_path>/
docs/tutorial/block_based_tutorial/macro_reuse/impl_1
7. Select the following .ipm files:
 shiftreg1_1_0.ipm
 shiftreg2_1_0.ipm
 shiftreg3_1_0.ipm

Lattice Radiant Block-Based Design Tutorial 16


Task 5: Reusing an Exported Macro

Click Add.
8. Enable the Copy file to directory check box, then click Add.
You can see the imported .ipm files in the Input Files folder.

9. Run Synthesize Design.


The post-synthesis Logic Macro is merged into your design.
It has <macro_name>_bb.v as the input. The logic synthesis tool treats
every module that matches <macro_name>_bb.v as a black box.
10. In the File List View, you can check the Project Properties by right-
clicking the selected .ipm file to see or change their value.
You can lower the preservation level value of the imported .ipm files.
 If the imported macro’s preservation level is Firm Macro, you can
lower it to Logic Macro.
 If the imported macro’s preservation level is Hard Macro, you can
lower it to Logic and Firm Macro.

11. Run Map Design.


For Firm Macro, the post-MAP macro design with placement constraint is
merged into your design.
For Hard Macro, the post-MAP macro design with placement and route
constraint is merged into your design.

Lattice Radiant Block-Based Design Tutorial 17


Task 5: Reusing an Exported Macro

Open Physical Designer, the netlist shows the reused macro instances.
They contain information of the original region from the create stage.

12. Click the Reports tab and expand Map Reports in the Project Summary
pane.

The Design Summary section of Map Report displays the following


information:
 Total number of reused Firm and Hard macros in the design.
 Device, preservation level, anchor, and main resources.
13. You can create a macro region with the Exclusive option in Physical
Designer.
 In Physical Designer netlist, right-click on a macro instance under
the Physical folder.
 Select the Reuse macro region... option.

Lattice Radiant Block-Based Design Tutorial 18


Task 5: Reusing an Exported Macro

 The Reuse Macro Region dialog box opens.


You can only enable the Exclusive option. The text boxes are not
editable.

 In the Reuse Macro Region dialog box, do the following:


 Enter the Macro Region Name.
 Click the Exclusive checkbox and select OK.

 Click the Save icon in Physical Designer.


The created macro regions are saved into a post-synthesis constraint
(.pdc) file.
If the Exclusive checkbox is enabled, the -exclusive option is added
to the ldc_create_region command line in the .pdc file.

Lattice Radiant Block-Based Design Tutorial 19


Summary of Accomplishments

14. Run Place & Route Design.


Open Physical Designer and select Routing Mode to see the macro
instances in the physical netlist.

Summary of Accomplishments
You have completed the Lattice Radiant Block-Based Design Tutorial . In this
tutorial, you have learned how to:
 Create a macro block in Pre-Synthesis Constraint Editor.
 Create a macro region in Physical Designer
 Export Macro using three preservation levels
 Logical (Logic Macro)
 Logical & Physical with Place Info (Firm Macro)
 Logic & Physical with Placement & Routing Info (Hard Macro)
 View the macro IPM package content
 Import existing .ipm files for macro reuse.
 Change the preservation level value of .ipm files.

Recommended References
You can find additional information on the subjects covered by this tutorial in
the Radiant Help:
 Entering the Design > Block-Based Design - Using Macro Blocks >
Creating a Macro Block

Lattice Radiant Block-Based Design Tutorial 20


Recommended References

 Entering the Design > Block-Based Design - Using Macro Blocks >
Creating a Macro Region
 Entering the Design > Block-Based Design - Using Macro Blocks >
Reusing a Macro Block
 Entering the Design > Block-Based Design - Using Macro Blocks >
Exporting Macro
 Entering the Design > Block-Based Design - Using Macro Blocks > Macro
Usage Guidelines

Lattice Radiant Block-Based Design Tutorial 21


Revision History

The following table gives the revision history for this document.

Date Version Description

11/20/2023 2023.2 Updated to reflect changes in Radiant 2023.2.

6/22/2023 2023.1 Initial release.

Lattice Radiant Block-Based Design Tutorial 22

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