Scribd
Upload
14 views

Lab01 - Introduction to VHDL

Uploaded by

eng.ranaismail.business24
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
14 views

Lab01 - Introduction to VHDL

Uploaded by

eng.ranaismail.business24
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 31

Lab 01 Introduction to VHDL

Hardware Description
Language
INTRODUCTION
• VHDL was designed in 1981 to describe
the functionality of hardware systems.
• VHDL is one the two most widely used
languages for hardware synthesis.
• VHDL is different from languages like C
in that it is intended to describe
hardware.
• Execution of a VHDL program results in
a simulation of the digital system.

2
VHDL as a language
• VHDL is a powerful language with numerous language
constructs that are capable of describing very complex
behavior.
• Learning all the features of VHDL is not a simple task.
• VHDL is a strongly typed language
• Type check at compile time.
• Allows user defined types.
• Not a Case Sensitive.
• Two consecutive dashes (--) is used for comment.
Describing Hardware in VHDL
• VHDL Descriptions consist of primary design units and secondary design
units.

• The primary design units are the Entity and the Package.

• The secondary design units are the Architecture and the Package Body.

• Secondary design units are always related to a primary design unit.

4
Entity
• All designs are expressed in terms of entities.

• An entity is the most basic building block in a design.


• A VHDL entity specifies the name of the entity, the ports of the entity,
and entity-related information.
• All designs are created using one or more entities.
• A behavioral model is similar to a “black box”.

5
Entity Declaration
entity EntityName is
port ( signalName1 , {signalName2},… : PortMode Datatype;
signalName3 , {signalName4},… : PortMode Datatype);
end EntityName;

6
Entity Declaration
• An entity declaration describes the interface of the component.

• PORT clause indicates input and output ports.

• An entity can be thought of as a symbol for a component.


Port Declaration
• PORT declaration establishes the interface of the object to the outside
world.
• Three parts of the PORT declaration
• Name
• Any identifier that is not a reserved word.
• Mode
• In, Out, Inout, Buffer
• Data type
• Any declared or predefined datatype.
• Sample PORT declaration syntax:
Port Modes
• IN – signal can only be used (i.e., can only be read or can only be used
on the right-hand-side of an equation). CANNOT BE ASSIGNED TO!!
• OUT – signal value can only be written. Cannot be seen or used in the
design as it is an output and therefore external.
• INOUT – signal can be both written to (assigned to) and read (used).
• BUFFER - are used when a particular port need to be read and written.
The source of buffer port can only be internal.
9
VHDL Data Types
Predefined Data Types
• bit (‘0’ or ‘1’)
• bit_vector (array of bits)
• integer
• real
• time (physical data type)
Integer
• Integer
• Minimum range for any implementation as defined by standard: -2,147,483,647 to
2,147,483,647
• Integer assignment example
Real
• Real
• Minimum range for any implementation as defined by standard: -1.0E38 to 1.0E38
• Real assignment example
Enumerated
• Enumerated
• User defined range
• Enumerated example
Array
• Array
• Used to collect one or more elements of a similar type in a single construct.
• Elements can be any VHDL data type.
Boolean, Bit and Bit_vector
• Type boolean is (false, true);

• Type bit is (‘0’, ‘1’);

• Type bit_vector is array (integer range <>) of bit;


Char and String
• type Char is (NUL, SOH, …, DEL);
• 128 chars in VHDL’87

• 256 chars in VHDL’93

• type String is array (positive range <>) of Char;


IEEE Predefined data types
• type Std_ulogic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’);
• ‘U’ -- Uninitialized
• ‘X’ -- Forcing unknown
• ‘0’ -- Forcing zero
• ‘1’ -- Forcing one
• ‘Z’ -- High impedance
• ‘W’ -- Weak Unknown
• ‘L’ -- Weak Low
• ‘H’ -- Weak High
• ‘-’ -- Don’t care

• type std_logic is resolved std_ulogic;


• type std_logic_vector is array (integer range <>) of std_logic;
Assignments
• constant a: integer := 523;
• signal b: bit_vector(11 downto 0);

b <= “000000010010”;
b <= B”000000010010”;
b <= B”0000_0001_0010”;
b <= X”012”; -- hexadecimal
b <= O”0022”; -- Octal
Architectures
• The entity describes the interface to the VHDL model.

• The architecture describes the underlying functionality of the entity and


contains the statements that model the behavior of the entity.

• An architecture is always related to an entity and describes the behavior


of that entity.

20
Architecture Body
• Four modeling styles
• Concurrent assignments (Dataflow)
• Interconnected component (Structure)
• Sequential assignment statements (Behavior)
• Combination of the above three
architecture ArchName of EntityName is
//signals declarations
-- signal identifier : datatype [ := expression ];

begin
….
….

End ArchName;
Concurrent Vs Sequential Execution

22
Concurrent Assignments
(Dataflow)
Example (1)
Example (2)
Example (3)
Concurrent Condition
Statement
When …… else

Syntax:
signalName <= expression_1 when condition_1 else
expression_2 when condition_2 else
expression_3 ;
Example (4)

a
B
C
d
With …… select

• Syntax:
• with expression select
signalName <= expression_1 when choice_1,
expression_2 when choice_2 ,
expression_3 when others;
Example (5)

a
B
C
d

You might also like