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Lecture-28MemoryManagement2

Design management

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15 views

Lecture-28MemoryManagement2

Design management

Uploaded by

ME22B1042 THUMATI VINEELA KUMARI
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Operating Systems (CS3000)

Lecture – 20
(Memory Management – 2)

Dr. Jaishree Mayank


Assistant Professor
Department of Computer Sc. and Engg.
Memory-Allocation Scheme
• First-Fit
• Allocate the first hole that is big enough
• Next-Fit
• Allocate the next hole that is big enough from the previous allocation
• Worst-Fit
• Allocate the largest hole; must also search the entire list
• Best-Fit
• Allocate the smallest hole that is big enough; must search entire list, unless
ordered by size
Memory-Allocation Scheme
Ex: 200KB, 400KB, 150KB, 400KB

100 500 200 300 600


Limitations of Contiguous Memory Management
• Entire process needs to be in RAM
• Allocation needs to be in contiguous memory
• Fragmentation
• Limit the size of the process by RAM-size
• Management of Partitions
Modern Memory Management Schemes
Virtual Memory – Technique that allows only part of the program needs to be in
memory for execution
• Paging
• Segmentation
Paging
• Paging is a memory-management scheme
allows the physical address space of a
process to be non-contiguous.

• Divide physical memory into fixed-sized


blocks called frames

• Divide logical memory into blocks of same


size called pages

• Keep track of all free frames

• To run a program of size n pages, need to


find n free frames and load program

• Set up a page table to translate logical to


physical addresses
Address Translation Scheme
Address generated by CPU is divided into:

Page number (p) – used as an index into a page table which contains base address of each
page in physical memory

Page offset (d) – combined with base address to define the physical memory address that is
sent to the memory unit (no. Of bits required to represent the page size or word no of page)

frame number (f) – used to represent frame number which is a base address base address of
each page in physical memory

Page offset (d) – same as previously defined


Address Translation Scheme
1. LA=29 bits
2. LAS=256 KW
3. PA=33 bits
4. PAS=64MW

5. LA 13 bits, PA=12 bits, Page size 1KW


Address Translation Scheme
Example: Address Translation Scheme
Problems
1. Consider the virtual address space is 44KB. Physical address space is 24KB.
Page size=4KB. Find the (p, d) in logical and (f, d) in physical address.

2. Consider the physical memory space is 64MB and 32-bit virtual address space. Page size is 4KB,
what is the approximate size of page table?
(a) 2 MB (b) 3MB (c ) 4 MB (d) 6 MB
Problems
3. Consider the virtual address space is 32 bit.
Page size=4KB. Page table entries of 4 byte. What is the approximate size of page table size?
(a)2MB (b) 3MB (c) 4 MB (d) 8MB

4. Consider the computer system implements 40 bit virtual address and Page size is 16KB, what is
the approximate size of page table, if each page table entry is 48 bits.
(a)398MB (b) 48 MB(c) 192 MB(d) 96MB
Hardware Implementation of Page-table
Case1: Implement the page table as a set of dedicated registers

Problem: This can be used only when page table is small.

Case2:-Keep the page table in main memory and a page table base register (PTBR)
Problem:- 2 memory accesses (one for page table and one for actual byte)

Solution of Case 2
 TLB is high-speed cache memory.
 It consists of two parts : key and value
 Search is fast
 Few of the page-table entries
 When logical addresses is generated by the CPU, its page number is presented to the TLB.
 If page number is found, its frame number is easily available and used to access the memory.
 If not found in the TLB, a memory reference to the page table is made.
 After accessing, we add the page number and frame number to the TLB.
Paging With TLB
Effective Access Time
• Associative Lookup = e time unit
• Assume memory cycle time is 1 microsecond
• Hit ratio (a) – percentage of times that a page number is found in TLB;

• Effective Access Time (EAT)


EAT = a(e+m) + (e+2m)(1 – a)
Problem 1
Consider that 80-percent hit ratio means that we find the desired page number in the
TLB 80 percent of the time.
Assume it takes 20 nanoseconds to search the TLB and 100 nanoseconds to access
memory.
Find the effective memory-access time.

Sol:-
Problem 1 Solution
Consider that 80-percent hit ratio means that we find the desired page number in the
TLB 80 percent of the time.
Assume it takes 20 nanoseconds to search the TLB and 100 nanoseconds to access
memory.
Find the effective memory-access time.

Sol:-EAT= TLB hit (TLB access time+Memeory acc time)+(1-TLB hit) (TLB AT+2MAT)
=0.8(20+100)+0.2(20+200)
=96+44
= 140ns
Problem 2
If effective memory access time is given as 160ns. We assume 90-percent hit ratio
means that we find the desired page number in the TLB 90 percent of the time.
100 nanoseconds to access memory.
Find the TLB access time.

Sol:-
Problem 2
If effective memory access time is given as 160ns. We assume 90-percent hit ratio
means that we find the desired page number in the TLB 90 percent of the time.
100 nanoseconds to access memory.
Find the TLB access time.

Sol:-EAT= TLB hit (TLB access time+Memeory acc time)+(1-TLB hit) (TLB AT+2MAT)
160=0.9(T+100)+0.1(T+200)
160=1T+90+20
T= 50ns(TLB access time)
Memory Protection Using bit
Valid-invalid bit attached to each entry in the page table:
• “valid” indicates that the associated page is in the process logical address space, and is
thus a legal page
• “invalid” indicates that the page is not in the process logical address space
Shared Pages Concept
 An advantages of paging is the possibility of sharing common code.
 This is particularly important in time-sharing environment.

Shared code
• One copy of read-only (reentrant) code shared among processes (i.e., text
editors, compilers, window systems).
• Shared code must appear in same location in the logical address space of
all processes

Private code and data


• Each process keeps a separate copy of the code and data
• The pages for the private code and data can appear anywhere in the logical
address space
Example
Shared Pages Concept
• Assume 40 users using text editors
• Text editor size= 150 KB
• Data size=20 KB

• Non-Shared Memory
Total Size=6800KB

• Shared Memory
Total Size=950KB
Thank You
Any Questions?

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