DIGITAL ELECTRONICS

QUESTION AND ANSWERS (QUESTION BANK)

ONE MARK QUESTIONS [email protected]
1: What is an exclusive OR gate?
A: The logic gate whose output is high only when odd numbers of inputs are high is
known as an XOR gate.
Or: Two input XOR GATE produces a high output when both the inputs are at different
logic states
2: Draw the symbol of an XOR gate. 3:Write the Boolean equation
of XOR gate?

A:
XOR GATE

4: Write the truth table of XOR gate. 5. Draw the symbol of XNOR gate.
6Write the Boolean expression for XNOR gate.

Input Output
A B
Y= A B
0 0 0
0 1 1
1 0 1
1 1 0

7. Write the truth table of XNOR gate. 8. Name the Universal gates?
Input Output Ans. NAND gate and NOR gate are the Universal
A B gates
Y= A B
0 0 1 9. How many two input NAND gates must be
0 1 0 used to produce two input OR function?
1 0 0 Ans. 3 NAND gates are used to produce two input
1 1 1 OR gate
10. How many two input NOR gates must be used to produce two inputs OR
function?
Ans. 2 NOR gates are used to produce two input OR gate.

11. Why do we use digital codes?

• Computers and electronic devices need a systematic and precise method to read
information. This system requires each character, letter or symbol to be unique
and easily distinguishable.

• A digital code is a rule for converting analog into digital signals

12. What is a BCD code?

 Ans. BCD is a numeric code in which each digit of a decimal number is represented by a
group of four bits using 8-4-2-1 or 2-4-2-1 codes. It is expanded as Binary Coded
Decimal.
13. What is a gray code?
Ans. Gray code is a minimum change code belongs to non-weighted codes. There will be
only one bit change in gray code for the successive decimal number.
14. Which are weighted codes?
Ans. It is a code in which each bit has its own bit positional value or Weightage.
15. Which are the non-weighted codes?
 Excess-3 code and Gray code.

16. Name the self-complementing code.

 Excess-3 code.

17. Convert (1101)2 into gray code.

1  1  0  1

1 0 1 1

18. Name the alpha numeric codes.

ASCII, EBCDIC and Five bit Baudot code.
19. Expand ASCII.
American Standard Code for Information Interchange.
20. Expand EBCDIC.
 Extended Binary Coded Decimal Interchange Code.

21. How many zone bits are there in EBCDIC?

 Four zone bits.

22. WHAT IS HALF ADDER?

ANS: HALF ADDER IS a COMBINATIONAL LOGIC CIRCUIT WHICH PERFORMS ADDITION OF
TWO BITS A & B and producing TWO OUTPUTS SUM AND CARRY.
23. WHAT IS FULL ADDER?
ANS: FULL ADDER IS A COMBINATIONAL LOGIC CIRCUIT THAT PERFORMS ADDITION OF
THREE INPUTS A, B AND Cin CARRY BIT GENERATED FROM PREVIOUS ADDITION AND
PRODUCES TWO OUTPUTS SUM AND CARRY.
24. WHAT IS HALF SUBTRACTOR?
ANS. HALF SUBTRACTOR IS A COMBINATIONAL LOGIC CIRCUIT WHICH PERFORMS
SUBTRACTION OF TWO BITS NAMELY MINUEND AND SUBTRAHEND RESULTING IN TWO
OUTPUTS AS DIFFERENCE AND BORROW.
25. DRAW THE BLOCK DIAGRAM OF HALF ADDER. 26. DRAW THE BLOCK
DIAGRAMOF FULL ADDER.
 S = A  B  Cin
S=A
B

C = A.B + B.Cin
C = A.B + A.Cin
27. Write the Boolean expression for sum of half adder
Ans: =AB 29: Write the Boolean expression
for sum of full adder
28. DRAW THE BLOCK DIAGRAM OF HALF SUBTRACTOR.
Ans: S = A  B  Cin

30: write the Boolean expression

for the carry of half adder
Ans: C=A.B

31: Write the Boolean expression for the carry of full adder
Ans: C =AB+BCin+ACin
32: write the Boolean expression for the difference of half subtractor.
Answer: D = A  B
33: write the Boolean expression for borrow of a half subtractor.
Ans: Bout = A B
34. Define Min Term.
Ans. Minterm is the product (AND) term in a Canonical SOP (CSOP) which contains all the
input variables present either in compliment or uncompliment form.

35. Define Max Term.

Ans. Maxterm is the Sum (OR) term in a Canonical POS (CPOS) which contains all the
input variables present either in compliment or uncompliment form.
36. Define SOP.
Ans. The Boolean expression consists of two or more logical product (AND) terms that are
combined with OR logic (sum) is known as SOP.
37. Define POS.
Ans. The Boolean expression consists of two or more logical sum (OR) terms that are
combined with AND logic (product) is known as POS.
38. Define CPOS.
Ans. If each OR term in the POS contains all the input variables either in complement or
uncomplemented form then that POS is called canonical POS.
39. Define CSOP.
Ans. If each AND term in the SOP contains all the input variables either in complement
or uncomplemented form then that SOP is called canonical SOP.
40. what is a karnaugh map?
 Karnaugh map is a graphical method or visual display of simplification of Boolean
expression by systematic approach.

41. What is meant by looping?

Looping or grouping means grouping of adjacent cells which contains 1’s. E.g. Pair,
Quad or Octet.

42. What is a cell in a K map?

A cell in a K map is a box which represents a particular combination of variables in its
product form or minterms.
43. What is meant by redundant group?
A redundant group is a group in which all the 1’s in a group are over lapped by other
groups and has to be eliminated.
44. What is a pair?
A group of two adjacent cells containing 1 either horizontally or vertically but not
diagonally on a K map is called a pair.
45. What is a quad?
A quad is a group of four adjacent cells containing 1 in a K map. It may be as a
square or vertical cells or horizontal cells or even on the four corners of the k-map.

46. What is an octet?

Ans: An octet is a group of eight adjacent cells that contain 1 either in two rows or two
columns in K-map
47. How many variables does the pair eliminate?
Ans: One variable which appear in both compliment and uncomplimented form.
48. How man variable does quad eliminate?
Ans: Two variables which appear in both compliment and uncomplimented form.
49. How many variables does octet eliminate?
Ans: Three variables that appear in both compliment and uncomplimented form.
50. What is a don’t care condition?
Ans: An output condition that is not specified and can be either 1 or 0 without affecting
the operation of the system is called don’t care condition
51. Name the universal gate used to realize AND-OR logic?
Ans.: NAND gate
52. Name the universal gate used to realize OR-AND logic?
Ans.: NOR gate
53. What is a sequential logic circuit?
Ans. Sequential logic circuits are basic memory elements which has the capacity to store
one bit at a time. They are nothing but combinational logic circuits with feedback.
54.What is a flip flop?
Ans: The basic memory element which is used to store one bit data at a time is called as
flip flop. It has 2 inputs and 2 out puts and the outputs are compliment to each other.
55.Is the flip flop a bi-stable device
 Ans: Yes, a flip flop is a bi-stable multi vibrator which has two stable states. It can remain
in either one of the states indefinitely unless an external i/p is given to change its state.
56.Define a clock pulse?
Ans: A clock pulse is a periodic train of continuous rectangular or square pulses.

61. What is a register?

Ans: A register is a set of flip-flops used to store binary data. The storage capacity of a
register is the number of flip flops connected. I,e, for 4 bit storage we need 4 flip flops
connected together.
57 Draw the logic circuit of an unclocked SR flip-flop 58. Draw the logic
circuit of D-flip flop
Ans.

59. Draw the logic diagram of a J K flip-flop 60. Draw a diagram of a T

flip-flop

62. Which is the line used to transfer data in and out of a PISO shift register?
Ans: The shift/load input line is used to transfer the data bits in and out of a PSIO shift
register. If this line is high then the data is shifted out from one register to another
serially, if this line is low then the input data is loaded to all the flip flop.

63. What is a counter?

Ans: A group of flip flops arranged in such a way that they can be used to count the
binary numbers with the clock pulse applied is known as counter.

TWO MARK QUESTIONS

1. What is an XOR gate? Write its truth table. 2.What is an XOR gate?
Write its truth table.
A two input XOR gate is a logic gate which produces A two input XNOR gate is a logic
gate which produces
a high output when both the inputs are at different a high output when both the
inputs are at same
logic states. logic states.

Output
Input Output

A B
Y= A B
0 0 0
0 1 1
1 0 1
1 1 0
Input
3. Pin diagram of A B IC7400
4. Pin Y= A B diagram of IC7402
0 0 1
0 1 0
1 0 0
1 1 1

5. Explain the term Universal gates.

Ans: These are logic gates from which any Boolean expression including basic gates and
derived gates can be constructed.
 6. Realise XNOR gate using only NOR gate. 9. Convert gray code 1000

binary using XOR gate.

7. What is the most important characteristics of gray code? Explain.

Ans: Gray code changes by only one bit at a time from one number to the next number,
hence has a minimum change in the coding system this is the important characteristics
of gray code.
8. Distinguish between excess-3 and BCD codes.
EXCESS-3 CODE BCD CODE
• Excess-3 code is a non- • BCD code is a weighted code and
weighted code and belongs only 2421 is a self complimenting
to self complimenting code. code
• It is obtained by adding 3 to • Each decimal number is
each decimal number. represented by a separate group of
four bits using BCD code.
10. Distinguish between half adder and full adder.
Ans: Full adder is the combinational logic circuit which adds three bits (two inputs and
one carry bit generated in previous addition) and gives two outputs as sum and carry
Half adder is the combinational logic circuit which adds two bits at a time and produces
two outputs sum and carry.
14. Distinguish b/w SOP and POS equations.
Ans. SOP is the Sum (OR) of two or more product terms (AND). It is easy to realize using
NAND gates only or AND-OR logic. The logic state of SOP is high
eg. AB+BC
POS is the product (AND) of two or more sum terms (OR). It is easy to realize using NOR
gates only or OR-AND logic. The logic state of POS is low. eg.(A+B)(B+C)
11. Write the truth table and timing diagram of half adder.
Ans: Timing diagram truthtable
 Input Output
A B C= S= A
A.B
B
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
12.Write the truth table and timing diagram of full
adder.

13. Realize the full adder using two half adders and a OR gate.

15. Convert AB+C into canonical sop.

Ans. = AB[ C+C] + [ A + A] [B + B] C
= ABC + ABC+ A B C + AB C+ A B C + A B C
= ABC+ ABC + A B C + A B C +A B C

16. Convert (A+C)(B+C)

ANS. = ( A + 0 + C ) ( 0 + B + C )
= ( A + B B+ C) ( A A + B + C )
= ( A+B+C) ( A + B + C) ( A + B + C) ( A + B + C )
17. Distinguish b/w Minterm & Maxterm.
MINTERM MAXTERM
1.Minterms are the product terms in CSOP 1.Maxterms are the product terms in CPOS
which contain all the variables either in which contain all the variables either in
complement or uncompliment form and are complement or uncompliment form and are
denoted by ‘m’ denoted by ‘M’
2. logic state of the minterm high 2. logic state of maxterm is low

18. Write the Truth Table for 3 variable i/p with minterm and maxterms
designation.

19. Explain the necessity of eliminating redundant groups in K – map

Ans: A redundant group is a group in which all the 1’s are overlapped by other groups.
Redundant group has to be eliminated because it is an extra term in the simplified
expression which is not necessary.
20. Explain don’t care condition.
Ans: The input combinations for which the output is not specified are called don’t care
conditions or incompletely specified functions. The symbol used to represent don’t care
condition is ‘X’. It can be considered as 1 and include in the grouping if it results in more
simplified expression otherwise it can be treated as 0 and exclude from the grouping. But
only don’t care conditions cannot be grouped at least one cell should contain a high
output in the group.
21. Distinguish between AND-OR LOGIC and OR-AND LOGIC
AND-OR LOGIC OR-AND LOGIC
1.It is used to realize SOP expressions 1.It is used to realize POS expressions
2. It is realized using only NAND gates 2. It is realized using only NOR gates
3. All the AND gates are connected to an 3. All the OR gates are connected to an
OR gate at the output AND gate at the output
24 & 25. Draw the logic circuits for the expression AC+C USING BASIC GATES &

AB + B using NAND gates

22: Draw 4 variable K-map with min term designations 23: write the truth
table for the expression A B + AB

Input output
Y=
A B A B A B AB
A.B+AB
0 0 1 1 1 0 1
0 1 1 0 0 0 0
1 0 0 1 0 1 1
1 1 0 0 0 0 0

26. Draw the AND-OR logic circuit for the expression Y = A B + B

27. Distinguish between combinational and sequential logic circuits.

COMBINATIONAL LOGIC CIRCUIT SEQUETIONAL LOGIC CIRCUIT
 The output depends only on the  The output depends on present
present input. input as well as previous output.
 It cannot store information. i.e. it  It can store information. i.e. it is a
does not have a memory element memory element
 It does not have feedback Back  It has feedback input
input

28. Distinguish between SR and JK flip flop.

SR FLIP FLOP JK FLIP FLOP
 It is the basic flip flop which is known JK flip flop is known as universal flip
as SET – RESET flip flop flop
 It has INVALID state when  It does not have an INVALID state
S=R=Clk=1 I.e. both the outputs are instead it has Toggling state. i.e. the
 at same logic state (high) flip flop toggles from Set state to
Reset state and vice versa.
 The inputs does not have the  The inputs had feedback input
feedback input

29. What is race around condition? How is it eliminated?

when J= K=Clk =1, The UNCERTAINITY of the output of JK FF at the end of the
clock pulse is known as RACE AROUND. The race around condition can be eliminated by
using Edge triggered JK flip flop or Master slave flip flop.
30. Mention types of SHIFT REGISTERS?
Ans. The two types of SHIFT REGISTERS are 1. Serial shift register
2. parallel shift register

31. Draw logic diagram of SISO shift register?

32. Draw logic diagram of SIPO shift register?

33: Draw the logic diagram of a PISO shift register.

34: Draw the logic diagram of PIPO shift register.

35: Give a broad classification of counters.

ANS: Counters are broadly classified as: 1. Asynchronous counters: they are serial
counters
2. Synchronous counters: they are parallel
counters