CEG2136: Computer Architecture I / CEG2536: Architecture des Ordinateurs I

FINAL EXAMINATION - SAMPLES

A
Q1.1 For 1 K memory locations you need:
(a) 8 address lines
(b) 10 address lines
(c) 12 address lines
(d) None of the above

Q1.2 Which CPU register provides the

address from which the next
instruction opcode is to be fetched?
(a) Instruction register IR
(b) Accumulator AC
(c) Program counter PC
(d) None of these

Q1.4 An arithmetic unit performs basic operations on two numbers A and B, under the control
of two bits S and Cin., as shown in the following table:
S Cin = 0 Cin = 1
0 F = A + B (addition) F = A + 1 (increment A)
1 F = A - 1 (decrement A) F = A + B’+ 1 (subtraction)

The following combinational circuit (multiplexor and full adder) is used to implement the
functions described above for bit i. Select from the following combinations of multiplexor inputs
which set of logic values implements correctly the above functions

S C in

Ci (a) D0=Bi, D1=0, D2=1, D3=Bi

S1 S0
D0 Ai Xi (b) D0=0, D1=Bi, D2=Bi, D3=1
Full
Fi
D 1 MUX
4x1
Adder (c) D0=1, D1=Bi, D2=Bi, D3=0
Yi
D2 (d) D0=Bi, D1= 0, D2=1, D3=Bi’
C i+1
D3 (e) D0=1, D1=Bi, D2=Bi, D3=0
Q2
The block diagram of the basic computer that was introduced in chapter 5 of Mano’s textbook is
given in the annex, along with its instruction list. The instruction word is 16 bit long and has the
following structure …

Q2.1 At some point, the content of PC of the basic computer is 3AF (all numbers are in
hexadecimal) and the content of AC is 2EC3, as shown in the following table. The content
of memory is partially given below, as well:

MEMORY BASIC COMPUTER REGISTERS

Memory Content before Content after
Address
content instruction execution instruction execution
3AD 03B5 PC 3AF
3AE ABBA AC 2EC3
3AF 93AD AR 0000
3B0 DEED DR 0000
3B1 7BEE IR 0000
3B2 AD08 E 0
3B3 10BC I 0
3B4 1CAA SC
3B5 3B9F
3B6 3BA0

a. What is the instruction that will be fetched and executed?

b. Show the operands and the binary operation that will be performed in the AC when the
instruction is executed.

c. Fill out the last column (“Content after instruction execution”) of the above table with
the contents of registers PC, AR, DR, AC, and IR in hexadecimal and the values of E,
I and the sequence counter SC in binary, all shown at the end of the instruction cycle.

CEG 2136 Final Examination Samples _ Page 2 out of 14

Q2.2 What is the result, in decimal, of the operation performed by the following assembly
program?
ORG 100
LDA OP
CMA
INC
ADD OP1
STA OP2
HLT
OP1, 0039
OP, FFA5
OP2, 0
END

The machine code of this program is stored in a memory unit of 1 kilo-word of 16 bits
implemented on an Altera FPGA; give the Quartus .mif file that describes this program

Addr +0 +1 +2 +3 +4 +5 +6 +7
100 2107
108
110

Q4.2 You have to expand the instruction list of your textbook basic computer with three more
instructions (ASR, DIV, TAT) as shown in the following table; both circuits of the datapath
and the control unit need to be extended.

ASR F020 Arithmetic Right Shift (DR <- DR/2)

DIV F010 Divide by 4 (DR <- DR/4)
TAT F008 Swap AC with DR (DR <-> AC)
This basic computer is a simplified version of the one presented in the textbook as it does not have
any provisions to deal with interrupts.

The datapath has to be redesigned to allow your DR register to support the following operations:
 LDDR = x T4: DR <- (bus) /Transfer value from bus to DR
 INRDR = y T3 : DR <- DR+1 /Increment DR
 CLRDR = z T3: DR <- 0 /Clear DR
 SHRDR = v T3 + w T4: DR <- shr DR /Shift right DR

Design and draw the logic diagram of DRi (bit i of register DR), using any type of combinational
circuits and a JK flip-flop.

CEG 2136 Final Examination Samples _ Page 3 out of 14

Q5

Q5.1 RTL notation is used in the following table to describe the FETCH cycle of a memory reference
instruction. Give short explanations of the respective microoperations in the last column

State RTL Microoperations Explanations

T0 AR  PC

T1 IR  M [AR]

PC  PC  1

T2 D0 , D1 ,..., D7  DecodeIR(14  12)

AR  IR(11  0)

I  IR(15)

I  D7'  T3 AR  M [ AR]

CEG 2136 Final Examination Samples _ Page 4 out of 14

Q5.2a Use RTL notation to describe the EXECUTION cycle of each of the following three newly added
instructions; give the corresponding control signals in terms of the instruction code and the sequence
counter. Use as many lines for your table as you need; if needed more, please use the back of the
page.

Instr. Condition RTL Bus Select Control signals

S2, S1, S0
ASR D7IT3: DR <- shr DR SHRDR, …

TAT AC <= DR,

DR <=AC
(done simultaneously)

DIV

Q5.2b Derive the equations of the control signals from the above table:

CEG 2136 Final Examination Samples _ Page 5 out of 14

 B

Question 1

Consider the following logic diagram:

a) What is the C4, S3, S2, S1, S0 value if:

(1) Register A = 1101, Register B = 0110, and M=0
(2) Register A = 1101, Register B = 0110, and M=1
Write your calculations and results in the last two columns of the following table

A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0
M C4
(binary) (binary) (binary)

1101 0110 0

1101 0110 1

b) Given that 2’s complement representation is employed in this circuit, convert to decimal the
binary numbers in the following table:
A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0
M C4
(decimal) (decimal) (decimal)

c) Are your results correct? Explain

d) Expand your adder with a circuit that can signalize overflow

CEG 2136 Final Examination Samples _ Page 6 out of 14

Question 3
Consider the computer of Lab 4, the architecture of which is described in Figure 1 and Tables
1, 2, 3, 4, and 5. The instruction type is determined by the two most significant bits of the 8-
bit register IR, as follows:
X0 = IR(7)’ IR(6)’ denotes a memory-reference instruction (MRI) in direct addressing mode;
X1 = IR(7)’ IR(6) denotes a register-reference instruction (RRI); and
X2 = IR(7) IR(6)’ denotes a memory-reference instruction (MRI) in indirect addressing mode.
Assume that all registers are equipped with 3 control bits for loading the register (LD), increment
by 1 (INC), and reset to zero (CLR).
1. Find the list of all micro-operations which change the value of register AC.
2. Derive the logic equations or draw the logic diagram of the control circuit of AC.

Question 4

Two memory-reference instructions in the Basic Computer are to be changed to the instructions
specified in the following table.
Symbol Opcode Symbolic designation Description in words
ADM 001 Add AC to memory
BNA 011 If ( then Branch if AC is negative

In the following table, write down the necessary micro-operations (in RTL) to perform the
execution phase of each instruction. Note that the execution phase of such type of instructions
starts at T4. See figures 2 and 3 from Annex.
Note that the value in AC should not be changed by the execution of any instruction unless the
instruction specifies a change in its content. To this extent you can use TR to store the content of
AC temporary.

Symbol RTL Comments

ADM

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Question 5 (15 points)

Column (3) of the following table shows the content of a memory segment of the Basic
Computer that stores a machine language program and its operands.

Accumulator after the

Symbolic (Assembly)
Memory Memory execution of the
Operation Codes or
Address Content current instruction
operands in HEX
(hex or binary)
Binary (1) Hex (2) Binary (3) Hex (4) (5) (6)
1000 0001 0111 0111 1000 0000 0000

1000 0001 1000 0010 1000 0001 1101

1000 0001 1001 0001 1000 0001 1110

1000 0001 1010 1000 1000 0001 1111

1000 0001 1011 0011 1000 0001 1101

1000 0001 1100 0111 0000 0000 0001

1000 0001 1101 0000 0001 0010 0001

1000 0001 1110 0000 0000 0000 1111

1000 0001 1111 0000 1000 0010 0000

1000 0010 0000 0000 0001 1100 0100

1. Convert from binary to hexadecimal both the address and the memory contents (columns
(1) and (3)) and write your results in columns (2) and (4), respectively.
2. Use Table 6 from Annex to convert the machine language program (stored in the first six
memory locations) to symbolic operation codes (assembly language). Write the assembly
language instructions in the corresponding cells of column (5) of the above table. Use
hexadecimal representation for the address field of the instructions.
3. Fill out the last column (6) of the table with the content of the accumulator after the
execution of each instruction.

CEG 2136 Final Examination Samples _ Page 8 out of 14

Question 6

a) Write a subroutine (MUL) in assembly b) This part is independent of part (a).

language that multiplies two positive The coordinates of two 2-dimensional vectors (ax, ay,
numbers by a repeated addition method. For bx, by) are stored at consecutive addresses starting
example, to multiply 6 x 4, the subroutine at F01. Write an assembly language program that
evaluates the product by adding the calculates the scalar (dot) product of two 2-
multiplicand (6) four times (multiplier), i.e., dimensional vectors, assuming that all their
6+6+6+6. coordinates are positive numbers:
Write your program using instructions of the p = ax bx+ay by
Basic Computer given in the Table 6 from the Your program is stored in memory beginning with
Annex. Your subroutine should be stored in location at address 100, and it has to place the
the memory of your Basic Computer product “p” at address F00.
beginning with address A00.
To calculate partial products (ax bx and ay by), you
Before invoking your subroutine MUL, the should call subroutine MUL. Parameters have to be
calling program places: passed as follows:
 the multiplicand (6 in the above example)  memory location 9FF is used to pass a factor, say ax;
in memory location at address 9FF;  the other factor (i.e., bx) is passed to the subroutine
 the multiplier (4 in the above example) in through the accumulator;
the accumulator.  the product ax bx is passed back to your program by
The result (the product of the two numbers) is subroutine MUL through the accumulator.
passed by subroutine to the calling program
through the accumulator.
NOTE: You are allowed to use different
ways to pass parameters, but full explanations
should be provided.

CEG 2136 Final Examination Samples _ Page 9 out of 14

 ANNEX
The 8-bit Computer of Lab 4
Data[7..0] 256x 8 Memory Data[7..0]
Address [7..0] Control Unit
Sequence counter
Address register AR (SC) State Register

Program counter PC State Decoder (T)

Stop register
IR[7..0]
Instruction register( IR
Instruction Decoder
DR[7..0] (lab_controller)

Data register DR
Control Register
(Register bank)

ALU Accumulator (AC)

Control commands to
O2O1O0 counters , registers , bus
ALU select multiplexer and ALU
INPUT Address REGISTER
S2S1S0
(OUTA)
Bus select DIP switches
Data[7..0]
OUTPUT Data REGISTER 7-segment display
controllers 7-segment
OUTD
displays
Fig. 1. Block diagram of the 8-bit Computer of Lab 4

Table 1: Starting micro-operations in the instruction cycle of the 8-bit mini computer
Instant Description Notation (RTL)

Load the program counter PC in AR, and increment PC T0 : AR ← PC

T0
T0 S′ : PC ← PC + 1
Read instruction from memory and put it in the instruction register IR T1 : IR ← M [AR]
T1

This cycle is not used to allow for the new value of the instruction to propagate in the
T2 controller (nothing)

T3 If X1 => it is a register - reference instruction that will be executed now T3 X1 : execute an RRI
(RRI) instruction (Table 4)
T3 If X0 or X2 , read the memory address of the operand and place it in AR, and T3 IR(6)’ : AR ← PC
increment PC. Recall that (X0 + X2 ) = IR(6)’
T3 IR(6)’ S’ : PC ←
T4 Read memory address into AR PC + 1
T4 IR(6)’ : AR ← M
T5 If indirect addressing, read the operand address from memory location pointed to by AR [AR]
T5 X2 : AR ← M [AR]
T5 If direct addressing, don’t do anything, as the operand address is already in AR since T6 T5 X0 : (nothing)
starting Execute the memory-reference instructions (MRI) described in Table 2 (see Table 2)
from T6

CEG 2136 Final Examination Samples _ Page 10 out of 14

Table 2: Execution of a memory-reference instruction (MRI) in the 8-bit mini computer
Symbol Notation (RTL)

T6 Y0 : DR ← M [AR]
ADD Y0 = IR(6)’ IR(1) IR(0)’
T7 Y0 : AC ← AC + DR , SC ← 0
T6 Y1 : DR ← M [AR]
LDA Y1 = IR(6)’ IR(2)
T7 Y1 : AC ← DR , SC ← 0
T6 : (cycle not used to allow for the
STA Y2 = IR(6)’ IR(3) address bus to stabilize)
T7 Y2 : M [AR] ← AC , SC ← 0
BUN Y3 = IR(6)’ IR(4) T6 Y3 : PC ← AR , SC ← 0
ISZ (assuming that the T6 Y4 : DR ← M [AR]
next instruction is a T7 Y4 : DR ← DR + 1
memory-reference T8 Y4 : M [AR] ← DR
instruction, stored at 2 Y4 = IR(6)’ IR(5) T9 Y4 : if (DR = 0)S’ then (PC ← PC + 1)
memory locations T10Y4 : if (DR = 0)S’ then (PC ← PC + 1)
further down) T10 Y4 : SC ← 0
T6 Y5 : DR ← M [AR]
AND Y5 = IR(6)’ IR(1)’ IR(0)
T7 Y5 : AC ← AC ∧ DR , SC ← 0
T6 Y6 : DR ← M [AR]
SUB Y6 = IR(6)’ IR(1)’ IR(0)
T7 Y6 : AC ← AC − DR , SC ← 0

Table 3: Execution of register-reference instructions (RRI)

of the 8-bit mini computer
Symbol Notation (RTL)
CLA T3 X1 IR(0): AC ← 0
CMA T3 X1 IR(1) : AC ← AC’
ASL T3 X1 IR(2): AC ← ashl
ASR T3 X1 IR(3): AC ← ashr
INC T3 X1 IR(4): AC ←AC+1
HLT T3 X1 IR(5): S ← 1

Table 4: Table 5:
Function table of the 8-bit ALU Function table of the 8-bit bus
O2O1O0 ALU operation S2 S1 S0 Register placed on the bus
000 F = AC + DR / addition 0 0 0 Memory
0 01 F = AC – DR / subtraction 0 0 1 AR
01 0 F = ashl AC / arithmetic shift left 0 1 0 PC
011 F = ashr AC / arithmetic shift right 0 1 1 DR
100 F = AC ∧ DR / AND 1 0 0 IR
101 F = AC ∨ DR / OR 1 0 1 AC
110 F = AC’ / 1’s complement 1 1 0 OUTA
111 F = DR / transfer DR to AC 1 1 1 None

CEG 2136 Final Examination Samples _ Page 11 out of 14

 The 16-bit Basic Computer of the textbook / L'ordinateur de base 16 bits du
manuel

Fig. 2. Basic Computer registers connected to a common bus

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 Fig. 3. Principle flowchart for instruction cycle of the 16-bit Basic Computer of the textbook

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 Table 7. RTLs of the Basic Computer
Fetch R'To:
R'T1:
Decode R'T2:
Indirect D'7IT3: AR ← M[AR]
Table 6.
Interrupt: T0’T1’T2’IEN(FGI+FGO): R ← 1
Basic Computer Instructions List RT0: AR ← 0, TR ← PC
RT1: M[AR] ← TR, PC ← 0
RT2: PC←PC+1, IEN← 0, R←0,SC←0
Hex
Symbol Description Memory - reference instructions
code
AND D0T4: DR ← M[AR]
AND 0 or 8 AND M to AC D0T5: AC ← AC ^ DR, SC ← 0
ADD 1 or 9 Add M to AC, carry to ADD D1T4: DR ← M[AR]
E D1T5: AC ← AC+DR, E←Cout, SC←0
LDA 2 or A Load AC from M LDA D2T4: DR ← M[AR]
D2T5: AC ← DR, SC ← 0
STA 3 or B Store AC in M STA. D3T4: M[AR] ← AC, SC ← 0
BUN 4 or C Branch unconditionally BUN D4T4: PC ← AR, SC ← 0
to m
BSA D5T4: M[AR] ← PC, AR ← AR + 1
BSA 5 or D Save return address in m
and branch to m + 1 D5T5: PC ← AR, SC ← 0
ISZ 6 or E Increment M and skip if ISZ D6T4: DR ← M[AR]
zero D6T5: DR ← DR + 1
D6T6: M[AR] ← DR, SC ← 0
D6T6DR': PC ← PC + 1
Register - reference instructions
D7I'T3 = r (common to all RRI)
IR(i) = Bi (i = 0, 1, 2, ... , 11)
r: SC ← 0
CLA 7800 Clear AC CLA rB11: AC ← 0
CLE 7400 Clear E CLE rB10: E←0
CMA 7200 Complement AC CMA rB9: AC ← AC'
CME 7100 Complement E CME rB8: E ← E'
CIR 7080 Circulate right E,AC CIR rB7: AC←shr AC,AC(15)←E,E←AC(0)
CIL 7040 Circulate left E, AC CIL rB6: AC←shlAC,AC(0)←E,E←AC(15)
INC 7020 Increment AC, INC rB5: AC ← AC + 1
SPA 7010 Skip if AC is positive SPA rB4AC'(15): PC ← PC + 1
SNA 7008 Skip if AC is negative SNA rB3AC(15): PC ← PC + 1
SZA 7004 Skip if AC is zero SZA rB2AC': PC ← PC + 1
SZE 7002 Skip if E is zero SZE rB1E': PC ← PC + 1
HLT 7001 Halt computer HLT rB0: S←0
Input - output instructions
D7IT3 = p (common to all IOI)
INP F800 Input information and IR(i) = Bi (i = 6, 7, 8, 9, 10, 11)
clear flag p: SC ← 0
OUT F400 Output information INP pB11: AC(0-7) ← INPR, FGI ← 0
and clear flag OUT pB10: OUTR ← AC(0-7), FGO ← 0
SKI F200 Skip if input flag is on SKI pB9FGI: PC ← PC + 1
SKO F100 Skip if output flag is on SKO pB8FGO: PC ← PC + 1
ION F080 Turn interrupt on ION pB7: IEN ← 1
IOF F040 Turn interrupt off IOF pB6: IEN ← 0

CEG 2136 Final Examination Samples _ Page 14 out of 14