ENGINEERING NOTES

ON
COMPUTER ORGANIZATION
(BECC0317)
VVCE AUTONOMOUS 2022 SCHEME

MODULE 04
THE MEMORY SYSTEM

Version: 1.0
Release Date: 30th January 2024

by
MOHAMED ANEES
Assistant Professor
Department of Electronics & Communication
Vidyavardhaka College of Engineering, Mysuru
 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

TABLE OF CONTENTS

4.0 THE MEMORY SYSTEM.......................................................................................... 3

4.1 CONNECTION OF MEMORY TO THE PROCESSOR ..................................................... 3
4.2 SEMICONDUCTOR RAM MEMORIES............................................................................. 4
4.2.1 INTERNAL ORGANIZATION OF MEMORY CHIPS ................................................................ 4
4.2.2 STATIC MEMORIES .................................................................................................................... 5
4.2.2.1 STATIC RAM CELL ............................................................................................................ 5
4.2.2.2 ASYNCHRONOUS DRAM ................................................................................................. 6
4.2.2.3 SRAM V/S DRAM ............................................................................................................... 7
4.2.2.4 INTERNAL ORGANIZATION OF 2M X 8 DRAM ........................................................... 7
4.3 READ ONLY MEMORIES .................................................................................................. 8
4.3.1 ROM ............................................................................................................................................... 9
4.3.2 PROM ............................................................................................................................................. 9
4.3.3 EPROM ........................................................................................................................................ 10
4.3.4 EEPROM ...................................................................................................................................... 10
4.3.5 FLASH MEMORY ....................................................................................................................... 10
4.4 SPEED, SIZE AND COST .................................................................................................. 11
4.5 MEMORY HIERARCHY ................................................................................................... 11
4.6 CACHE MEMORY............................................................................................................. 12
4.6.1 CACHE MEMORY ...................................................................................................................... 12
4.6.2 LOCALITY OF REFERENCE..................................................................................................... 12
4.7 VIRTUAL MEMORY ORGANIZATION ......................................................................... 13

Mohamed Anees, Asst. Professor 2 Dept. of E&CE, VVCE Mysuru

 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

4.0 THE MEMORY SYSTEM

4.1 CONNECTION OF MEMORY TO THE PROCESSOR

The connection between the processor and its memory consists of address, data, and
control lines, as shown in Figure.

Fig.: Connection of the Memory to the Processor

Address Bus: The processor uses the address lines to specify the memory location.

Data Bus: The processor uses the data lines to transfer the data.

̅̅̅̅ This control line indicates read or write operation.

𝐑/𝐖:
̅ = 1, Read operation, R/W
If R/W ̅ = 0, Write operation.

Memory Address Register (MAR): The MAR holds the address of the memory
location to be accessed.

Memory Data Register (MDR): The MDR contains the data to be written into or read
out of the addressed location.

Memory Function Completed (MFC): This is the processor’s internal control signal
that indicates that the requested memory operation has been completed.

Memory Access Time: It is the time that elapses between the initiation of an operation
to transfer a word of data and the completion of that operation.

Memory Cycle Time: The minimum time delay required between the initiation of two
successive memory operations.

Mohamed Anees, Asst. Professor 3 Dept. of E&CE, VVCE Mysuru

 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

4.2 SEMICONDUCTOR RAM MEMORIES

4.2.1 INTERNAL ORGANIZATION OF MEMORY CHIPS
The internal organization of 16 x 8 memory is as shown in figure.

Fig.: Organization of bit cells in a memory chip of size 16 x 8

• CS (Chip Select) input selects a given chip in a multichip memory system. The
̅ control signal specified read or write operation.
𝐑/𝐖

• Each row of cells constitutes a memory word. All cells of a row are connected to
a common line referred to as the word line. The word line is selected by a
decoder.

• The cells in each column are connected to a Sense/Write circuit by two-bit lines,
and the Sense/Write circuits are connected to the data input/output lines of the
chip.

• During a Read operation, the Sense/Write circuits read the information stored in
the cells selected by a word line and place this information on the output data
lines.

• During a Write operation, the Sense/Write circuits receive input data and store
them in the cells of the selected word.

Mohamed Anees, Asst. Professor 4 Dept. of E&CE, VVCE Mysuru

 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

4.2.2 STATIC MEMORIES

Memories that consist of circuits capable of retaining their state as long as power is
applied are known as static memories.

4.2.2.1 STATIC RAM CELL

Figure illustrates how a Static RAM (SRAM) cell may be implemented.

Fig.: A Static RAM Cell

Two inverters are cross-connected to form a latch. The latch is connected to two-bit
lines by transistors T1 and T2. These transistors act as switches that can be opened or
closed under control of the word line.

Read Operation
▪ In order to read the state of the SRAM cell, the word line is activated to close
switches T1 and T2.
▪ ̅
If the cell is in state 1, the signal on bit line 𝒃 is high and the signal on bit line 𝒃
is low.
▪ The Sense/Write circuit at the end of the two-bit lines monitors their state and
sets the corresponding output accordingly.

Write Operation
▪ ̅,
During a Write operation, the Sense/Write circuit drives bit lines 𝒃 and 𝒃
instead of sensing their state.
▪ ̅ and
It places the appropriate value on bit line 𝒃 and its complement on 𝒃
activates the word line. This forces the cell into the corresponding state, which
the cell retains when the word line is deactivated.

Mohamed Anees, Asst. Professor 5 Dept. of E&CE, VVCE Mysuru

 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

4.2.2.2 ASYNCHRONOUS DRAM

• Information is stored in a dynamic memory cell in the form of a charge on a
capacitor. But this charge can be maintained for only tens of milliseconds.
• Since the cell is required to store information for a much longer time, its
contents must be periodically refreshed by restoring the capacitor charge to its
full value.
• An example of a dynamic memory cell that consists of a capacitor, C, and a
transistor, T, is shown in Figure.

Fig.: A Single-Transistor Dynamic Memory Cell

• To store information in this cell, transistor T is turned on and an appropriate

voltage is applied to the bit line. This causes a known amount of charge to be
stored in the capacitor.
• After the transistor is turned off, the charge remains stored in the capacitor, but
not for long. The capacitor begins to discharge. This is because the transistor
continues to conduct a tiny amount of current.
• Hence, the information stored in the cell can be retrieved correctly only if it is
read before the charge in the capacitor drops below some threshold value.
• During a Read operation, the transistor in a selected cell is turned on. A sense
amplifier connected to the bit line detects whether the charge stored in the
capacitor is above or below the threshold value. If the charge is above the
threshold, the sense amplifier drives the bit line to the full voltage representing
the logic value 1. This recharges the capacitor to full voltage of logic one.
• If the sense amplifier detects that the charge in the capacitor is below the
threshold value, it pulls the bit line to ground level to discharge the capacitor
fully.

Mohamed Anees, Asst. Professor 6 Dept. of E&CE, VVCE Mysuru

 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

4.2.2.3 SRAM V/S DRAM

Parameter SRAM Cell DRAM Cell

Single Cell

Cell Structure Each bit stored in a flip-flop latch Each bit stored as charge in a capacitor
Refresh
No refresh needed Requires periodic refresh (refresh cycle)
Requirement
Density Lower density Higher density
Power
Higher power consumption Lower power consumption
Consumption
Complexity More complex circuitry Simpler circuitry
Cost Expensive Less expensive than SRAM
Usage Cache memory, registers, small buffers Main memory (RAM) in computers

4.2.2.4 INTERNAL ORGANIZATION OF 2M X 8 DRAM

A 2-Megabit DRAM chip, configured as 512K x 8, is shown in Figure 8.7.

Fig.: Internal organization of a 2M x 8 dynamic memory chip

Mohamed Anees, Asst. Professor 7 Dept. of E&CE, VVCE Mysuru

 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

Internal Organization:
• The cells are organized in the form of a 4K x 4K array.
• The 4096 cells in each row are divided into 512 groups of 8, so that a row can
store 512 bytes of data. Therefore, 12 address bits are needed to select a row.
• Another 9 bits are needed to specify a group of 8 bits in the selected row. Thus, a
21-bit address is needed to access a byte in this memory. The high-order 12 bits
and the low-order 9 bits of the address constitute the row and column address of a
byte, respectively.

Read or Write Operation:

• Row address is applied first. When ̅̅̅̅̅̅
𝐑𝐀𝐒 = 𝟎, Row address is loaded into the
Row Address Latch . Then a read operation is initiated, in which all the cells are
read and refreshed.
• Shortly after the row address is loaded, the column address is applied and loaded
into Column Address Latch, when 𝐂𝐀𝐒 ̅̅̅̅̅̅ = 𝟎. The information in this latch is
decoded and the appropriate group of 8 Sense/Write circuits are selected.
• ̅ control signal indicates a Read operation, the output values of the
If the 𝐑/𝐖
selected circuits are transferred to the data lines, 𝐃𝟕−𝟎 .
• If the 𝐑/𝐖 ̅ control signal indicates a Write operation, the information on the
𝐃𝟕−𝟎 data lines is transferred to the selected circuits.

4.3 READ ONLY MEMORIES

• SRAM and DRAM are volatile memories. They Lose the contents when the power
is turned off. Many applications need memory devices to retain contents after the
power is turned off. For example, if the computer is turned on, the operating
system must be loaded from the disk into the memory. Hence a computer system
needs non-volatile memory.
• Non-volatile memory is read in the same manner as volatile memory.
o Separate writing process is needed to place information in this memory.
o Normal operation involves only reading of data, this type of memory is
called Read-Only memory (ROM).

Mohamed Anees, Asst. Professor 8 Dept. of E&CE, VVCE Mysuru

 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

4.3.1 ROM

Fig.: A ROM Cell

• Figure shows possible configuration for a ROM cell.

• A logic value 0 is stored in the cell if the transistor is connected to ground at point
𝑃; otherwise, a 1 is stored. The bit line is connected through a resistor to the power
supply.
• To read the state of the cell, the word line is activated. Thus, the transistor switch is
closed.
• The voltage on the bit line drops to near zero if there is connection between the
transistor and ground.
• If there is no connection to ground, the bit line remains at the high voltage,
indicating a 1.
• A sense circuit at the end of the bit line generates the proper output value.
• Data are written into a ROM when it is manufactured.

4.3.2 PROM
• PROM stands for programmable ROM. This allows the data to be loaded by a
user.
• Before it is programmed, the memory contains all 0s. The user can insert 1s at the
required locations by burning out the fuses at these locations using high-current
pulses.
• Process of inserting the data is irreversible.
• PROMs provide a faster and considerably less expensive approach because they
can be programmed directly by the user.

Mohamed Anees, Asst. Professor 9 Dept. of E&CE, VVCE Mysuru

 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

4.3.3 EPROM
• EPROM stands for Erasable Programmable Read-Only Memory. EPROM
is known for its ability to be programmed and erased multiple times, making it a
rewritable memory device.
• The programming involves applying higher-than-normal voltages to specific
memory cells, causing them to change their state.
• The erasure process involves exposing the EPROM chip to ultraviolet (UV)
light, which clears the data stored in the memory cells.
• EPROM chips have a small quartz window on the top that allows ultraviolet
light to reach the memory cells. The UV light is used during the erasure
process.
• A significant disadvantage of EPROMs is that a chip must be physically
removed from the circuit for reprogramming.

4.3.4 EEPROM
• EEPROM stands for Electrically Erasable Programmable Read-Only
Memory.
• EEPROM is programmable, allowing users to write data to it using electrical
signals. The programming process involves applying specific voltage levels to
memory cells, causing changes in their state.
• EEPROM is electrically erasable.
• EEPROM has a limited number of write-erase cycles, and repeated
programming and erasing can affect the longevity of the memory cells.

4.3.5 FLASH MEMORY

• Flash memory is a type of non-volatile computer storage that can be electrically
erased and reprogrammed.
• Flash memory can be electrically erased and reprogrammed. This process is
typically performed at the block or sector level.
• Flash memory is a solid-state storage technology, meaning it has no moving
parts. This makes it more durable and less prone to mechanical failures compared
to traditional hard disk drives.
• Flash devices have greater density. Higher capacity and low storage cost per bit.
• Power consumption of flash memory is very low, making it attractive for use in
equipment that is battery-driven.

Mohamed Anees, Asst. Professor 10 Dept. of E&CE, VVCE Mysuru

 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

4.4 SPEED, SIZE AND COST

A big challenge in the design of a computer system is to provide a sufficiently large
memory, with a reasonable speed at an affordable cost.
Static RAM:
Very fast, but expensive, because a basic SRAM cell has a complex circuit making it
impossible to pack a large number of cells onto a single chip.
Dynamic RAM:
Simpler basic cell circuits, hence, are much less expensive, but significantly slower
than SRAMs.
Magnetic disks:
Storage provided by DRAMs is higher than SRAMs but is still less than what is
necessary. Secondary storage such as magnetic disks provide a large amount of storage
but is much slower than DRAMs.

4.5 MEMORY HIERARCHY

Fig.: Memory Hierarchy

• Fastest access is to the data held in processor registers. Registers are at the top of the
memory hierarchy.
• A relatively small amount of memory can be implemented on the processor chip. This
is processor cache. Two levels of cache can be implemented. Level 1 (L1) cache is on
the processor chip. Level 2 (L2) cache is in between the main memory and
processor.
• Next level is main memory, implemented as SIMMs. Much larger, but much slower
than cache memory.
• Next level is magnetic disks. Huge amount of in expensive storage.
• Speed of memory access is critical; the idea is to bring instructions and data that will
be used in the near future as close to the processor as possible.

Mohamed Anees, Asst. Professor 11 Dept. of E&CE, VVCE Mysuru

 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

4.6 CACHE MEMORY

4.6.1 CACHE MEMORY
Processor is much faster than the main memory. As a result, the processor has to
spend much of its time waiting while instructions and data are being fetched from the
main memory. Speed of the main memory cannot be increased beyond a certain point.
Cache memory is an architectural arrangement which makes the main memory
appear faster to the processor than it really is.

4.6.2 LOCALITY OF REFERENCE

• Cache memory is based on the property of computer programs known as
“LOCALITY OF REFERENCE”.
• Analysis of programs indicates that many instructions in localized areas of a program
are executed repeatedly during some period of time, while the others are accessed
relatively less frequently. These instructions may be the ones in a loop, nested loop
or few functions calling each other repeatedly. This is called “Locality of
Reference”.
o Temporal locality of reference: Recently executed instruction is likely to be
executed again very soon.
o Spatial locality of reference: Instructions with addresses close to a recent
instruction are likely to be executed soon.

Fig.: Use of a cache memory

• The processor issues a Read request, a block of words is transferred from the main
memory to the cache, one word at a time. Subsequent references to the data in this
block of words are found in the cache. At any given time, only some blocks in the
main memory are held in the cache. Which blocks in the main memory are in the
cache is determined by a “Mapping Function”.
• When the cache is full, and a block of words needs to be transferred from the main
memory, some block of words in the cache must be replaced. This is determined by a
“Replacement Algorithm”.

Mohamed Anees, Asst. Professor 12 Dept. of E&CE, VVCE Mysuru

 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

4.7 VIRTUAL MEMORY ORGANIZATION

Fig.: Virtual Memory Organization

• Techniques that automatically move program and data into the physical main memory
when they are required for execution are called virtual memory techniques. The binary
addresses that the processor issues are called virtual or logical addresses.
• A special hardware unit, called the Memory management unit (MMU) translates
virtual addresses into physical addresses.
• When the desired data or instructions are in the main memory they are fetched and
executed.
• If the data are not in the main memory, the MMU causes the operating system to bring
the data into the main memory from the disk. Transfer of data between the disk and the
main memory is performed using the DMA scheme.
• MMU causes the operating system to bring the data from the secondary storage into the
main memory.

Mohamed Anees, Asst. Professor 13 Dept. of E&CE, VVCE Mysuru

 ENGINEERING NOTES / COMPUTER ORGANIZATION / BECCO317 / MODULE 04

Q. CO &
Question Marks
No. BL

01 With neat diagram, explain the connection of the memory to CO1, L2 05

the processor.
Explain the following with respect to memory.
(a) 𝑅/𝑊̅ signal
02 (b) MFC Signal CO1, L2 05
(c) Block transfer
(d) Memory access time
(e) Memory cycle time
03 Briefly explain read and write operation of the SRAM cell. CO1, L2 05
04 Briefly explain CMOS memory cell. CO1, L2 05

05 With neat diagram, explain a single transistor dynamic CO1, L2 05

memory cell.
06 Explain cache memory. CO1, L2 05
07 With a neat diagram, explain virtual memory organization. CO1, L2 05

08 Sketch the memory representation and block diagram for CO2, L3 05

4KB x 8 RAM
09 Sketch the organization of bit cells in a memory chip CO2, L3 05
consisting of 16 words of 8 bits each.
10 Compare SRAM and DRAM cell. CO2, L3 05

11 With a neat diagram explain the internal organization of a CO2, L3 05

2Mx8 dynamic memory chip.
12 With neat diagram explain read or write operation with CO2, L3 05
respect to 2Mx8 dynamic memory chip.
13 Compare various read only memories. CO2, L3 05

Mohamed Anees, Asst. Professor 14 Dept. of E&CE, VVCE Mysuru