Unit - 3 Central processing

The computer's central processing unit (CPU) is the portion of a computer that
retrieves and executes instructions. The control unit controls all CPU operations,
including ALU operations, the movement of data within the CPU, and the exchange
of data and control signals across external interfaces (system bus).
3.1 Processor organization
The ALU does the actual computation or processing of data. The control unit
controls the movement of data and instructions into and out of the processor and
controls the operation of the ALU
Internal Structure of CPU
Figure below depicts is a slightly more detailed view of the processor.

Fig: Internal structure of CPU

The data transfer and logic control paths are indicated, including an element labeled
internal processor bus. This element is needed to transfer data between the various
registers and the ALU because the ALU in fact operates only on data in the internal
processor memory. The figure also shows typical basic elements of the ALU.
In both cases (the internal structure of the computer as a whole and the internal
structure of the processor), there is a small collection of major elements (computer:
processor, I/O, memory; processor: control unit, ALU, registers) connected by data
paths.
3.2 General Register Organization
A set of flip-flops forms a register. A register is a unique high-speed storage area in
the CPU. They include combinational circuits that implement data processing. The
information is always defined in a register before processing. The registers speed up
the implementation of programs.
Registers implement two important functions in the CPU operation are as follows –
 It can support a temporary storage location for data. This supports the directly
implementing programs to have fast access to the data if required.
 It can save the status of the CPU and data about the directly implementing
program.

Example − Address of the next program instruction, signals get from the
external devices and error messages, and including different data is saved in
the registers.

If a CPU includes some registers, therefore a common bus can link these
registers. A general organization of seven CPU registers is displayed in the
figure.

Fig: General Register Organization

 The CPU bus system is managed by the control unit. The control unit explicit
the data flow through the ALU by choosing the function of the ALU and
components of the system.
Consider R2 ← R1 + R3, the following are the functions implemented within
the CPU –
MUX A Selector (SELA) − It can place R1 into bus A.
MUX B Selector (SELB) − It can place R3 into bus B.
ALU Operation Selector (SELOPR) − It can select the arithmetic
addition (ADD).
Decoder Destination Selector (SELD) − It can transfer the result into R2.

The multiplexers of 3-state gates are performed with the buses. The state of 14 binary
selection inputs determines the control word. The 14-bit control word defines a
micro-operation.

 Control Word

Control word is defined as a word whose individual bits represent the various
control signal. Therefore, each of the control steps in the control sequence of
an instruction defines a unique combination of 0s and 1s in the CW. The
control words related to an instructions are stored in microprogram memory.

It consists of four fields SELA, SELB and SELD or SELREG contains three
bit each and SELOPR field contains four bits thus the total bits in the control
word are 13-bits.

 The three bit of SELA select a source registers of the A input of the
ALU.
 The three bits of SELB select a source registers of the B input of the
ALU.
 The three bits of SELD or SELREG select a destination register using
the decoder.
 The four bits of SELOPR select the operation to be performed by ALU.
 Control word for operation R2=R1+R3

Control Word for Micro Operation (Stored in Control Memory)

 Stack Organization

Stack is also known as the Last in First Out (LIFO) list. It is the most important
feature in the CPU. It saves data such that the element stored last is retrieved
first. A stack is a memory unit with an address register. This register
influences the address for the stack, which is known as Stack Pointer (SP).
The stack pointer continually influences the address of the element that is
located at the top of the stack.
It can insert an element into or delete an element from the stack. The insertion
operation is known as push operation and the deletion operation is known as
pop operation. In a computer stack, these operations are simulated by
incrementing or decrementing the SP register.
There are two operations in Stack
 Push – Insert an item on the top of the stack.
 Pop – Deletes an item on the top of the stack.

a) Register Stack

The stack can be arranged as a set of memory words or registers. Consider

a 64-word register stack arranged as displayed in the figure. The stack
pointer register includes a binary number, which is the address of the
element present at the top of the stack. The three-element A, B, and C are
located in the stack.

The element C is at the top of the stack and the stack pointer holds the
address of C that is 3. The top element is popped from the stack through
reading memory word at address 3 and decrementing the stack pointer by
1. Then, B is at the top of the stack and the SP holds the address of B that
is 2. It can insert a new word, the stack is pushed by incrementing the stack
pointer by 1 and inserting a word in that incremented location.

Fig: Register Stack Organization

The stack pointer includes 6 bits, because 26 = 64, and the SP cannot
exceed 63 (111111 in binary). After all, if 63 is incremented by 1, therefore
the result is 0(111111 + 1 = 1000000). SP holds only the six least
significant bits. If 000000 is decremented by 1 thus the result is 111111 .

Therefore, when the stack is full, the one-bit register ‘FULL’ is set to 1. If
the stack is null, then the one-bit register ‘EMPTY’ is set to 1. The data
register DR holds the binary information which is composed into or
readout of the stack.

First, the SP is set to 0, EMPTY is set to 1, and FULL is set to 0. Now, as

the stack is not full (FULL = 0), a new element is inserted using the push
operation.
 b) Memory Stack

A stack can be implemented in a random access memory (RAM) attached

to a CPU. The implementation of a stack in the CPU is done by assigning
a portion of memory to a stack operation and using a processor register as
a stack pointer. The starting memory location of the stack is specified by
the processor register as stack pointer.

 Instruction Format

Computer perform task on the basis of instruction provided. An instruction in

computer comprises of groups called fields. These field contains different
information as for computers everything is in 0 and 1 so each field has
different significance on the basis of which a CPU decide what so perform.

On the basis of number of address instruction are classified as:

Note that we will use X = (A+B) *(C+D) expression to showcase the
procedure.

i. Zero address instruction

A stack based computer do not use address field in instruction. To

evaluate an expression first it is converted to revere Polish Notation i.e.
Post fix Notation
Expression: X = (A+B)*(C+D)
Post fixed: X = AB+CD+*
TOP means top of stack
M[X] is any memory location

opcode mode

e.g.

PUSH A TOP = A

PUSH B TOP = B
 ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

ii. One address instruction

This use a implied ACCUMULATOR register for data manipulation.

One operand is in accumulator and other is in register or memory
location. Implied means that the CPU already know that one operand is
in accumulator so there is no need to specify it.

opcode Operand/address of operand mode

Expression: X = (A+B) *(C+D)

AC is accumulator
M [] is any memory location
M[T] is temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]

STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]
 STORE X M[X] = AC

iii. Two address instruction

This is common in commercial computers. Here two address can be

specified in the instruction. Unlike earlier in one address instruction the
result was stored in accumulator here result can be stored at different
location rather than just accumulator, but require more number of bit to
represent address.

opcode Destination Address Source Address Mode

Here destination address can also contain operand.

Expression: X = (A+B) *(C+D)

R1, R2 are registers
M [] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = C

ADD R2, D R2 = R2 + D

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

iv. Three address instruction

This has three address field to specify a register or a memory location.

Program created are much short in size but number of bits per
instruction increase. These instructions make creation of program much
easier but it does not mean that program will run much faster because
 now instruction only contain more information but each micro
operation (changing content of register, loading address in address bus
etc.) will be performed in one cycle only.

opcode Destination Source Source Mode

address Address Address

Expression: X = (A+B) *(C+D)

R1, R2 are registers
M [] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

 Addressing modes
The operands of the instructions can be located either in the main memory or
in the CPU registers. If the operand is placed in the main memory, then the
instruction provides the location address in the operand field. Many methods
are followed to specify the operand address. The different methods/modes for
specifying the operand address in the instructions are known as addressing
modes.
Different types of addressing mode

1. Immediate addressing mode

In immediate addressing mode the operand value is present in the
instruction.
Operand = A
2. Register addressing mode

 Every instruction includes operands; the operands can be a

memory location, a processor register or an I/O device. The
instruction which uses processor registers to represent operands
is the instruction in register addressing mode.

Here, the effective address is a register where the value of the

operand is present.
EA=R
Below we have two instructions as our examples for register
addressing mode.
Add R4, R3
Load R3, R2

 In the examples above, the Add instruction uses registers to

represent both of its operands. Similarly, the Load instruction
also uses registers to represent both of its operands. So, the
instruction above uses register addressing mode to describe the
address of the operand. Below, we have a figure showing the Add
instruction in the example above.
 Fig: Register Addressing mode

3. Direct addressing mode

 The direct addressing mode is also known as Absolute

Addressing mode. Here, the instruction contains the address of
the location in memory where the value of the operand is stored.

Here, the effective address is the address of memory location.

EA=A
For example, observe the examples below:
Add R2, A
Store R2, B

 The Add instruction includes the memory location A which has

the value to be added to the content of register R2. Similarly, the
Store instruction has the address of memory location B where the
content of register R2 will be stored. Below we have a figure
showing the direct addressing of the operand A in the Add
instruction of the example above.
 Fig: Direct Addressing Mode

4. Indirect addressing mode

In indirect addressing mode the address field refer to the address of
a word in memory, which contains a full-length address of the
operand.

Fig: Indirect Addressing mode

5. Register indirect addressing mode

Register indirect addressing mode is similar to indirect addressing
mode. The only difference is that the address field refers to a register
than a main memory.
 Fig: Register indirect addressing mode

3.3 Data Transfer and Manipulation

 Data transfer instruction

Data transfer instructions transfer the data between memory and processor
registers, processor registers, and I/O devices, and from one processor register
to another. There are eight commonly used data transfer instructions. Each
instruction is represented by a mnemonic symbol.

Different Data transfer instructions and their Symbol:

Name Mnemonic Symbol

Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

 The load instruction is used to transfer data from the memory to

a processor register, which is usually an accumulator.
  The store instruction transfers data from processor registers to
memory.
 The move instruction transfers data from processor register to
memory or memory to processor register or between processor
registers itself.
 The exchange instruction swaps information either between two
registers or between a register and a memory word.
 The input instruction transfers data between the processor
register and the input terminal.
 The output instruction transfers data between the processor
register and the output terminal.
 The push and pop instructions transfer data between a processor
register and memory stack.

 Data manipulation instruction

Data manipulation instructions perform operations on data and provide the
computational capabilities for the computer. The data manipulation
instructions in a typical computer usually divided into three basic types as
follows.
 Arithmetic Instruction
 Logical and bit manipulation instruction
 Shift instruction
 Arithmetic instruction
Arithmetic operations include addition, subtraction, multiplication, and
division. Some computers provide instructions only for addition and
subtraction operations and generate multiplication and division operations
from these two operations. Each instruction is represented by a mnemonic
symbol.
Different Arithmetic Instruction and their symbol

Name Mnemonic
Increment INC
Decrement DEC
Add ADD
Subtract SUB
Multiply MUL
Divide DIV
Add with carry ADDC
Subtract with borrow SUBB
Negative(2’s Complement) NEG
  The increment instruction adds 1 to the value stored in the register or
memory word.
 The decrement instruction subtracts 1 from the contents stored in the
register or memory word.
 The add instruction add content of register to the accumulator
 The subtract instruction subtracts the content of AC and store the results
in AC.
 The Multiply instruction multiply the contents of register with the
contents of the AC and store the result in the accumulator
 The divide instruction divides the contents of register with the contents
of the AC and store the quotient in the AC.
 Add with Carry instruction add the contents of register and the carry
flag with the contents of the accumulator and store the result in the AC.
 Subtract with borrow instruction subtract the contents of register and
the carry flag from the contents of the accumulator and store the result
in the AC
 Negative instruction negates a value by finding 2’s complement of its
single operand.

 Logical and bit manipulation instruction

Logical instructions perform binary operations on strings of bits stored in
registers. They are useful for manipulating individual bits or a group of bits.

Different Logical and bit manipulation name and their symbol:

Name Mnemonics
Clear CLR
Complement COM
AND AND
OR OR
Exclusive-OR XOR
Clear Carry CLRC
Set Carry SETC
Complement Carry COMC
Enable interrupt EI
Disable Interrupt DI

 The clear instruction replaces the specific operand with 0’s.

 The complement instruction inverts all the bits of the operand and produces
1’s complement.
  The AND, OR, and XOR instructions perform logical operations on each bit
or group of bits of the operand.
 The Clear carry instruction sets carry flag to 0.
 The Set Carry instruction sets carry flag to 1.
 The Complement Carry instruction complements the Carry flag.
 The Enable interrupt instruction enables the interrupt.
 The Disable interrupt instruction Disables the interrupt.

 Shift instruction

Shifts are operations in which the bits of a word are moved to the left or right.
Shift instructions may specify either logical shifts, arithmetic shifts, or rotate-
type operations.

Different shift instructions and their symbol:

Name Mnemonic
Logical Shift Right SHR
Logical Shift Left SHL
Arithmetic shift Right SHRA
Arithmetic shift Left SHLA
Rotate Right ROR
Rotate Left ROL
Rotate Right Through Carry RORC
Rotate Left Through Carry ROLC

3.4 Program Control

Data transfer and manipulation instructions specify the conditions for data
processing operations, whereas the program control instructions specify the
conditions that can alter the content of the program counter.
The change in the content of the program counter can cause an interrupt/break in the
instruction execution. However, the program control instructions control the flow of
program execution and are capable of branching to different program segments.
 Status bit Conditions
The status register comprises the status bits. The bits of the status register are
modified according to the operations performed in the ALU. The figure
displays a block diagram of an 8-bit ALU with a 4-bit status register.
 Fig: Status Register Bit

Status bit Conditions Condition Code or Flag Bits

Carry (C) 1 if end carry c8 is 1
Sign ( S) 1 if MSB F7 is 1
Zero (Z) 1 if output of ALU Contains all 0’s
Overflow (V) 1 if exclusive-OR of last two carry is 1

 The result of the 8-bit ALU operation is either 127 or -127.

 Z is a status bit used to indicate the result obtained after comparing A
and B. Here, the XOR operation is used to compare two numbers (Z =
0 if A = B).
 Conditional Branch Instructions

The conditional branch instruction checks the conditions for branching using
the status bits. Some of the commonly used conditional branch instructions
are shown in the table.

Mnemonic Condition Tested Condition

BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if not carry C=0
 BP Branch if plus S=0
BM Branch if Minus S=1
BV Branch if overflow V=1
BNV Branch if not overflow V=0
Unsigned Compare Condition (A-B)
BHI Branch if higher A>B
BHE Branch if higher or equal A≥B
BLO Branch if lower A<B
BLOE Branch if lower or equal A≤B
BE Branch if equal A=B
BNE Branch if not equal A≠B
Signed Compare Condition (A-B)
BGT Branch if greater than A>B
BGE Branch if greater or equal A≥B
BLT Branch if less than A<B
BLE Branch if less or equal A≤B
BE Branch if equal A=B
BNE Branch if not equal A≠B

 When the status condition is true, the program control is transferred to

the address specified in the instruction, otherwise, the control continues
with the instructions that are in the subsequent locations. The
conditional instructions are also associated with the program control
instructions such as jump, call, or return.
 The zero status bit checks if the result of the ALU is zero or not. The
carry bit checks if the most significant bit position of the ALU has a
carryout. It is also used with rotate instruction to check whether or not
the bit is shifted from the end position of a register into a carry position.
 The sign bit indicates the state of the most significant bit of the output
from the ALU (S = 0 denotes positive sign and S = 1 denotes negative
sign). The branch if plus and branch if minus is used to check whether
the value of the most significant bit represents a sign or not. The
overflow and underflow instructions are used in conjunction with
arithmetic operations performed on signed numbers.
 Subroutine call and Return
A subroutine is self-contained sequence of instructions that perform a given
computational task.
During the execution of a program a subroutine may be called to perform its
function many times at various points.
 The subroutine may return a computed value to its caller or provide various
result value or output parameters.

A subroutine call may also have side effects such as modifying data structure
in computer memory reading from or writing to the peripheral device, creating
a file, halting the program or a machine or even delaying the program’s
execution for a specified timeout.

 Program interrupt
 Interrupt is a signal emitted by hardware or software when a process or
an event needs immediate attention. It alerts the processor to a high-
priority process requiring interruption of the current working process.
In I/O devices one of the bus control lines is dedicated for this purpose
and is called the Interrupt Service Routine (ISR).
 When a device raises an interrupt at let’s say process i, the processor
first completes the execution of instruction i. Then it loads the Program
Counter (PC) with the address of the first instruction of the ISR. Before
loading the Program Counter with the address, the address of the
interrupted instruction is moved to a temporary location. Therefore,
after handling the interrupt the processor can continue with process
i+1.
 While the processor is handling the interrupts, it must inform the device
that its request has been recognized so that it stops sending the interrupt
request signal. Also, saving the registers so that the interrupted process
can be restored in the future, increases the delay between the time an
interrupt is received and the start of the execution of the ISR. This is
called Interrupt Latency.
 Fig: Transfer control via interrupts

 Types of interrupt
There are three major types of interrupts that are as follows

1) Hardware interrupts
If the signal for the processor is from external device or hardware is
called hardware interrupts. Example: from keyboard we will press the
key to do some action this pressing of key in keyboard will generate a
signal which is given to the processor to do action, such interrupts are
called hardware interrupts.
There are two types of hardware interrupt
 Maskable Interrupt: The hardware interrupts which can be
delayed when a much highest priority interrupt has occurred to
the processor.
 Non Maskable Interrupt: The hardware which cannot be
delayed and should process by the processor immediately.

2) Software interrupts
A software interrupt is initiated by executing an instruction. A software
interrupt is a special call instruction that behaves like an interrupt rather
than a subroutine call. It can be used by the programmer to initiate an
interrupt procedure at any desired point in the program.
There are two types of software interrupts i.e. Normal Interrupts and
Exception.
3.5 Reduced Instruction Set Computer (RISC)
RISC (reduced instruction set computer) is a microprocessor that is designed to
perform a smaller number of types of computer instructions so that it can operate at
a higher speed. Since each instruction type that a computer must perform requires
additional transistors and circuitry, a larger list or set of computer instructions tends
to make the microprocessor more complicated and slower in operation.
 CISC Characteristics

The CISC Stands for Complex Instruction Set Computer, developed by the
Intel. It has a large collection of complex instructions that range from simple
to very complex and specialized in the assembly language level, which takes
a long time to execute the instructions. So, CISC approaches reducing the
number of instruction on each program and ignoring the number of cycles per
instruction. It emphasizes to build complex instructions directly in the
hardware because the hardware is always faster than software. However,
CISC chips are relatively slower as compared to RISC chips but use little
instruction than RISC. Examples of CISC processors are VAX, AMD, Intel
x86 and the System/360.

Characteristics of CISC:
 Complex instruction, hence complex instruction decoding.
 Instructions are larger than one-word size.
 Instruction may take more than a single clock cycle to get executed.
 Less number of general-purpose registers as operation get performed in
memory itself.
 Complex Addressing Modes.
 More Data types.

Fig: CISC Architecture

 RISC Characteristics

RISC stands for Reduced Instruction Set Computer Processor, a

microprocessor architecture with a simple collection and highly customized
set of instructions. It is built to minimize the instruction execution time by
optimizing and limiting the number of instructions. It means each instruction
cycle requires only one clock cycle, and each cycle contains three parameters:
fetch, decode and execute. The RISC processor is also used to perform various
complex instructions by combining them into simpler ones. RISC chips
require several transistors, making it cheaper to design and reduce the
execution time for instruction.

Example of RISC: ARM, PA-RISC, Power Architecture, Alpha, AVR, ARC

and the SPARC.
Characteristics of RISC:
 Simpler instruction, hence simple instruction decoding.
 Instruction comes undersize of one word.
 Instruction takes a single clock cycle to get executed.
 More general-purpose registers.
 Simple Addressing Modes.
 Less Data types.
 Pipeline can be achieved.

Fig: RISC Architecture