Bipolar IC

FA5304AP(S)/FA5305AP(S) For Switching Power Supply Control

FA5304AP(S)/FA5305AP(S)

■ Description ■ Dimensions, mm
The FA5304AP(S) and FA5305AP(S) are bipolar ICs for
switching power supply control and can directly drive a power Á SOP-8
8 5
MOSFET. These ICs contain many functions in a small 8-pin
package. With these ICs, a high-performance power supply
can be created compactly because not many external

8.2±0.3
5.3
components are needed.

■ Features 1 4
• Drive circuit for connecting a power MOS-FET (IO = ±1.5A) 6.05
• Wide operating frequency range (5 to 600kHz)

–0.05
+0.1
• Pulse-by-pulse overcurrent limiting function

2.0max
0.20
Positive voltage detection: FA5304AP(S)
Negative voltage detection: FA5305AP(S)

°
• Overload cutoff function (Latch or non-protection mode

0~10
0.4±0.1 1.27±0.2 0.6
selectable)
• Output ON/OFF control function by external signals
• Overvoltage cutoff function in latch mode
• Undervoltage malfunction prevention function (ON at 16V Á DIP-8
8 5
and OFF at 8.7V)
• Error amplifier for control by tertiary winding detection
• Low standby current (90µA typ.)

6.5
• 8-pin package (DIP/SOP)

1 4
■ Applications 9.3
• Switching power supply for general equipment 1.5

3.0min 4.5max
3.4
+0.1 5
–0.0
0.3
7.6
2.54±0.25 0.5±0.1 0~15 5˚
˚ 0~1

c t .
o d u
p r
ed
i n u
n t
s c o
Di

7
FA5304AP(S)/FA5305AP(S)

■ Block diagram
Á FA5304AP(S)

Pin Pin Description

No. symbol
1 IN (–) Inverting input to error amplifier
2 FB Error amplifier output
3 IS (+) Overcurrent (+) detection
4 GND Ground
5 OUT Output
6 VCC Power supply
7 CT Oscillator timing capacitor
8 CS Soft-start and ON/OFF control

Á FA5305AP(S)

Pin Pin Description

No. symbol
1 IN (–)
c t .
Inverting input to error amplifier
2 FB

o d u Error amplifier output

3

p r
IS (–) Overcurrent (–) detection

ed
4 GND Ground

inu
5 OUT Output

nt
6 VCC Power supply

sco
7 CT Oscillator timing capacitor

Di
8 CS Soft-start and ON/OFF control

8
 FA5304AP(S)/FA5305AP(S)

■ Absolute maximum ratings ■ Recommended operating conditions

Common to FA5304AP(S) and FA5305AP(S) Common to FA5304AP(S) and FA5305AP(S)
Item Symbol Rating Unit Item Symbol Min. Max. Unit
Supply voltage VCC 30 V Supply voltage VCC 10 30 V
Output current IO ±1.5 A Error amplifier feedback resistor RNF 100 kΩ
Error amplifier input VIN 4 V Soft-start capacitor CS 0.1 1 µF
voltage
Oscillation frequency fOSC 5 600 kHz
Feedback terminal input voltage VFB 4 V
Overcurrent detection VIS –0.3 to +4 V
terminal input voltage
CS terminal input current ICS 2 mA
Total power dissipation Pd 800 (DIP-8) *1 mW
(Ta = 25°C) Notes:
550 (SOP-8) *2
* 1 Derating factor Ta > 25°C : 8.0mW/°C ( on PC board )
Operating temperature Topr –30 to +85 °C * 2 Derating factor Ta > 25°C : 5.5mW/°C ( on PC board )
Storage temperature Tstg –40 to +150 °C

■ Electrical characteristics (Ta=25°C, VCC=18V,fosc=135kHz)

Oscillator section Common to FA5304AP(S) and FA5305AP(S)
Item Symbol Test condition Min. Typ. Max. Unit
Oscillation frequency fOSC CT = 360pF 112 135 148 kHz
Frequency variation 1 (due to supply voltage change) fdv VCC = 10 to 30V ±1 %
Frequency variation 2 (due to temperature change) fdT Ta = –30 to +85°C ±4 %

Error amplifier section Common to FA5304AP(S) and FA5305AP(S))

Item Symbol Test condition Min. Typ. Max. Unit
Reference voltage VB 1.90 2.00 2.10 V
Input bias current IB V1 = 2V
c t . –500 –50 nA
Open-loop voltage gain AV

o d u 80 dB

r
Unity-gain bandwidth fT 1.0 MHz
Maximum output voltage (Pin 2) VOM+
d p
RNF = 100kΩ 2.70 V
VOM–
u e
RNF = 100kΩ 200 mV

i n
nt
Output source current (Pin 2) IMO+ VOM = 1V –100 –50 µA

Pulse width modulation circuit section

i s co to FA5304AP(S) and FA5305AP(S)
Common
Item D Symbol Test condition Min. Typ. Max. Unit
Input threshold voltage (Pin 2) VTH FBO Duty cycle = 0% 0.80 1.00 1.20 V
VTH FBM Duty cycle = DMAX 1.70 1.90 2.10 V
Maximum duty cycle DMAX 42 45 50 %

Soft-start circuit section Common to FA5304AP(S) and FA5305AP(S)

Item Symbol Test condition Min. Typ. Max. Unit
Charge current (Pin 8) ICHG Pin 8 = 0V –15 –10 –5 µA
Input threshold voltage (Pin 8) VTH CSO Duty cycle = 0% 0.80 1.00 1.20 V
VTH CSM Duty cycle = DMAX 1.70 1.90 2.10 V

9
FA5304AP(S)/FA5305AP(S)

Overcurrent limiting circuit section

Item Symbol Test condition FA5304AP(S) FA5305AP(S) Unit
Min. Typ. Max. Min. Typ. Max.
Input threshold voltage (Pin 3) VTH IS 0.20 0.24 0.28 –0.20 –0.17 –0.14 V
Overcurrent detection terminal source current IIS Pin 3 = 0V –300 –200 –100 –240 –160 –80 µA
Delay time TPD IS 150 200 ns

Latch-mode cutoff circuit section Common to FA5304AP(S) and FA5305AP(S)

Item Symbol Test condition Min. Typ. Max. Unit
CS terminal sink current ISINK CS Pin 8 = 6V, Pin 2 = 1V 40 70 150 µA
Cutoff threshold voltage (Pin 8) VTH CS 6.5 7.0 7.5 V

Overload cutoff circuit section Common to FA5304AP(S) and FA5305AP(S)

Item Symbol Test condition Min. Typ. Max. Unit
Cutoff threshold voltage (Pin 2) VTH FB 2.5 2.7 2.9 V

Undervoltage lock-out circuit section Common to FA5304AP(S) and FA5305AP(S)

Item Symbol Test condition Min. Typ. Max. Unit
OFF-to-ON threshold voltage VTH ON 15.5 16.0 16.5 V
ON-to-OFF threshold voltage VTH OFF 8.20 8.70 9.20 V
Voltage hysteresis VHYS 7.30 V

Output section Common to FA5304AP(S) and FA5305AP(S)

Item Symbol Test condition Min. Typ. Max. Unit
L-level output voltage VOL IO = 100mA 1.30 1.80 V
VOH IO = –100mA, VCC = 18V
.
H-level output voltage 16.0 16.5 V
Rise time tr No load

u c t 50 ns
Fall time tf No load

r o d 50 ns

d p
e
Output ON/OFF control circuit section Common to FA5304AP(S) and FA5305AP(S)

n u
ti
Item Symbol Test condition Min. Typ. Max. Unit
CS terminal source current

co n
ISOURCE CS Pin 8 = 0V –15 –10 –5 µA
OFF-to-ON threshold voltage (Pin 8)
ON-to-OFF threshold voltage (Pin 8)
D i sVTH ON
VTH OFF
CS pin voltage
CS pin voltage 0.30
0.56
0.42
0.76 V
V

Overall device Common to FA5304AP(S) and FA5305AP(S)

Item Symbol Test condition Min. Typ. Max. Unit
Standby current ICC ST VCC = 14V 90 150 µA
Operating-state supply current ICC OP 9 15 mA
OFF-state supply current ICC OFF 1.1 1.8 mA
Cutoff-state supply current ICCL 1.1 1.8 mA

10
 FA5304AP(S)/FA5305AP(S)

■ Description of each circuit

1. Oscillator (See block diagram on page 8.)
The oscillator generates a triangular waveform by charging
and discharging a capacitor. CT pin voltage oscillates
between an upper limit of approx. 3.0V and a lower limit of
approx. 1.0V. The oscillation frequency is determined by a
external capacitance CT connected to CT pin, and
approximately given by the following equation:

4.8 • 104
f (kHZ) = ..................(1)
CT (pF)
The recommended oscillation range is between 5k and
600kHz.
The oscillator output is connected to a PWM comparator.

2. Feedback circuit
Figure 1 gives an example of connection in which built-in error
amplifier is used to couple the feedback signal to IN(-) pin. Let n2 Fig. 1 Configuration with error amplifier
be the number of turns of secondary winding L2 and n3 be the
number of turns of tertiary winding L3. VCC and Vout are given by

Vcc= 2(V)•(R 1+R2)/R2....................................(2)

V OUTQ(n2/n3)•(Vcc+VD3 )–VD2........................(3)
(where VD2 and V D3 are the forward voltage drops across diodes D2
and D3 respectively).

Here, the following equation must be satisfied to prevent from

the malfunction of OUT pin at shutdown.

(R1•R2)/ (R1+R2)L11kΩ...............................(4)

Figure 2 gives an example of connection in which an

c t .
u
optocoupler is used to couple the feedback signal to the FB
pin. If this circuit causes power supply instability, the frequency

r o d
p
gain can be decreased by connecting R4 and C4 as shown in

d
figure 2. R4 should be between several tens of ohms to
several kiloohms and C4 should be between several thousand
u e
picofarads to one microfarads.
ti n
c o n Fig. 2 Configuration with optocoupler (FB pin input)

Dis
3. PWM comparator
The PWM comparator has four inputs as shown in Figure 3.
Oscillator output ① is compared with CS pin voltage ➁, FB pin
➂, and DT voltage ④. The lowest of three inputs ➁, ➂, and ④
is compared with output ①. If it is lower than the oscillator
output, the PWM comparator output is high, and if it is higher
than the oscillator output, the PWM comparator output is low
(see Fig. 4).
The IC output voltage is high during when the comparator
output is low, and the IC output voltage is low during when the
comparator output is high. Fig. 3 PWM comparator
When the IC is powered up, CS pin voltage ➁ controls soft
start operation. The output pulse then begins to widen
gradually. During normal operation, the output pulse width is
determined within the maximum duty cycle (FA5304A,
FA5305A: 45%) set by DT voltage ④ under the condition set
by feedback signal ➂, to stabilize the output voltage.

Fig. 4 PWM comparator timing chart

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FA5304AP(S)/FA5305AP(S)

4. CS pin circuit
As shown in Figure 5, capacitor CS is connected to the CS pin.
When power is turned on, the constant current source (10µA)
begins to charge capacitor CS. Accordingly, the CS pin voltage
rises as shown in Figure 6. The CS pin is connected to an
input of the PWM comparator. The device is in soft-start mode
while the CS pin voltage is between 1.0V and 1.9V common to
FA5304A and FA5305A. During normal operation, the CS pin
is clamped at 3.6V by internal zener diode Zn. If the output
voltage drops due to an overload, etc., the clamp voltage shifts
from 3.6V to 8.0V. As a result, the CS pin voltage rises to 8.0V.
The CS pin is also connected to latch comparator C2. If the pin
voltage rises above 7.0V, the output of comparator C2 goes
high to turn off the bias circuit , thereby shutting the output
down. Comparator C2 can be used not only for shutdown in
response to an overload, but also for shutdown in response to
an overvoltage. Comparator C1 is also connected to the CS
pin, and the bias circuit is turned off and the output is shut
down if the CS pin voltage drops below 0.42V. In this way, Fig. 5 CS pin circuit
comparator C1 can also be used for output on/off control.
As explained above, the CS pin can be used for soft-start
operation, overload and overvoltage output shutdown and
output on/off control.
Further details on the four functions of the CS pin are given
below.

4.1 Soft start function

Figure 7 shows the soft start circuit. Figure 8 is the soft-start
operation timing chart. The CS pin is connected to capacitor
CS . When power is turned on, a 10µA constant-current source
begins to charge the capacitor. As shown in the timing chart,
the CS pin voltage rises slowly in response to the charging
current. The CS pin is connected internally to the PWM

.
comparator. The comparator output pulse slowly widens as
shown in the timing chart.

u c t
d
The soft start period can be approximately evaluated by the
period ts from the time the IC is activated to the time the output
pulse width widens to 30%. Period ts is given by the following
p r o
Fig. 6 CS pin waveform

equation:
ed
i n u
tS (mS) = 160CS (µF).................................(2)
n t
s c o
Di

Fig. 7 Soft-start circuit

Fig. 8 Soft-start timing chart

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 FA5304AP(S)/FA5305AP(S)

4.2 Overload shutdown

Figure 9 shows the overload shutdown circuit, and Figure 10 is
a timing chart which illustrates overload shutdown operation.If
the output voltage drops due to an overload or short-circuit, the
output voltage of the FB pin rises. If FB pin voltage exceeds
the reference voltage (2.7V) of comparator C3, the output of
comparator C3 switches low to turn transistor Q off. In normal
operation, transistor Q is on and the CS pin is clamped at 3.6V
by zener diode Zn. With Q off, the clamp is released and the
10µA constant-current source begins to charge capacitor CS
again and the CS pin voltage rises. When the CS pin voltage
exceeds the reference voltage (7.0V) of comparator C2, the
output of comparator C2 switches high to turn the bias circuit
off. The IC then enters the latched mode and shuts the output
down. Shutdown current consumption is 400µA(VCC=9V).
This current must be supplied through the startup resistor. The Fig. 9 Overload shutdown circuit
IC then discharges the MOSFET gates.
Shutdown operation initiated by an overload can be reset by
lowering supply voltage VCC below 8.7V or forcing the CS pin
voltage below 7.0V.The period tOL from the time that the output
is short-circuited to the time that the bias circuit turns off is
given by the following equation:

tOL(mS ) = 340Cs(µF).........................................(3)

4.3 Overvoltage shutdown

Figure 11 shows the overvoltage shutdown circuit, and Figure
12 is a timing chart which illustrates overvoltage shutdown
operation.
The optocoupler PC1 is connected between the CS and VCC
pins. If the output voltage rises too high, the PC1 turns on to Fig. 10 Overload shutdown timing chart
raise the voltage at the CS pin via resistor R6. When the CS
pin voltage exceeds the reference voltage (7.0V) of
comparator C2, comparator C2 switches high to turn the bias

c t .
u
circuit off. The IC then enters the latched mode and shuts the
output down. The shutdown current consumption of the IC is

r o d
p
400µA(VCC=9V). This current must be applied via startup

d
resistor R5.
The IC then discharges the MOSFET gates.
u e
The shutdown operation initiated by an overvoltage condition
t i n
n
can be reset by lowering supply voltage VCC below 8.7V or
forcing the CS pin voltage below 7.0V.
s c o
Di
During normal operation, the CS pin is clamped by a 3.6V
zener diode with a sink current of 150µA max. Therefore, a
current of 150µA or more must be supplied by the optocoupler
in order to raise the CS pin voltage above 7.0V.

Fig. 11 Overvoltage shutdown circuit

Fig. 12 Overvoltage shutdown timing chart

13
FA5304AP(S)/FA5305AP(S)

4.4 Output ON/OFF control

The IC can be turned on and off by an external signal applied to
the CS pin.
Figure 13 shows the external output on/off control circuit, and
Figure 14 is the timing chart.
The IC is turned off if the CS pin voltage falls below 0.42V. The
output of comparator C1 switches high to turn the bias circuit
off. This shuts the output down. The IC then discharges the
MOSFET gates.
The IC turns on if the CS pin is opened for automatic soft start.
The power supply then restarts operation.

5. Overcurrent limiting circuit

The overcurrent limiting circuit detects the peak value of every
drain current pulse of the main switching MOSFET to limit the
overcurrent.
The detection threshold is +0.24V for FA5304A with respect to
ground as shown in Figure 15.
The drain current of the MOSFET is converted to voltage by
resistor R7 and fed to the IS pin of the IC. If the voltage exceeds
the reference voltage (0.24V) of comparator C4, the output of
comparator C4 goes high to set flip-flop output Q high. The
output is immediately turned off to shut off the current. Flip-flop Fig. 13 External output on/off control circuit
output Q is reset on the next cycle by the output of the PWM
comparator to turn the output on again. This operation is
repeated to limit the overcurrent.
If the overcurrent limiting circuit malfunctions due to noise,
place an RC filter between the IS pin and the MOSFET.
Figure 16 is a timing chart which illustrates current-limiting
operations.

c t .
o d u
p r
e d
i n u
n t
s c o
Di Fig. 14 Timing chart for external output on/off control

Fig. 15 Overcurrent limiting circuit for FA5304A Fig. 16 Overcurrent timing chart for FA5304A

14
 FA5304AP(S)/FA5305AP(S)

The detection threshold is -0.17v for FA5305A with respect to

ground as shown in Figure 17.
The operation is similar to that of FA5304A except the
threshold is minus voltage compared to that which is plus
voltage for FA5304A.
Figure 18 is a timing chart which illustrates current limiting
operations.

6. Undervoltage lockout circuit

The IC incorporates a circuit which prevents the IC from
malfunctioning when the supply voltage drops. When the
supply voltage is raised from 0V, the IC starts operation with
VCC=16.0V.
If the supply voltage drops, the IC shuts its output down when
VCC=8.7V. When the undervoltage lockout circuit operates, the
CS pin goes low to reset the IC.

7. Output circuit
As shown in Figure 19, the IC’s totem-pole output can directly Fig. 17 Overcurrent limiting circuit for FA5305A
drive the MOSFET. The OUT pin can source and sink currents
of up to 1.5A.
If IC operation stops when the undervoltage lockout circuit
operates, the gate voltage of the MOSFET goes low and the
MOSFET is shut down. CS pin voltage (3.6V)

DT voltage

Oscillator output
FB pin voltage
H
OUT pin output
L

IS ( – ) pin voltage
Minus

.
detection Comparator C4

t
Reference

c
voltage (– 0.17V)

o d u
Bias voltage

p r OFF

d
ue
Overcurrent limiting

ti n
co n
Dis
Fig. 18 Overcurrent timing chart for FA5305A

Fig. 19 Output circuit

15
FA5304AP(S)/FA5305AP(S)

■ Design advice

1. Startup circuit
It is necessary to start-up IC that the voltage inclination of VCC
terminal “dVcc/dt” satisfies the following equation(4).

dVcc/dt(V/s)>1.8/(Cs(µF)).................................(4)
Cs : capacitor connected between CS terminal and GND

Note that equation (4) must be satisfied in any condition. Also,

it is necessary to keep “latch mode” for overload protection or
overvoltage protection that the current supplied to VCC
terminal through startup resistor satisfies the following
equation(5).

Icc(Lat)>0.4mA for Vcc 9.2V.......................(5)

Icc(Lat): Cutoff-state(=Latch mode) supply current

The detail is explained as follows.

Fig. 20 Startup circuit example(1)
(1) Startup circuit connected to AC line directly
Fig. 20 shows a typical startup circuit that a startup resistor Rc
is connected to AC line directly. The period from power-on to
startup is determined by Rc, RD and CA. Rc, RD and CA must
be designed to satisfy the following equations.

dVcc/dt(V/s)=
(1/CA) • {(VAVE–Vccon )/RC –Vccon/RD–Iccst} >
1.8/(Cs(µF)).....................................................(6)

Rc(kΩ)< (VAVE–9.2(V))/{0.4 (mA) + (9.2(V)/RD(kΩ) } ...........(7)

VAVE = Vac • E2/π: Average voltage applied to AC line side of Rc
Vac: AC input effective voltage

c t .
u
Vccon: ON threshold of UVLO, 16.5V(max.)
Iccst: Standby current, 0.15 mA(max.)

r o d
In this method, Vcc voltage includes ripple voltage influenced
d p
by AC voltage. Therefore, enough dVcc/dt required by
u e
equation (6) tend to be achieved easily when Vcc reaches to
t i n
Vccon even if Vcc goes up very slowly.

c o n
s
After power-off, Vcc does not rise up because a voltage

Di
applied from bias winding to VCC terminal decreases and the
current flowing RC becomes zero, therefore, re-startup does
not occur after Vcc falls down below OFF threshold of UVLO
until next power-on.

16
 FA5304AP(S)/FA5305AP(S)

(2) Startup circuit connected to rectified line

This method is not suitable for FA5304A and FA5305A,
especially concerned with re-startup operation just after power-
off or startup which AC input voltage goes up slowly. Fig. 21
shows a startup circuit that a startup resistor RA is connected
to rectified line directly.
The period from power-on to startup is determined by RA , RB
and CA. RA, RB and CA must be designed to satisfy the
following equations.

dVcc/dt(V/s)=
(1/CA )•{( VIN –Vccon )/RA– Vccon/RB –Iccst } >
1.8/(Cs(µF))................................................(8)

RA(kΩ)< (VIN– 9.2(V))/{0.4(mA) + (9.2(V)/RB(kΩ))}..............(9)

VIN: E2 •(AC input effective voltage)

After power-off, once VCC falls down below OFF threshold

voltage, VCC rises up again and re-startup occurs while the Fig. 21 Startup circuit example(2)
capacitor C1 is discharged until approximately zero because
VCC voltage rises up by the current flowing RA.
This operation is repeated several times.
After the repeated operation, IC stops in the condition that VCC Startup is impossible (dVcc/dt <1.8/Cs
voltage is equal to Vccon (=ON threshold) because capacitor just before Vcc reaches Vccon).
C1 is discharged gradually and the decreased VCC inclination
is out of the condition required by equation (4). Icc>4mA is necessary for startup at
After that, re-startup by power-on can not be guaranteed even Tj <100°C and dVcc/dt=0.
when equation (8) is satisfied. The image of that the startup is
impossible is shown in Fig. 22. It is necessary to startup IC
that supply current Icc (startup) to VCC is over 4mA in the
condition of Tj < 100 °C during Vcc is kept at Vccon(616V, Power OFF
Power ON
balance state at Vccon after the repeated operation.
Vccon
Icc (start-up) > 4mA..............................(10)
c t .
at Vcc=Vccon, Tj<100°C, after power-off

o d u Startup is impossible

This balance state that startup is impossible tends to occur at

Vccoff

p r
higher temperature.
e d
If power-on is done when Vcc is not kept at Vccon (for
i n uFig. 22 Image of Vcc waveform when re-startup is impossible
example: power-off is done and after enough time that C1 is
nt
discharged until Vcc can not be pulled up to Vccon), the IC can

s c o
Di
startup in the condition given by equation(8).

In some cases, such as when the load current of power supply

is changed rapidly, you may want to prolong the hold time of
the power supply output by means of maintaining Vcc over the
off threshold.
For this purpose, connect diode D4 and electrolytic capacitor
C4 as shown in Fig. 23. This prolongs the hold time of the
power supply voltage Vcc regardless of the period from power-
on to startup.

Fig. 23 Startup circuit example(3)

17
FA5304AP(S)/FA5305AP(S)

2. Disabling overload shutdown function

As shown in Figure 24, connect a 330kΩ to 470kΩ resistor
between the CS pin and ground. Then, the CS pin voltage
does not rise high enough to reach the reference voltage
(7.0V) of the latch comparator, and the IC does not enter the
OFF latch mode. With this connection, the overvoltage
shutdown function is not available.

3. Setting soft start period and OFF latch delay

independently
Figure 25 shows a circuit for setting the soft start period and
OFF latch delay independently. In this circuit, capacitance CS
determines the soft start period, and capacitance CL
determines the OFF latch delay. If the overload shutdown and
overvoltage shutdown functions raise the CS pin voltage to
around 5V, zener diode Zn becomes conductive to charge CL. Fig. 25 Independent setting of soft-start period and OFF latch
The OFF latch delay can be thus prolonged by CL. delay

4. Laying out Vcc and ground lines

Figure 26 and Figure 27 show the recommended layouts of
VCC and ground lines. The bold lines represent paths carrying
large currents. The lines must have an adequate thickness.

5. Sink current setting for CS terminal

A sink current to CS terminal must be satisfied the following
condition to prevent from the malfunction which uncontrolled
pulse output generates at OUT terminal when latch-mode
protection should be operated for overvoltage.

150µA < Ics(sink) < 500µA at Vcs= 6.5(V)

Ics(sink): Sink current to CS terminal

Fig. 26 Vcc line and ground line for FA5304A

Example (for the circuit shown in Fig. 28 )
Ics(sink) = (28(V)–18(V)– 6.5(V))/7.5(kΩ)
c t .
u
6 467 (µA) < 500 (µA)

r o d
d p
u e
ti n
c o n
Di s

Fig. 27 Vcc line and ground line for FA5305A

7.5kΩ 18V Zener diode

CS
Fig. 24 Disabling overload shutdown function
Under 500µA

VCC

Fig. 28 Setting sink current for CS terminal

18
 FA5304AP(S)/FA5305AP(S)

6. Notice for high frequency operation

(1) The final pulse
These ICs have the original characteristics about the pulse
width at OUT terminal when the IC is stopped by undervoltage
lockout, ON/OFF function, or latched mode for overload or
overvoltage.

When the IC is stopped, the final pulse width is 2µs(max.)

longer than normal pulse width as shown in Figure. 29.
Here, normal pulse width "Aµs" is determined by measured
condition of the power supply unit, and whole width of final
pulse is "A+2µs(max.)".

Take care of a longer pulse mentioned above for designing or

testing the circuit of power supply units.
Fig. 29 OUT terminal voltage wavefrom

(2) Power dissipation and heating

The power dissipation of IC increases and the temperature
becomes higher in proportion to the operating frequency,
because the driving power of a switching device and the
through current of output stage of IC increase.
Determine the oscillation frequency so that the junction
temperature (Tj) does not rise to 125˚C.

Tj is calculated as following equation roughly.

Tj = Tc + θj - c • Vcc • Icc
Tc: Case temperature θj-c: Thermal resistance between the junction
Vcc: V CC voltage and the case (=50˚C/W)
I CC : Supply current at the VCC terminal

c t .
o d u
p r
ed
i n u
n t
s c o
Di

19
FA5304AP(S)/FA5305AP(S)

■ Characteristic curves (Ta = 25°C)

Oscillation frequency (fOSC) vs. Oscillation frequency (fOSC) vs.
timing capacitor capacitance (CT) ambient temperature (Ta)

Output duty cycle vs. FB terminal voltage (VFB) Output duty cycle vs. FB terminal source current (Isource)

c t .
o d u
p r
e d
i n u
nt
s c o
Di
Output duty cycle vs. CS terminal voltage (VCS) H-level output voltage (VOH) vs.
output source current (ISOURCE)

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 FA5304AP(S)/FA5305AP(S)

L-level output voltage (VOL ) vs. IS (+) terminal threshold voltage (VTH IS(+)) vs.
output sink current (ISINK ) ambient temperature (Ta)
FA5304AP(S)
VOL [V]

I SINK [A]

IS (–) terminal threshold voltage (VTH IS(–)) vs. IS (+) terminal current (IIS(+)) vs.
ambient temperature (Ta) IS (+) terminal voltage (VIS(+))
FA5305AP(S) FA5304AP(S)

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IS (–) terminal current (IIS(–) ) vs. CS terminal sink current (ISINK CS) vs.
IS (–) terminal voltage (VIS(–) ) CS terminal voltage (VCS )
FA5305AP(S)

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FA5304AP(S)/FA5305AP(S)

Error amplifier frequency (f) vs. voltage gain (Av) /phase (θ) Supply current (ICC) vs. supply voltage (VCC)
Normal operation

Supply current (ICC) vs. supply voltage (VCC)

OFF or OFF latch mode

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 FA5304AP(S)/FA5305AP(S)

■ Application circuit
Á Example of FA5304AP(S) application circuit (1)

.
Á Example of FA5304AP(S) application circuit (2)

u c t
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FA5304AP(S)/FA5305AP(S)

Á Example of FA5304AP(S) application circuit (3)

Á Example of FA5305AP(S) application circuit

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Parts tolerances characteristics are not defined in the circuit design

sample shown above. When designing an actual circuit for a product,
you must determine parts tolerances and characteristics for safe and
economical operation.

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