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102 views

ADC notes

Uploaded by

ketankotane70
Copyright
© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
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 Counter type ADC

The counter type ADC is constructed using a binary counter, DAC and a comparator.
The output voltage of a DAC is VD which is equivalent to corresponding digital input
to DAC.
The following figure shows the n-bit counter type ADC.

Operation:
The n-bit binary counter is initially set to 0 by using reset command. Therefore the
digital output is zero and the equivalent voltage VD is also 0V.
When the reset command is removed, the clock pulses are allowed to go through
AND gate and are counted by the binary counter.
The D to A converter (DAC) converts the digital output to an analog voltage and
applied as the inverting input to the comparator. The output of the comparator enables
the AND gate to pass the clock.
The number of clock pulses increases with time and the analog input voltage VD is a
rising staircase waveform as shown in figure below.
The counting will continue until the DAC output VD, equals and just rises more than
unknown analog input voltage VA. Then the comparator output becomes low and this
disables the AND gate from passing the clock.
The counting stops at the instance VA< VD, and at that instant the counter stops its
progress and the conversion is said to be complete.

 Dual Slope type ADC


In dual slope type ADC, the integrator generates two different ramps, one with the
known analog input voltage VA and another with a known reference voltage –Vref.
Hence it is called a s dual slope A to D converter. The logic diagram for the same is
shown below.
Operation:
The binary counter is initially reset to 0000; the output of integrator reset to 0V and
the input to the ramp generator or integrator is switched to the unknown analog input
voltage VA.
The analog input voltage VA is integrated by the inverting integrator and generates a
negative ramp output. The output of comparator is positive and the clock is passed
through the AND gate. This results in counting up of the binary counter.
The negative ramp continues for a fixed time period t1, which is determined by a
count detector for the time period t1. At the end of the fixed time period t1, the ramp

∴VS=-VA/RC×t1
output of integrator is given by

When the counter reaches the fixed count at time period t1, the binary counter resets
to 0000 and switches the integrator input to a negative reference voltage –Vref.
Now the ramp generator starts with the initial value –Vs and increases in positive
direction until it reaches 0V and the counter gets advanced. When Vs reaches 0V,
comparator output becomes negative (i.e. logic 0) and the AND gate is deactivated.
Hence no further clock is applied through AND gate. Now, the conversion cycle is

∴VS=Vref/RC×t2
said to be completed and the positive ramp voltage is given by

Where Vref & RC are constants and time period t2 is variable.

Successive Approximation type ADC


Successive Approximation type ADC is the most widely used and popular ADC
method. The conversion time is maintained constant in successive approximation type
ADC, and is proportional to the number of bits in the digital output, unlike the counter
and continuous type A/D converters. The basic principle of this type of A/D converter
is that the unknown analog input voltage is approximated against an n-bit digital value
by trying one bit at a time, beginning with the MSB. The principle of successive
approximation process for a 4-bit conversion is explained here.

This type of ADC operates by successively dividing the voltage range by half, as
explained in the following steps.
(1) The MSB is initially set to 1 with the remaining three bits set as 000. The digital
equivalent voltage is compared with the unknown analog input voltage.
(2) If the analog input voltage is higher than the digital equivalent voltage, the MSB is
retained as 1 and the second MSB is set to 1. Otherwise, the MSB is set to 0 and the
second MSB is set to 1. Comparison is made as given in step (1) to decide whether to
retain or reset the second MSB.

It consists of a successive approximation register (SAR), DAC and comparator. The


output of SAR is given to n-bit DAC. The equivalent analog output voltage of DAC,
VD is applied to the non-inverting input of the comparator. The second input to the
comparator is the unknown analog input voltage VA. The output of the comparator is
used to activate the successive approximation logic of SAR.
When the start command is applied, the SAR sets the MSB to logic 1 and other bits
are made logic 0, so that the trial code becomes 1000.

Advantages:
1 Conversion time is very small.
2 Conversion time is constant and independent of the amplitude of the analog input
signal VA.

Disadvantages:
1 Circuit is complex.
2 The conversion time is more compared to flash type ADC.
 SINGLE SLOPE ADC

Figure 4.6.3.Block Diagram of single slope ADC


shown above is the block diagram of single slope ADC.These converter techniques
are based on comparing the unknown analog i/p voltage with a reference voltage that
begins at 0v & increases linearly with time.The time required for the reference voltage
to reach the value of unknown analog i/p voltage is proportional to the amplitude of
unknown analog i/p voltage.The time period can be measured using a digital
counter.The main circuit of this converter is a ramp generator which on receiving a
RESET from the control circuit increases linearly with time from 0v to a max volt Vm
Assume a +ive analog i/p voltage Vi is applied at the non-inverting i/p of the
comparator.When a RESET signal is applied to the control logic, the 4-digit decade
counter resets to 0 & the ramp begins to increase.Vi is +ive the comparator o/p is in
HIGH state. This allows the clk pulse to pass to the i/p of the 4-digit counter through
the AND gate & the counter is incremented.This process continues until the analog i/p
voltage is greater than the ramp generator voltage.When the ramp generator voltage is
equal to the analog i/p voltage, the comparator o/p becomes negatively saturated or
logic 0.The clk is prevented from passing through the gate causing the counter
operation.Then the control circuit generates a STROBE ROHINI COLLEGE OF
ENGINEERING & TECHNOLOGY EC8453 LINEAR INTEGRATED CIRCUITS
signal,which latches the counter values in the 4-digit latch,which is displayed on 7-
segmant displays.The displayed value is then equivalent to the amplitude of analog
input voltage.

 A to D Converter- Specifications
1. Resolution:

The resolution refers to the finest minimum change in the signal which is
accepted for conversion, and it is decided with respect to number of bits.
It is given as 1/2n, where ‘n’ is the number of bits in the digital output
word. As it is clear, that the resolution can be improved by increasing the
number of bits or the number of bits representing the given analog input
voltage.
Resolution can also be defined as the ratio of change in the value of input
voltage Vi, needed to change the digital output by 1 LSB. It is given as

Resolution = ViFS / (2n – 1)

Where ‘ViFS’ is the full-scale input voltage.

‘n’ is the number of output bits.

2.Quantization error:

If the binary output bit combination is such that for all the values of input
voltage Vi between any two voltage levels, there is a unavoidable
uncertainty about the exact value of Vi when the output is a particular
binary combination. This uncertainty is termed as quantization error. Its
value is ± (1/2) LSB. And it is given as,

QE = ViFS / 2(2n – 1)

Where ‘ViFS’ is the full-scale input voltage

‘n’ is the number of output bits.

Maximum the number of bits selected, finer the resolution and smaller the
quantization error.

3.Conversion Time:

It is defined as the total time required for an A/D converter to convert an


analog signal to digital output. It depends on the conversion technique
and propagation delay of the circuit components.

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