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DLD lab manual ok report

DLD(digital logic design) (COMSATS University Islamabad)

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Digital Logic Design

EEE241
Labs Report

ALI IJAZ
Group Member AZKA MALIK
Names
HUZAIFAH GOHAR
SP20-BSE-007
Registration SP20-BSE-022
Numbers SP20-BSE-037

Class BSE 2A

Instructor’s Name SIR SIKENDAR GULL

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Table of Contents

LAB # 01 Introduction to Basic Logic Gate ICs on Digital Logic Trainer and Proteus Simulation........................3
Lab #02 Boolean Function Implementation using Universal Gates.....................................................................8
LAB #03 Introduction to Verilog and Simulation using XILINX ISE....................................................................18
LAB #04 Design and Implementation of Boolean Functions by Standard Forms using ICs/Verilog...................29
Lab #05 Logic Minimization of Complex Functions using Automated Tools.......................................................34
Lab #06 Xilinx ISE Design Flow with FPGA......................................................................................................39
LAB #07 Design and Implementation n-bit adder/subtractor on FPGA..............................................................44
LAB #08 Design and Implementation of n-bit Binary Multiplier on FPGA..........................................................49
Lab #09 Design and Implementation of BCD to 7-Segment Decoder on FPGA................................................54
Lab # 10 Design and implementation of a sequence detector using Mealy/Moore Machine.............................60

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LAB # 01 Introduction to Basic Logic Gate ICs on Digital

Logic Trainer and Proteus Simulation

In Lab Tasks
Task 1)
Verify all gates using their ICs on KL-31001 Digital Logic Lab Trainer

INPUTS OUTPUTS

A B AND OR XOR NAND NOR XNOR

0 0 0 0 0 1 1 1

0 1 0 1 1 1 0 0

1 0 0 1 1 1 0 0

1 1 1 1 0 0 0 1

Table to observe Different Gates

INPUT OUTPUT

A B

0 1

1 0

Table to observe NOT Gate

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Task 2)
Verify all gates using their ICs on KL-31001 Digital Logic Lab Trainer

INPUTS OUTPUTS

A B AND OR XOR NAND NOR XNOR

0 0 0 0 0 1 1 1

0 1 0 1 1 1 0 0

1 0 0 1 1 1 0 0

1 1 1 1 0 0 0 1

Table to observe Different Gates

INPUT OUTPUT

A B

0 1

1 0

Table to observe NOT Gate

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Post Lab Tasks

1) What is Fan-in and Fan out?
Fan in:
Fan-in refers to a maximum number of digital inputs given to logic gates.
Fan out:
Fan out refers to the output or a number of loads that a logic gate can drive.

2) Make a list of logic gate of ICs of TTL and CMOS family along with ICs
name.

7400 Series 4000 Series

1 7400 Quad NAND Gate 4000 - Dual 3-Input NOR Gate
and Inverter.

2 7402 Quad NOR Gate 4001 - Quad 2-Input NOR Gate.

3 7408 Quad AND Gate 4002 - Dual 4-Input NOR Gate.

4 7404 Hex Inverters 4007 - Dual Complementary Pair

and Inverter.

5 7403 Quad NOR Gate 4008 - 4-Bit Full Adder.

6 7401 Quad 2-input NAND 4011 - Quad 2-Input NAND Gate.

Gate with Open Collector
Outputs.

7 7405: Hex Inverter with 4012 - Dual 4-input NAND Gate.

Open Collector Outputs.

8 7410 Triple 3- Input NAND 4013 - Dual D-type flip-flop with

Gate set and clear.

9 7411 Triple 3- Input AND 4014 - 8-bit Static Shift Register

Gate with Synchronous Parallel Enable
Input

1 7415 Triple 3- Input AND 4015 - Dual 4-Bit Serial-

0 Gate with open collector In/Parallel-Out Shift Register
outputs
11 7420 Dual 4-input NAND 4016 - Quad Bilateral Switch
Gate
1 7421 Dual 4- Input AND 4017 - Johnson Decade Counter
2 Gate with 10 Decoded Outputs

1 7430 8-Input NAND Gate 4020 - 14-stage binary counter

3

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1 7432 Quad 2-Input OR Gate 4021 - 8-Bit Static Shift Register

4 with Asynchronous Parallel Load
Input

1 7442 BCD to Decimal 4022 - 4-Bit binary up/down

5 Decoder counter

Simulation Results

NOT Gate:

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Different Gates:

Conclusion:

In this lab we have learned about logic gates, truth

tables, inputs and outputs their properties function
and about ICs as well. We have also learned about
Proteus Software and learned how to do simulation
on Proteus Software as well.

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Lab #02 Boolean Function Implementation using Universal

Gates

In Lab Tasks
Part 1: Implementing any logic expression by using only NAND gates
TASK 1.1) Verification of NOT Function:

F = A’

INPUT OUTPUT

A F

0 1

1 0

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Observation Table for NOT Gate

Task 1.2) Verification of AND Function:

F = AB

INPUTS OUTPUTS
A B F
0 0 0
0 1 0

1 0 0
1 1 1

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Task 1.3) Verification of OR Function:

F=A+B

INPUTS OUTPUTS

A B F
0 0 0

0 1 1

1 0 1

1 1 1

Task 1.4) Verification of XOR Function:

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F = A’B + AB’

INPUTS OUTPUTS

A B F
0 0 0

0 1 1

1 0 1

1 1 0

Task 1.5) Verification of XNOR Function:

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F = AB+ A’B’
INPUTS OUTPUTS

A B F
0 0 1

0 1 0

1 0 0

1 1 1

Task 1.6) Implementation of any Boolean Function (2-Variables) by

using only NAND gates

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F = AB
INPUTS OUTPUTS

A B FC FO

0 0 0 0
0 1 0 0
1 0 0 0
1 1 1 1

Part 2: Implementing any Logic expression by using only NOR gates

In Lab Tasks Part 2

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In lab Task part 2.1: Verification of NOT function

NOT gate using NOR GATE

INPUT OUTPUT

A F

0 1

1 0

Task 2.2) Verification of AND Function:

AND gate using NOR gate

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INPUTS OUTPUTS

A B F
0 0 0

0 1 0

1 0 0

1 1 1

Task 2.3) Verification of OR Function:

OR gate using NOR gate

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INPUTS OUTPUTS

A B F
0 0 0

0 1 1

1 0 1

1 1 1

Conclusion

In this lab we have learned how to implement different

gates using Universal gates i.e. NAND AND NOR. We had
also made different gates by using different types of other
gates. We learned to make truth tables by using Boolean
functions.

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LAB #03 Introduction to Verilog and Simulation using XILINX

ISE

In-Lab Task 2:
Task 1:
Write a Verilog code (Gate-Level) for NOT, OR, NOR, NAND, XOR and XNOR.

Answer:
Verilog code for NOT:
module NOT_gate (Y, A);
input A;
output Y;
not (Y,A);
endmodule

Verilog code for OR:

module OR_gate (Y, A, B);
input A, B;
output Y;
or (Y, A, B);
endmodule

Verilog code for NOR:

module NOR_gate (Y, A ,B);
input A, B;
output Y;
nor (Y, A, B);
endmodule

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Verilog code for NAND:

Module NAND_gate (Y, A, B);
input A, B;
output Y,
nand (Y, A, B);
endmodule

Verilog code for XOR:

module XOR_gate (Y, A, B);
input A,B;
output Y;
xor (Y, A, B);
endmodule

Verilog code for XNOR:

module XNOR_gate (Y, A, B);
input A, B;
output Y;
xnor (Y, A, B);
endmodule

Task 2:
Write a stimulus/test bench for Task 01 and show the simulation results.

Answer:
NOT:
Testbench:
module NOT_Testbench;
// Inputs
reg A;
// Outputs
wire Y;
// Instantiate the Unit Under Test (UUT)
NOT_Gateuut (
.A(A),

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.Y(Y)
);
initial begin
// Initialize Inputs
A = 0;
// Wait 100 ns for global reset to finish
#100;A=1;
// Add stimulus here
end
endmodule

OR:

Testbench:
module OR_testbench;
// Inputs
reg A;
reg B;
// Outputs
wire Y;
// Instantiate the Unit Under Test (UUT)
OR_gateuut (
.A(A),
.B(B),
.Y(Y)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
// Wait 100 ns for global reset to finish

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#100;A=1;B=1;
// Add stimulus here
end
endmodule

NOR:

Testbench:
module NOR_testbench;
// Inputs
reg A;
reg B;
// Outputs
wire Y;
// Instantiate the Unit Under Test (UUT)
NOR_gateuut (
.A(A),
.B(B),
.Y(Y)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;

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// Wait 100 ns for global reset to finish

#100;A=1;B=1;
// Add stimulus here
end
endmodule

NAND:

Test bench:
module NAND_testbench;

// Inputs
reg A;
reg B;

// Outputs
wire Y;

// Instantiate the Unit Under Test (UUT)

NAND_gateuut (
.A(A),
.B(B),
.Y(Y)
);

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initial begin
// Initialize Inputs
A = 0;
B = 0;

// Wait 100 ns for global reset to finish

#100;A=1;B=1;

// Add stimulus here

end

endmodule

XOR:

Test bench:
module XNOR_testbench;

// Inputs
reg A;
reg B;

// Outputs
wire Y;

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// Instantiate the Unit Under Test (UUT)

XOR_gateuut (
.A(A),
.B(B),
.Y(Y)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;

// Wait 100 ns for global reset to finish

#100;A=1;B=1;

// Add stimulus here

end

endmodule

XNOR:

Testbench:
module XNOR_testbench;

// Inputs
reg A;

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reg B;

// Outputs
wire Y;

// Instantiate the Unit Under Test (UUT)

XNOR_gateuut (
.A(A),
.B(B),
.Y(Y)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;

// Wait 100 ns for global reset to finish

#100;A=1;B=1;

// Add stimulus here

end

endmodule

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Post-Lab:
Task 1:

Write a Verilog code for the given Boolean function* (e.g.F = x + x’y + yz’)

a) Using Gate-Level model (Provide Gate Level diagram and Truth Table)

b) Using Dataflow model

Answer:

a) Gate level:
Verilog Code:
module Boolean_Function(
input x,
input y,
input z,
output F
);
wire w1, w2, w3, w4;
not g1(w1, x);
and g2(w2, w1, y);
not g3(w3, z);
and g4(w4, y, w3);
or g5(F, x, w2, w4);
endmodule

Gate level Diagram:

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Dataflow Model:
Assign F = (x) | (~x & y) | (y & ~z)

Task 2:

Write a stimulus/test bench for Task 01 and show the simulation results.

Answer:

Testbench:
module Boolean_Function_Testbench;

// Inputs
reg x;
reg y;
reg z;

// Outputs
wire F;

// Instantiate the Unit Under Test (UUT)

Boolean_Functionuut (
.x(x),
.y(y),
.z(z),
.F(F)
);

initial begin
// Initialize Inputs
x = 0;
y = 0;
z = 0;

// Wait 100 ns for global reset to finish

#100;x=1;y=1;z=1;

// Add stimulus here

end

endmodule

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Conclusion:

In this lab we had studied Verilog (Hardware description language)

with Xilinx ISE. Verilog is used in modern digital systems. It is most
commonly used in the design and verification of Digital Circuits.
Xilinx is used for the verification and simulation of different
Verilog codes and mixed languages design.

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LAB #04 Design and Implementation of Boolean Functions

by Standard Forms using ICs/Verilog

In-Lab Tasks
Implement the circuit for the given function “F”. Function’s output is given in
Table 4.5. Finds its Boolean expression in SoP and PoS forms.

Answer:

Implementation of circuit:

Boolean Expressions:
F = Σ(3, 7, 8, 13, 14, 15)

SoPForm=(A+B+C+D).(A+B+C+D’).(A+B+C’+D).(A+B’+C+D).(A+B’+C+D’)+(A+B’+C’+D).
(A’+B+C+D’).(A’+B+C’+D).(A’+B+C’+D’).(A’+B’+C+D)

Reduced SoP Form = (A+C).(A+D).(B’+C+D).(A’B+C’).(A’+B+D’)

PoS Form = A’B’CD + A’BCD + AB’C’D’ + ABC’D + ABCD’ + ABCD

Reduced PoS Form = A’CD + ABC + ABD + AB’C’D’

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Post Lab Tasks:

1. Write a Verilog code for the sum of minterms circuit, � 1, (Structural Level).
Answer:

Verilog Code:
module F1(
input A,
input B,
input C,
input D,
output F
);
wire w1, w2, w3, w4, w5, w6, w7, w8;
not g1(w, A);
and g2(w2, w1, C, D);
and g3(w3, A, B, C);
and g4(w4, A, B, D);
not g5(w5, B);
not g6(w6, C);
not g7(w7, D);
and g8(w8, A, w5, w6, w7);
or g9(F, w2, w3, w5, w8);
endmodule

2. Write a Verilog code for the reduced SoP circuit, �2, (Structural Level).
Answer:

Verilog Code:
module F2(
input A,
input B,
input C,
input D,
output F
);
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15, w16, w17, w18,
w19, w20, w21, w22, w23, w24, w25, w26, w27, w28, w29, w30;
nand g1(w1, A, C);
nand g2(w2, C, A);
nand g3(w3, w1, w2);
nand g4(w5, A, D);

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nand g5(w6, A, D);

nand g6(w7, w5, w6);
nand g7(w4, w3, w7);
nand g8(w28, w4, w4);
nand g9(w8, B, B);
nand g10(w10, w8, C, D);
nand g11(w9. B, B);
nand g12(w11, w9, C, D);
nand g13(w12, w10, w11);
nand g14(w13, A, A);
nand g15(w15, w13, B, w14);
nand g16(w14, C, C);
nand g17(w16, A, A);
nand g18(w17, C, C);
nand g19(w18, w16, B, w17);
nand g20(w19,w15, w18);
nand g21(w20, A, A);
nand g22(w21, D D);
nand g23(w23, A, A);
nand g24(w24, D, D);
nand g25(w22, w20, B, w21);
nand g26(w25, w23, B, w24);
nand g27(w26, w22, w25);
nand g28(w27, w12, w19, w26);
nand g29(w29, w27, w27);
nand g30(w30, w28, w29);
nand g31(F, w30, w30);
endmodule

3. Simulate and verify the outputs by making an appropriate stimulus for the
above modules.
Answer:

F1:
module F1_Testbench;
// Inputs
reg A;
reg B;
reg C;
reg D;

// Outputs
wire F;

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// Instantiate the Unit Under Test (UUT)

F1 uut (
.A(A),
.B(B),
.C(C),
.D(D),
.F(F)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;
C = 0;
D = 0;

// Wait 100 ns for global reset to finish

#100;A=0;B=0;C=0;D=1;

// Add stimulus here

end

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Conclusion

In this Lab we had learned how to implement Boolean

Functions by SOP(sum of products) and POS (products of
sum).

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Lab #05 Logic Minimization of Complex Functions using

Automated Tools

In-Lab Task 01:

Implement the minimized function given below using logic gate IC(s).

F(A, B, C, D) = Σ (3, 5, 7, 11)

Function in sum of Min-terms form: AˊBˊCD + AˊBCˊD + AˊBCD + ABˊCD

Simplified Function using K-map: AˊBD + BˊCD

Simplified Calculation (K-map):

AˊBCˊD + AˊBCD + AˊBˊCD + ABˊCD

= AˊBD (Cˊ + C) + BˊCD (A + Aˊ)

= AˊBD + BˊCD

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Circuit Diagram of a min-terms form of the Function:

Circuit Diagram of a simplified Function:

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Truth Table:

A B C D F Observed Outputs
F1 F2
0 0 0 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 0 0 0
0 0 1 1 1 1 1
0 1 0 0 0 0 0
0 1 0 1 1 1 1
0 1 1 0 0 0 0
0 1 1 1 1 1 1
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 0 0
1 0 1 1 1 1 1
1 1 0 0 0 0 0
1 1 0 1 0 0 0
1 1 1 0 0 0 0
1 1 1 1 0 0 0

F1: Output of min-terms form of circuit

F2: Output of simplified function circuit

In-Lab Task 2:
Using Structural Model, write a Verilog description for the 8-variables function ‘F’.

F (a, b, c, d, e, f, g, h) = summation (11, 23, 44, 64)

F (a, b, c, d, e, f, g, h) = a'b'c'd'ef'gh + a'b'c'de'fgh + a'b'cd'efg'h' + a'bc'd'e'f'g'h'

Verilog Code:

module main;
wire F;
reg a,b,c,d,e,f,g,h;
initial
begin

$monitor("a=%d,b=%d,c=%d,d=%d,e=%d,f=%d,g=%d,h=%d,F=%d",a,b,c,d,e,f,g,h,F);
a=0;b=0;c=0;d=0;e=1;f=0;g=1;h=1;
#100 a=1;b=0;c=1;d=1;e=1;f=0;g=1;h=0;
end

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GL Z(F,a,b,c,d,e,f,g,h);
endmodule
module GL(F,a,b,c,d,e,f,g,h);
input a,b,c,d,e,f,g,h;
output F;
or g1(F,w25,w26,w27);
and g2(w26,w17,w18,w19,w20,w21,w22,w23,w24);
and g3(w27,w9,w10,w11,w12,w13,w14,w15,w16);
not g4(w7,a,a);
not g5(w8,b);
not g6(w1,c);
not g7(w2,d);
not g8(w13,e);
not g9(w4,f);
not g10(g);
not g11(h);

endmodule

Post Lab Tasks

 Using Data flow model , write a Verilog description for the 8-variable function ‘F’(used in
“In-lab Task 2”)

F (a, b, c, d, e, f, g, h) = summation (11, 23, 44, 64)

F (a, b, c, d, e, f, g, h) = a'b'c'd'ef'gh + a'b'c'de'fgh + a'b'cd'efg'h' + a'bc'd'e'f'g'h'

Data flow Model:

assign f = (~a & ~b & ~c & ~d & e & ~f & g & h) | (~a & ~b & ~c & d & ~e & f & g & h) | (~a & ~b & c &
~d & e & f & ~g & ~h) | (~a & b & ~c & ~d & ~e & ~f & ~g & ~h)

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Simulate and verifying the output.

Simulation Result on Verilog:

Conclusion / Critical Analysis:

In this lab we learnt how to implement K-Map minimization using

ICs which helps in solving excessive variables and reduces the need
for extensive calculations. We also studied about the use of logic
minimization automated tools for an excessive number of variables
in order to enhance efficiency and make a well-designed circuit. We
also simulated the function by using Xilinx Software to check its
accuracy and efficiency by comparing calculated and simulated
results.

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Lab #06 Xilinx ISE Design Flow with FPGA

Pre-lab Task:

K-Map Minimization

K-MAP for ‘w’ K-Map for ‘x’

Reduced equation for w:

w= A

Reduced equation for x

x= A’B+AB’

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K-Map for ‘y’ K-Map for ‘z’

Reduced equation for ‘y’:

y= B’C+BC’

Reduced equation for ‘z’

z= C’D+CD’

Step B
Gate level circuit diagram:

In-lab Task:

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Q1: using Gate level model, write a verilog description of binary to gray
conversion.

module gray_code(w,x,y,z,a,b,c,d);
input a,b,c,d;
output w,x,y,z;
wire w1, w2, w3, w4,w5,w6,w7,w8,w9.w10,w11,w12,w13;
not g1(w1, a);
not g2(w,w1);
not g3(w2,a);
and g4(w4,w2,b);
not g5(w3,b);
and g6(w5,w3,a);
or g7(x,w4,w5);
not g8(w6,b);
and g9(w7,w6,c);
not g10(w8,c);
and g11(w9,w8,b);
or g12(y,w7,w9);
not g13(w10,c);
and g14(w12,w10,d);
not g15(w11,d);
and g16(w13,w11,c);
or g17(z,w12,w13);
endmodule

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Q2: using behavioral model, write a verilog description of binary to gray

conversion.

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Post-lab Task:
Timing table:

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Critical Analysis/Conclusion:

In this lab we learned the use of behavioral modelling for

circuit designing. With the help of behavioral modelling we
designed a Verilog code which was used to convert Binary
Coded Decimal (BCD) to Gray code. We also used K map
minimizer to minimize the circuit and it was implemented on
Proteus.

LAB #07 Design and Implementation n-bit adder/subtractor

on FPGA.

Pre-lab task:
Half adder by Gate Level:
module half_adder(s, c, a, b);
input a, b;
output s, c;
wire w1, w2, w3;
and g0(c, a, b);
nand g1(w2, a, b);
nand g2(w1, a, w2);
nand g3(w3, w2, b);
nand g4(s, w1, w3);
endmodule

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In-lab Task:
Part 01:
4-bit binarry Adder by Gate level along with test bench:
module main;
reg [3:0]a, b;
reg cin;
wire [3:0]s;
wire c;
initial
begin
$monitor("a=%b, b= %b, cin=%b, s=%b, c=%b", a, b, cin, s, c);
a=0; b=0; cin=0;
#100 a=1; b=0; cin=0;
#100 a=1; b=1; cin=0;
#100 a=15; b=15;cin=0;
end
Fourbit_Adder g1(s, c, a, b, cin);
endmodule

module half_adder(s, c, a, b);

input a, b;
output s, c;
wire w1, w2, w3;
and g0(c, a, b);
nand g1(w2, a, b);
nand g2(w1, a, w2);
nand g3(w3, w2, b);
nand g4(s, w1, w3);
endmodule

module full_Adder(s, c, x , y, cin);

wire s1, c1, s2, c2;
input x, y, cin;
output s, c;
half_adder g1(s1, c1, x, y);
half_adder g2(s, c2, s1, cin);
or g3(c, c1, c2);
endmodule

module Fourbit_Adder(s, c, a, b, cin);

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input [3:0]a, b;
input cin;
output [3:0]s;
output c;
wire c1, c2, c3;
full_Adder g1(s[0], c1, cin, a[0], b[0]);
full_Adder g2(s[1], c2, c1, a[1], b[1]);
full_Adder g3(s[2], c3, c2, a[2], b[2]);
full_Adder g4(s[3], c, c3, a[3], b[3]);
endmodule

Part 02:
Comparator Verilog Code along with test bench:
module main;
reg [3:0] a,b;
wire x,y,z;
initial
begin
$monitor("a=%b, b=%b, x=%b, y=%b, z=%b", a, b, x, y, z);
a=0;b=0;
#10;a=8; b=8;
#10;a=2;b=6;
#10; a=5;b=3;

end
comparator s1(a,b,x,y,z);

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endmodule

module comparator(a, b, x, y, z);

input[3:0]a, b;
output reg x,y,z;
always@(a,b)
begin
if (a==b)
begin
x=1'b1;
y=1'b0;
z=1'b0;
end
else if(a>b)
begin
x= 1'b0;
y= 1'b0;
z= 1'b1;
end
else
begin
x= 1'b0;
y= 1'b1;
z= 1'b0;
end
end
endmodule

Post-lab Task:
Behavioral implementation of n-bit adder/subtractor:

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Test Bench:

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Critical Analysis/Conclusion:

In this lab we learned how to perform behavioral

modeling. With the help of behavioral modeling we
implemented comparator as well as n-bit adder.
Moreover, we were introduced to the use of parameter
in the verilog code.

LAB #08 Design and Implementation of n-bit Binary

Multiplier on FPGA

Pre Lab Task

Using Structural-Level model write a Verilog description of 2-bit by 2-bit multiplier

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Test bench:

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In Lab Task 1
Implement 4-bit by 2-bit Binary Multiplier Using ICs

Verifying its functionality by comparison

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Now simulating the same A – bits and B – bits on Proteus

In Lab Task 2

Simulating 4 – bit by 3 – bit multiplier on Xilinx using Verilog structural

programming:

4x3 bit multiplier:

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Test bench:

Critical Analysis:

4–bit by 2–bit multiplier designing on Proteus was only time-

consuming. Since, we had hands-on experience with Proteus in the
last semester, there were no serious issues while using this. On the
other hand, 4 – bit by 3 – bit multiplier’s Verilog structural description
on Xilinx was overwhelming. The module importing procedure took us
a while to figure out and at the end, the simulation produced wrong
results. After skimming through our code over again and again, we
found a minute mistake that was causing the trouble. The same input
was repeated two times. After fixing the type in the code, we received
the ideal outcome.

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Lab #09 Design and Implementation of BCD to 7-Segment

Decoder on FPGA

IN-LAB TASK 1
Test the functionality Of a BCD to 7-Segment decoder IC (CD4511) with
common cathode 7-Segment display

On Proteus:

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IN-LAB TASK 2

Design and Implementation of a BCD to 7-Segment decoder on

FPGA (Nexys2)
On Xilinx:

Test bench:

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Post-lab Tasks

1: Verilog for BCD to 7 segment-decoder

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Test bench:

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2: Recourse utilization and timing delay

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CONCLUSION/ CRITICAL ANALYSIS:

In this lab we had two tasks that we had to perform. In task 1 we

used common cathode to test the functionality of BCD to 7-
Segment decoder by simulating the circuit on Proteus. We also
observed the behavior of BCD to 7-Segment decoder on 7-Segment
by choosing different BCD values. In task 2 on Xilinx to get the
truth table. On the Xilinx we implemented the code and test bench.
In order to display the inputs and outputs on stimulation we gave
the $monitor command and we also used case statement. Then we
gave different input combinations to get the desired output. We
stimulated the code then to get the waveform. We didn’t get the
correct results due to some problems in our code but after
thoroughly going through our code we were able to fix the small
error and got the required results.

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Lab # 10 Design and implementation of a sequence detector

using Mealy/Moore Machine

State Diagram:

State Table:

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Equations
Reduced from K-Maps:

Equation from A1:

~ABC+A~B

Equation from B1:

~A~BC+A~B~C+ABC

Equation from Y:
AB~C

Circuit Diagram:

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In-lab+Post-lab
Moore FSM for Sequence Detection:

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Test Bench & Timing table:

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Timing Table

Mealy FSM for Sequence Detection

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Test Bench:

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Conclusion / Critical Analysis:

In this lab, we knew about Mealy and Moore model. But we used
Mealy machine model in this report. In lab task we converted
decimal number (22) into binary number then we used that binary
number to implement the state diagram using mealy model. The
state diagram of mealy machine associates an output value with each
transition edge, in contrast to the state diagram for a Moore
machine, which associates an output value with each state. In Mealy
model, we observed in state diagram that the next state depends on
the input and present state. We also observed that number of states
can become unmanageable if they are too many.

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