7.

External Memory Interfaces in

Cyclone IV Devices
March 2016
CYIV-51007-2.6

CYIV-51007-2.6

This chapter describes the memory interface pin support and the external memory
interface features of Cyclone® IV devices.
In addition to an abundant supply of on-chip memory, Cyclone IV devices can easily
interface with a broad range of external memory devices, including DDR2 SDRAM,
DDR SDRAM, and QDR II SRAM. External memory devices are an important system
component of a wide range of image processing, storage, communications, and
general embedded applications.

1 Altera recommends that you construct all DDR2 or DDR SDRAM external memory
interfaces using the Altera® ALTMEMPHY megafunction. You can implement the
controller function using the Altera DDR2 or DDR SDRAM memory controllers,
third-party controllers, or a custom controller for unique application needs.
Cyclone IV devices support QDR II interfaces electrically, but Altera does not supply
controller or physical layer (PHY) megafunctions for QDR II interfaces.

This chapter includes the following sections:

■ “Cyclone IV Devices Memory Interfaces Pin Support” on page 7–2
■ “Cyclone IV Devices Memory Interfaces Features” on page 7–12

f For more information about supported maximum clock rate, device and pin planning,
IP implementation, and device termination, refer to the External Memory Interface
Handbook.

© 2016 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos
are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its ISO
semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and 9001:2008
services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service Registered
described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.

Cyclone IV Device Handbook,

Volume 1
March 2016

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7–2 Chapter 7: External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Pin Support

Figure 7–1 shows the block diagram of a typical external memory interface data path
in Cyclone IV devices.

Figure 7–1. Cyclone IV Devices External Memory Data Path (1)

DQS/CQ/CQn
DQ

OE IOE
OE IOE
Register Register

IOE
IOE
Register
Register
VCC IOE
DataA IOE LE
Register Register Register

GND IOE
Register
DataB IOE LE LE
Register Register Register

System Clock
PLL

-90° Shifted Clock Capture Clock

Note to Figure 7–1:

(1) All clocks shown here are global clocks.

f For more information about implementing complete external memory interfaces, refer
to the External Memory Interface Handbook.

Cyclone IV Devices Memory Interfaces Pin Support

Cyclone IV devices use data (DQ), data strobe (DQS), clock, command, and address
pins to interface with external memory. Some memory interfaces use the data mask
(DM) or byte write select (BWS#) pins to enable data masking. This section describes
how Cyclone IV devices support all these different pins.

f For more information about pin utilization, refer to Volume 2: Device, Pin, and Board
Layout Guidelines of the External Memory Interface Handbook.

Data and Data Clock/Strobe Pins

Cyclone IV data pins for external memory interfaces are called D for write data, Q for
read data, or DQ for shared read and write data pins. The read-data strobes or read
clocks are called DQS pins. Cyclone IV devices support both bidirectional data strobes
and unidirectional read clocks. Depending on the external memory standard, the DQ
and DQS are bidirectional signals (in DDR2 and DDR SDRAM) or unidirectional
signals (in QDR II SRAM). Connect the bidirectional DQ data signals to the same
Cyclone IV devices DQ pins. For unidirectional D or Q signals, connect the read-data
signals to a group of DQ pins and the write-data signals to a different group of DQ pins.

1 In QDR II SRAM, the Q read-data group must be placed at a different VREF bank
location from the D write-data group, command, or address pins.

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Chapter 7: External Memory Interfaces in Cyclone IV Devices 7–3
Cyclone IV Devices Memory Interfaces Pin Support

In Cyclone IV devices, DQS is used only during write mode in DDR2 and
DDR SDRAM interfaces. Cyclone IV devices ignore DQS as the read-data strobe
because the PHY internally generates the read capture clock for read mode. However,
you must connect the DQS pin to the DQS signal in DDR2 and DDR SDRAM interfaces,
or to the CQ signal in QDR II SRAM interfaces.

1 Cyclone IV devices do not support differential strobe pins, which is an optional

feature in the DDR2 SDRAM device.

f When you use the Altera Memory Controller MegaCore® function, the PHY is
instantiated for you. For more information about the memory interface data path,
refer to the External Memory Interface Handbook.

1 ALTMEMPHY is a self-calibrating megafunction, enhanced to simplify the

implementation of the read-data path in different memory interfaces. The
auto-calibration feature of ALTMEMPHY provides ease-of-use by optimizing clock
phases and frequencies across process, voltage, and temperature (PVT) variations.
You can save on the global clock resources in Cyclone IV devices through the
ALTMEMPHY megafunction because you are not required to route the DQS signals on
the global clock buses (because DQS is ignored for read capture). Resynchronization
issues do not arise because no transfer occurs from the memory domain clock (DQS) to
the system domain for capturing data DQ.

All I/O banks in Cyclone IV devices can support DQ and DQS signals with DQ-bus
modes of ×8, ×9, ×16, ×18, ×32, and ×36 except Cyclone IV GX devices that do not
support left I/O bank interface. DDR2 and DDR SDRAM interfaces use ×8 mode DQS
group regardless of the interface width. For a wider interface, you can use multiple ×8
DQ groups to achieve the desired width requirement.
In the ×9, ×18, and ×36 modes, a pair of complementary DQS pins (CQ and CQ#)
drives up to 9, 18, or 36 DQ pins, respectively, in the group, to support one, two, or four
parity bits and the corresponding data bits. The ×9, ×18, and ×36 modes support the
QDR II memory interface. CQ# is the inverted read-clock signal that is connected to
the complementary data strobe (DQS or CQ#) pin. You can use any unused DQ pins as
regular user I/O pins if they are not used as memory interface signals.

f For more information about unsupported DQS and DQ groups of the Cyclone IV
transceivers that run at 2.97 Gbps data rate, refer to the Cyclone IV Device Family Pin
Connection Guidelines.

March 2016 Altera Corporation Cyclone IV Device Handbook,

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7–4 Chapter 7: External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Pin Support

Table 7–1 lists the number of DQS or DQ groups supported on each side of the
Cyclone IV GX device.

Table 7–1. Cyclone IV GX Device DQS and DQ Bus Mode Support for Each Side of the Device
Number Number Number Number Number Number
Device Package Side ×8 ×9 ×16 ×18 ×32 ×36
Groups Groups Groups Groups Groups Groups
Right 1 0 0 0 — —
EP4CGX15 169-pin FBGA Top (1) 1 0 0 0 — —
Bottom (2) 1 0 0 0 — —
Right 1 0 0 0 — —
169-pin FBGA Top (1) 1 0 0 0 — —
Bottom (2) 1 0 0 0 — —
Right 2 2 1 1 — —
EP4CGX22
324-pin FBGA Top 2 2 1 1 — —
EP4CGX30
Bottom 2 2 1 1 — —
Right 4 2 2 2 1 1
484-pin FBGA (3) Top 4 2 2 2 1 1
Bottom 4 2 2 2 1 1
Right 4 2 2 2 1 1
484-pin FBGA Top 4 2 2 2 1 1
EP4CGX50 Bottom 4 2 2 2 1 1
EP4CGX75 Right 4 2 2 2 1 1
672-pin FBGA Top 4 2 2 2 1 1
Bottom 4 2 2 2 1 1
Right 4 2 2 2 1 1
484-pin FBGA Top 4 2 2 2 1 1
Bottom 4 2 2 2 1 1
Right 4 2 2 2 1 1
EP4CGX110
672-pin FBGA Top 4 2 2 2 1 1
EP4CGX150
Bottom 4 2 2 2 1 1
Right 6 3 2 2 1 1
896-pin FBGA Top 6 3 3 3 1 1
Bottom 6 3 3 3 1 1
Notes to Table 7–1:
(1) Some of the DQ pins can be used as RUP and RDN pins. You cannot use these groups if you are using these pins as RUP and RDN pins for
OCT calibration.
(2) Some of the DQ pins can be used as RUP pins while the DM pins can be used as RDN pins. You cannot use these groups if you are using the
RUP and RDN pins for OCT calibration.
(3) Only available for EP4CGX30 device.

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Chapter 7: External Memory Interfaces in Cyclone IV Devices 7–5
Cyclone IV Devices Memory Interfaces Pin Support

Table 7–2 lists the number of DQS or DQ groups supported on each side of the
Cyclone IV E device.

Table 7–2. Cyclone IV E Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 1 of 3)
Number Number Number Number Number Number
Device Package Side ×8 ×9 ×16 ×18 ×32 ×36
Groups Groups Groups Groups Groups Groups
Left 0 0 0 0 — —
Right 0 0 0 0 — —
144-pin EQFP
Bottom (1), (3) 1 0 0 0 — —
Top (1), (4) 1 0 0 0 — —
Left (1) 1 1 0 0 — —
EP4CE6 Right (2) 1 1 0 0 — —
256-pin UBGA
EP4CE10 Bottom 2 2 1 1 — —
Top 2 2 1 1 — —
Left (1) 1 1 0 0 — —
Right (2) 1 1 0 0 — —
256-pin FBGA
Bottom 2 2 1 1 — —
Top 2 2 1 1 — —
Left 0 0 0 0 — —
Right 0 0 0 0 — —
144-pin EQFP
Bottom (1), (3) 1 0 0 0 — —
Top (1), (4) 1 0 0 0 — —
Left 0 0 0 0 — —
Right 0 0 0 0 — —
164-pin MBGA
Bottom (1), (3) 1 0 0 0 — —
Top (1), (4) 1 0 0 0 — —
Left 1 1 0 0 — —
Right 1 1 0 0 — —
256-pin MBGA
Bottom (1), (3) 2 2 1 1 — —
Top (1), (4) 2 2 1 1 — —
EP4CE15
Left (1) 1 1 0 0 — —
Right (2) 1 1 0 0 — —
256-pin UBGA
Bottom 2 2 1 1 — —
Top 2 2 1 1 — —
Left (1) 1 1 0 0 — —
Right (2) 1 1 0 0 — —
256-pin FBGA
Bottom 2 2 1 1 — —
Top 2 2 1 1 — —
Left 4 4 2 2 1 1
Right 4 4 2 2 1 1
484-pin FBGA
Bottom 4 4 2 2 1 1
Top 4 4 2 2 1 1

March 2016 Altera Corporation Cyclone IV Device Handbook,

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7–6 Chapter 7: External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Pin Support

Table 7–2. Cyclone IV E Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 2 of 3)
Number Number Number Number Number Number
Device Package Side ×8 ×9 ×16 ×18 ×32 ×36
Groups Groups Groups Groups Groups Groups
Left 0 0 0 0 — —
Right 0 0 0 0 — —
144-pin EQFP
Bottom (1), (3) 1 0 0 0 — —
Top (1), (4) 1 0 0 0 — —
Left (1) 1 1 0 0 — —
Right (2) 1 1 0 0 — —
EP4CE22 256-pin UBGA
Bottom 2 2 1 1 — —
Top 2 2 1 1 — —
Left (1) 1 1 0 0 — —
Right (2) 1 1 0 0 — —
256-pin FBGA
Bottom 2 2 1 1 — —
Top 2 2 1 1 — —
Left (1) 2 2 1 1 0 0
Right (2) 2 2 1 1 0 0
EP4CE30 324-pin FBGA
Bottom 2 2 1 1 0 0
Top 2 2 1 1 0 0
Left 4 4 2 2 1 1
Right 4 4 2 2 1 1
484-pin FBGA
Bottom 4 4 2 2 1 1
EP4CE30 Top 4 4 2 2 1 1
EP4CE115 Left 4 4 2 2 1 1
Right 4 4 2 2 1 1
780-pin FBGA
Bottom 6 6 2 2 1 1
Top 6 6 2 2 1 1
Left 2 2 1 1 0 0
Right 2 2 1 1 0 0
EP4CE40 324-pin FBGA
Bottom 2 2 1 1 0 0
Top 2 2 1 1 0 0

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Chapter 7: External Memory Interfaces in Cyclone IV Devices 7–7
Cyclone IV Devices Memory Interfaces Pin Support

Table 7–2. Cyclone IV E Device DQS and DQ Bus Mode Support for Each Side of the Device (Part 3 of 3)
Number Number Number Number Number Number
Device Package Side ×8 ×9 ×16 ×18 ×32 ×36
Groups Groups Groups Groups Groups Groups
Left 4 4 2 2 1 1
Right 4 4 2 2 1 1
484-pin UBGA
Bottom 4 4 2 2 1 1
Top 4 4 2 2 1 1
Left 4 4 2 2 1 1
EP4CE40
Right 4 4 2 2 1 1
EP4CE55 484-pin FBGA
Bottom 4 4 2 2 1 1
EP4CE75
Top 4 4 2 2 1 1
Left 4 4 2 2 1 1
Right 4 4 2 2 1 1
780-pin FBGA
Bottom 6 6 2 2 1 1
Top 6 6 2 2 1 1
Notes to Table 7–2:
(1) Some of the DQ pins can be used as RUP and RDN pins. You cannot use these groups if you are using these pins as RUP and RDN pins for
OCT calibration.
(2) Some of the DQ pins can be used as RUP pins while the DM pins can be used as RDN pins. You cannot use these groups if you are using the
RUP and RDN pins for OCT calibration.
(3) There is no DM pin support for these groups.
(4) PLLCLKOUT3n and PLLCLKOUT3p pins are shared with the DQ or DM pins to gain ×8 DQ group. You cannot use these groups if you are using
PLLCLKOUT3n and PLLCLKOUT3p.

f For more information about device package outline, refer to the Device Packaging
Specifications webpage.

DQS pins are listed in the Cyclone IV pin tables as DQSXY, in which X indicates the DQS
grouping number and Y indicates whether the group is located on the top (T), bottom
(B), or right (R) side of the device. Similarly, the corresponding DQ pins are marked as
DQXY, in which the X denotes the DQ grouping number and Y denotes whether the
group is located on the top (T), bottom (B), or right (R) side of the device. For example,
DQS2T indicates a DQS pin belonging to group 2, located on the top side of the device.
Similarly, the DQ pins belonging to that group is shown as DQ2T.

1 Each DQ group is associated with its corresponding DQS pins, as defined in the Cyclone
IV pin tables. For example:

■ For DDR2 or DDR SDRAM, ×8 DQ group DQ3B[7..0] pins are associated with
the DQS3B pin (same 3B group index)
■ For QDR II SRAM, ×9 Q read-data group DQ3T[8..0] pins are associated with
DQS0T/CQ0T and DQS1T/CQ0T# pins (same 0T group index)
The Quartus® II software issues an error message if a DQ group is not placed properly
with its associated DQS.

March 2016 Altera Corporation Cyclone IV Device Handbook,

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7–8 Chapter 7: External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Pin Support

Figure 7–2 shows the location and numbering of the DQS, DQ, or CQ# pins in the
Cyclone IV GX I/O banks.

Figure 7–2. DQS, CQ, or CQ# Pins in Cyclone IV GX I/O Banks (1)

DQS1T/CQ1T#

DQS3T/CQ3T#

DQS5T/CQ5T#

DQS4T/CQ5T

DQS2T/CQ3T

DQS0T/CQ1T
I/O Bank 9 I/O Bank 8B I/O Bank 8 I/O Bank 8A I/O Bank 7
Transceiver Block (QL1)

DQS4R/CQ5R

I/O Bank 6
DQS2R/CQ3R

DQS0R/CQ1R
Cyclone IV GX Device
Transceiver Block (QL0)

DQS1R/CQ1R#

I/O Bank 5
DQS3R/CQ3R#

DQS5R/CQ5R#

I/O Bank 3B I/O Bank 3 I/O Bank 3A I/O Bank 4

DQS1B/CQ1B#

DQS3B/CQ3B#

DQS5B/CQ5B#

DQS4B/CQ5B

DQS2B/CQ3B

DQS0B/CQ1B

Note to Figure 7–2:

(1) The DQS, CQ, or CQ# pin locations in this diagram apply to all packages in Cyclone IV GX devices except devices in
169-pin FBGA and 324-pin FBGA.

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Chapter 7: External Memory Interfaces in Cyclone IV Devices 7–9
Cyclone IV Devices Memory Interfaces Pin Support

Figure 7–3 shows the location and numbering of the DQS, DQ, or CQ# pins in I/O banks
of the Cyclone IV GX device in the 324-pin FBGA package only.

Figure 7–3. DQS, CQ, or CQ# Pins for Cyclone IV GX Devices in the 324-Pin FBGA Package

DQS1T/CQ0T#

DQS3T/CQ1T#

DQS2T/CQ1T

DQS0T/CQ0T
I/O Bank 9 I/O Bank 8 I/O Bank 8A I/O Bank 7

DQS2R/CQ1R

I/O Bank 6
Transceiver Block (QL1)

DQS0R/CQ0R
Cyclone IV GX Device
324-pin FBGA Package
DQS1R/CQ0R#

I/O Bank 5
DQS3R/CQ1R#

I/O Bank 3 I/O Bank 3A I/O Bank 4

DQS1B/CQ0B#

DQS3B/CQ1B#

DQS2B/CQ1B

DQS0B/CQ0B

Figure 7–4 shows the location and numbering of the DQS, DQ, or CQ# pins in I/O
banks of the Cyclone IV GX device in the 169-pin FBGA package.

Figure 7–4. DQS, CQ, or CQ# Pins for Cyclone IV GX Devices in the 169-Pin FBGA Package
DQS1T/CQ0T#

DQS0T/CQ0T

I/O Bank 9 I/O Bank 8 I/O Bank 8A I/O Bank 7

I/O Bank 6

DQS0R/CQ0R
Transceiver Block (QL1)

Cyclone IV GX Device
169-pin FBGA Package
I/O Bank 5

DQS1R/CQ0R#

I/O Bank 3 I/O Bank 3A I/O Bank 4

DQS1B/CQ0B#

DQS0B/CQ0B

March 2016 Altera Corporation Cyclone IV Device Handbook,

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7–10 Chapter 7: External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Pin Support

Figure 7–5 shows the location and numbering of the DQS, DQ, or CQ# pins in the
Cyclone IV E device I/O banks.

Figure 7–5. DQS, CQ, or CQ# Pins in Cyclone IV E I/O Banks (1)

DQS1T/CQ1T#

DQS3T/CQ3T#

DQS5T/CQ5T#

DQS4T/CQ5T

DQS2T/CQ3T

DQS0T/CQ1T
I/O Bank 8 I/O Bank 7

DQS2L/CQ3L DQS2R/CQ3R

I/O Bank 6
I/O Bank 1
DQS0R/CQ1R
DQS0L/CQ1L
Cyclone IV E Device
DQS1R/CQ1R#
DQS1L/CQ1L#
I/O Bank 2

I/O Bank 5
DQS3L/CQ3L# DQS3R/CQ3R#

I/O Bank 3 I/O Bank 4

DQS3B/CQ3B#

DQS4B/CQ5B

DQS2B/CQ3B

DQS0B/CQ1B
DQS1B/CQ1B#

DQS5B/CQ5B#

Note to Figure 7–5:

(1) The DQS, CQ, or CQ# pin locations in this diagram apply to all packages in Cyclone IV E devices except devices in
144-pin EQFP.

Cyclone IV Device Handbook, March 2016 Altera Corporation

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Chapter 7: External Memory Interfaces in Cyclone IV Devices 7–11
Cyclone IV Devices Memory Interfaces Pin Support

Figure 7–6 shows the location and numbering of the DQS, DQ, or CQ# pins in I/O
banks of the Cyclone IV E device in the 144-pin EQFP and 164-pin MBGA packages.

Figure 7–6. DQS, CQ, or CQ# Pins for Cyclone IV E Devices in the 144-Pin EQFP and 164-pin
MBGA Packages

DQS1T/CQ1T#

DQS0T/CQ1T
I/O Bank 8 I/O Bank 7

DQS0L/CQ1L DQS0R/CQ1R

I/O Bank 6
I/O Bank 1

Cyclone IV E Devices
in 144-pin EQFP and
164-pin MBGA

I/O Bank 5
I/O Bank 2

DQS1L/CQ1L# DQS1R/CQ1R#

I/O Bank 3 I/O Bank 4

DQS1B/CQ1B#

DQS0B/CQ1B

In Cyclone IV devices, the ×9 mode uses the same DQ and DQS pins as the ×8 mode, and
one additional DQ pin that serves as a regular I/O pin in the ×8 mode. The ×18 mode
uses the same DQ and DQS pins as ×16 mode, with two additional DQ pins that serve as
regular I/O pins in the ×16 mode. Similarly, the ×36 mode uses the same DQ and DQS
pins as the ×32 mode, with four additional DQ pins that serve as regular I/O pins in
the ×32 mode. When not used as DQ or DQS pins, the memory interface pins are
available as regular I/O pins.

Optional Parity, DM, and Error Correction Coding Pins

Cyclone IV devices support parity in ×9, ×18, and ×36 modes. One parity bit is
available per eight bits of data pins. You can use any of the DQ pins for parity in
Cyclone IV devices because the parity pins are treated and configured similarly to DQ
pins.
DM pins are only required when writing to DDR2 and DDR SDRAM devices.
QDR II SRAM devices use the BWS# signal to select the byte to be written into
memory. A low signal on the DM or BWS# pin indicates the write is valid. Driving the
DM or BWS# pin high causes the memory to mask the DQ signals. Each group of DQS
and DQ signals has one DM pin. Similar to the DQ output signals, the DM signals are
clocked by the -90° shifted clock.

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Cyclone IV Devices Memory Interfaces Features

In Cyclone IV devices, the DM pins are preassigned in the device pinouts. The
Quartus II Fitter treats the DQ and DM pins in a DQS group equally for placement
purposes. The preassigned DQ and DM pins are the preferred pins to use.
Some DDR2 SDRAM and DDR SDRAM devices support error correction coding
(ECC), a method of detecting and automatically correcting errors in data
transmission. In 72-bit DDR2 or DDR SDRAM, there are eight ECC pins and 64 data
pins. Connect the DDR2 and DDR SDRAM ECC pins to a separate DQS or DQ group in
Cyclone IV devices. The memory controller needs additional logic to encode and
decode the ECC data.

Address and Control/Command Pins

The address signals and the control or command signals are typically sent at a single
data rate. You can use any of the user I/O pins on all I/O banks of Cyclone IV devices
to generate the address and control or command signals to the memory device.

1 Cyclone IV devices do not support QDR II SRAM in the burst length of two.

Memory Clock Pins

In DDR2 and DDR SDRAM memory interfaces, the memory clock signals (CK and
CK#) are used to capture the address signals and the control or command signals.
Similarly, QDR II SRAM devices use the write clocks (K and K#) to capture the
address and command signals. The CK/CK# and K/K# signals are generated to
resemble the write-data strobe using the DDIO registers in Cyclone IV devices.

1 CK/CK# pins must be placed on differential I/O pins (DIFFIO in Pin Planner) and in
the same bank or on the same side as the data pins. You can use either side of the
device for wraparound interfaces. As seen in the Pin Planner Pad View, CK0 cannot be
located in the same row and column pad group as any of the interfacing DQ pins.

f For more information about memory clock pin placement, refer to Volume 2: Device,
Pin, and Board Layout Guidelines of the External Memory Interface Handbook.

Cyclone IV Devices Memory Interfaces Features

This section discusses Cyclone IV memory interfaces, including DDR input registers,
DDR output registers, OCT, and phase-lock loops (PLLs).

DDR Input Registers

The DDR input registers are implemented with three internal logic element (LE)
registers for every DQ pin. These LE registers are located in the logic array block (LAB)
adjacent to the DDR input pin.

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Cyclone IV Devices Memory Interfaces Features

Figure 7–7 illustrates Cyclone IV DDR input registers.

Figure 7–7. Cyclone IV DDR Input Registers

DDR Input Registers in Cyclone IV Device

dataout_h LE DQ
Register

Input Register A I

neg_reg_out

dataout_l LE LE
Register Register

Register C I Input Register B I

Capture Clock
PLL

These DDR input registers are implemented in the core of devices. The DDR data is
first fed to two registers, input register AI and input register BI.
■ Input register AI captures the DDR data present during the rising edge of the clock
■ Input register BI captures the DDR data present during the falling edge of the clock
■ Register CI aligns the data before it is synchronized with the system clock
The data from the DDR input register is fed to two registers, sync_reg_h and
sync_reg_l, then the data is typically transferred to a FIFO block to synchronize the
two data streams to the rising edge of the system clock. Because the read-capture
clock is generated by the PLL, the read-data strobe signal (DQS or CQ) is not used
during read operation in Cyclone IV devices; hence, postamble is not a concern in this
case.

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Cyclone IV Devices Memory Interfaces Features

DDR Output Registers

A dedicated write DDIO block is implemented in the DDR output and output enable
paths.
Figure 7–8 shows how a Cyclone IV dedicated write DDIO block is implemented in
the I/O element (IOE) registers.

Figure 7–8. Cyclone IV Dedicated Write DDIO

DDR Output Enable Registers

Output Enable
IOE
Register

Output Enable
Register AOE
data1
data0

IOE
Register

Output Enable
Register BOE

DDR Output Registers

datain_l
IOE
Register
data0 DQ or DQS
Output Register AO
data1

datain_h
IOE
Register
-90° Shifted Clock
®
Output Register BO

The two DDR output registers are located in the I/O element (IOE) block. Two serial
data streams routed through datain_l and datain_h, are fed into two registers,
output register Ao and output register Bo, respectively, on the same clock edge.
The output from output register Ao is captured on the falling edge of the clock, while
the output from output register Bo is captured on the rising edge of the clock. The
registered outputs are multiplexed by the common clock to drive the DDR output pin
at twice the data rate.
The DDR output enable path has a similar structure to the DDR output path in the
IOE block. The second output enable register provides the write preamble for the DQS
strobe in DDR external memory interfaces. This active-low output enable register
extends the high-impedance state of the pin by half a clock cycle to provide the
external memory’s DQS write preamble time specification.

f For more information about Cyclone IV IOE registers, refer to the Cyclone IV Device
I/O Features chapter.

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Chapter 7: External Memory Interfaces in Cyclone IV Devices 7–15
Cyclone IV Devices Memory Interfaces Features

Figure 7–9 illustrates how the second output enable register extends the DQS
high-impedance state by half a clock cycle during a write operation.

Figure 7–9. Extending the OE Disable by Half a Clock Cycle for a Write Transaction (1)

System clock
(outclock for DQS)

OE for DQS Delay

(from logic array) 90 o
by Half
a Clock
Cycle
DQS Preamble Postamble

Write Clock
(outclock for DQ,
-90o phase shifted
from System Clock)
datain_h D0 D2
(from logic array)

datain_I
D1 D3
(from logic array)

OE for DQ
(from logic array)

DQ D0 D1 D2 D3

Note to Figure 7–9:

(1) The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the
Quartus II software implements the signal as an active high and automatically adds an inverter before the AOE register
D input.

OCT with Calibration

Cyclone IV devices support calibrated on-chip series termination (RS OCT) in both
vertical and horizontal I/O banks. To use the calibrated OCT, you must use the RUP
and RDN pins for each RS OCT control block (one for each side). You can use each
OCT calibration block to calibrate one type of termination with the same VCCIO for
that given side.

f For more information about the Cyclone IV devices OCT calibration block, refer to the
Cyclone IV Device I/O Features chapter.

PLL
When interfacing with external memory, the PLL is used to generate the memory
system clock, the write clock, the capture clock and the logic-core clock. The system
clock generates the DQS write signals, commands, and addresses. The write-clock is
shifted by -90° from the system clock and generates the DQ signals during writes. You
can use the PLL reconfiguration feature to calibrate the read-capture phase shift to
balance the setup and hold margins.

1 The PLL is instantiated in the ALTMEMPHY megafunction. All outputs of the PLL are
used when the ALTMEMPHY megafunction is instantiated to interface with external
memories. PLL reconfiguration is used in the ALTMEMPHY megafunction to
calibrate and track the read-capture phase to maintain the optimum margin.

f For more information about usage of PLL outputs by the ALTMEMPHY

megafunction, refer to the External Memory Interface Handbook.

March 2016 Altera Corporation Cyclone IV Device Handbook,

Volume 1
7–16 Chapter 7: External Memory Interfaces in Cyclone IV Devices
Document Revision History

f For more information about Cyclone IV PLL, refer to the Clock Networks and PLLs in
Cyclone IV Devices chapter.

Document Revision History

Table 7–3 lists the revision history for this chapter.

Table 7–3. Document Revision History

Date Version Changes
■ Updated Table 7–1 to remove support for the N148 package.
March 2016 2.6 ■ Updated note (1) in Figure 7–2 to remove support for the N148 package.
■ Updated Figure 7–4 to remove support for the N148 package.
May 2013 2.5 Updated Table 7–2 to add new device options and packages.
February 2013 2.4 Updated Table 7–2 to add new device options and packages.
October 2012 2.3 Updated Table 7–1 and Table 7–2.
■ Updated for the Quartus II software version 10.1 release.
■ Added Cyclone IV E new device package information.
December 2010 2.2
■ Updated Table 7–2.
■ Minor text edits.
November 2010 2.1 Updated “Data and Data Clock/Strobe Pins” section.
■ Added Cyclone IV E devices information for the Quartus II software version 9.1 SP1
release.
February 2010 2.0 ■ Updated Table 7–1.
■ Added Table 7–2.
■ Added Figure 7–5 and Figure 7–6.
November 2009 1.0 Initial release.

Cyclone IV Device Handbook, March 2016 Altera Corporation

Volume 1