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Computer Architecture & Organization(1)

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Computer Architecture & Organization(1)

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2022ece.r109
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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Code:CS20AOE502 R 20

B.Tech III Year I Semester Regular& Supply Examinations January - 2024


COMPUTER ARCHITECTURE & ORGANIZATION
(Electronics & Communication Engineering)
Time: 3 hrs. Max Marks: 60
PART-A
(Compulsory Question)
1. Answer the following 05 x 02 = 10 Marks

a) List different types of instructions. 2M


b) Outline the purpose of address sequencer. 2M
c) What are the 2 IEEE standards for floating point numbers? 2M
d) What is the purpose of I/O interface? 2M
e) Compare CISC and RISC. 2M
PART-B
Answer All five Units 05 x 10 = 50 Marks
UNIT-I
2. a) Explain Register transfer language notation with the suitable example. 5M
b) Discuss about Register transfer with examples. 5M
OR
3. a) Explain common bus constructed using multiplexers. 5M
b) Discuss about the various types of addressing modes with examples in detail. 5M
UNIT-II
4. a) Illustrate the selection of address for control memory with a neat sketch. 5M
b) Compare hardwired control and micro programmed control. 5M
OR
5. a) Explain direct and indirect addressing modes instructions with examples. 5M
b) Describe the micro programmed control organization with diagram. 5M
UNIT-III
6. a) Illustrate addition and subtraction of two floating point binary numbers with a flow 5M
chart.
b) Describe Explain about booth multiplication with example. 5M
OR
7. a) Illustrate addition and subtraction of fixed point binary numbers with flow chart. 5M
b) Outline registers used in floating point arithmetic operations. 5M
UNIT-IV
8. a) Describe the different mapping procedures in organization of cache memory. 5M
b) Compare between Isolated I/O and Memory-Mapped I/O. 5M
OR
9. a) Summarize and list out memory hierarchy according to the speed and size. 5M
b) Explain the dairy chain interrupt with suitable diagrams. 5M

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Code:CS20AOE502 R 20
UNIT-V
10. a) What is instruction pipelining? What are the conflicts that occurred during 5M
instruction pipelining?
b) Describe the data and control path techniques in pipelining. 5M
OR
11. a) Explain inter processor communication and synchronization in a shared 5M
multiprocessor environment.
b) Define the Multiprocessor. Explain its characteristics. 5M
*****

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