Notes_PE_Unit 06
Notes_PE_Unit 06
6.1 Three phase VSI Inverter for 1200 and 1800 modes of operation
In this article, we will discuss 3 Phase Inverter Circuit which is used as DC to 3 phase AC
converter. Do remember that, even in the modern days achieving a completely sinusoidal
waveform for varying loads is extremely difficult and is not practical. So here we will discuss the
working of an ideal three-phase converter circuit neglecting all the issues related to practical 3
phase inverter.
Below is a three-phase inverter circuit diagram designed using thyristors & diode (for voltage
spike protection)
And below is a three-phase inverter circuit diagram designed using only switches. As you can
see this six mechanical switch setup is more useful in understanding the 3 phase inverter
working than the cumbersome thyristor circuit.
What we will do here is open & symmetrically closes these six switches to get the three-phase
voltage output for the resistive load. There are two possible ways for triggering the switches to
achieve the desired result, one in which switches conduct for 180º and another in which
switches only conduct for 120º. Let us discuss each pattern below:
The ideal circuit is drawn before it can be divided into three segments namely segment one,
segment two & segment three and we will use these notational in the later section of the
article. Segment one consists of a pair of switches S1&S2, segment two consists of switching pair
S3 &S4 and segment three consists of switching pair S5&S6. At any given time both the switches
in the same segment should never be closed as it leads to battery short circuits failing the entire
setup, so this scenario should be avoided at all times.
Now let’s start switching sequence by closing the switch S1 in the first segment of the ideal
circuit and let’s name the start as 0º. Since the selected time of conduction is 180º the switch S1
will be closed from 0º to 180º.
But after 120º of the first phase, the second phase will also have a positive cycle as seen in the
three-phase voltage graph, so switch S3 will be closed after S1. This S3 will also be kept closed
for another 180º. So S3 will be closed from 120º to 300º and it will be open only after 300º.
Similarly, the third phase also has a positive cycle after 120º of second phase positive cycle, as
shown in the graph at the beginning of the article. So the switch S5 will be closed after 120º S3
closing i.e. 240º. Once the switch is closed it will be kept closed for coming 180º before being
opened, with that the S5 will be closed from 240º to 60º (second cycle).
Up until now, all we did was assume that’s the conduction is done once the top layer switches
are closed but for current flow from the circuit must be completed. Also, do remember that both
switches in the same segment should never be in the closed at the same time, so if one switch is
closed then another must be open.
For satisfying the above both conditions, we will close S2, S4& S6 in a predetermined order. So
only after S1 gets opened we will have to close S2. Similarly, S4 will be closed after S3 gets
opened at 300º and in the same way S6 will be closed after S5 completes the conduction cycle.
This cycle of switching between switches of the same segment can be seen below figure. Here S2
followsS1, S4 follows S3 and S6 follows S5.
By following this symmetrical switching we can achieve the desired three-phase voltage
represented in the graph. If we fill in the beginning switching sequence in the above table we will
have a complete switching pattern for 180º conduction mode as below.
From 0-60: S1, S4 & S5 are closed and the remaining three switches are opened.
From 60-120: S1, S4 & S6 are closed and the remaining three switches are opened.
From 120-180: S1, S3&S6 are closed and the remaining three switches are opened.
And the sequence of switching goes on like that. Now let us draw the simplified circuit for each
step to better understand the current flow and voltage parameters.
Step1: (for 0-60) S1, S4&S5 are closed while the remaining three switches are open. In such a
case, the simplified circuit can be as shown below.
Vab = Vao – V bo = Vs
Step2: (for 60 to 120) S1, S4&S6 are closed while the remaining three switches are open. In such
a case, the simplified circuit can be as shown below.
Step3: (for 120 to 180) S1, S3&S6 are closed while the remaining three switches are open. In
such a case, the simplified circuit can be drawn as below.
Vab = Vao – V bo = 0
Similarly, we can derive the phase voltages and line voltages for the next steps in the sequence.
And it can be shown as the figure given below:
The 120º mode is similar to 180º at all aspects except the closing time of each switch is reduced
to 120, which were 180 before.
As usual, let’s start switching sequence by closing the switch S1 in the first segment and be the
start number to 0º. Since the selected time of conduction is 120º the switch S1 will be opened
after 120º, so the S1 was closed from 0º to 120º.
Since half cycle of the sinusoidal signal goes from 0 to 180º, for the remaining time S1 will be
open and is represented by the gray area above.
Now after 120º of the first phase, the second phase will also have a positive cycle as mentioned
before, so switch S3 will be closed after S1. This S3 will also be kept closed for another 120º. So
S3 will be closed from 120º to 240º.
Similarly, the third phase also has a positive cycle after 120º of the second phase positive cycle
so the switch S5 will be closed after 120º of S3 closing. Once the switch is closed, it will be kept
closed for coming 120º before being opened and with that, the switch S5 will be closed from
240º to 360º
This cycle of symmetrical switching will be continued for achieving the desired three-phase
voltage. If we fill in the beginning and ending switching sequence in the above table we will have
a complete switching pattern for 120º conduction mode as below.
From 0-60: S1&S4 are closed while remaining switches are opened.
From 60-120: S1 &S6 are closed while remaining switches are opened.
From 180-240: S2&S3 are closed while remaining switches are opened
From 240-300: S2&S5 are closed while remaining switches are opened
From 300-360: S4&S5 are closed while remaining switches are opened
And this sequence of steps goes on like that. Now let us draw the simplified circuit for each step
to better understand the current flow and voltage parameters of the 3 Phase Inverter circuit.
Step1: (for 0-60) S1, S4 are closed while the remaining four switches are open. In such a case,
the simplified circuit can be shown as below.
Vab = Vao – V bo = Vs
Step2: (for 60 to 120) S1 &S6 are closed while the remaining switches are open. In such a case,
the simplified circuit can be shown as below.
Step3: (for 120 to 180) S3&S6 are closed while the remaining switches are open. In such a case,
the simplified circuit can be shown as below.
So for 120 to 180: Vao =0, Vbo= Vs/2 & Vco = -Vs/2
Similarly, we can derive the phase voltages and line voltages for the next upcoming steps. And if
we draw a graph for all the steps then we will get something like below.
It can be seen in the output graphs of both 180º and 120º switching cases that we have achieved
an alternating three-phase voltage at the three output terminals. Although the output waveform
is not a pure sine wave, it did resemble the three-phase voltage waveform. This is a simple ideal
circuit and approximated waveform for understanding 3 phase inverter working. You can design
a working model based on this theory using thyristors, switching, control, and protection
circuitry.
When load is connected at the output of inverter, the output voltage of inverter is
controlled by internal control of inverter.
There are two or more than two inverters connected in series in this method.
The output of the inverter is connected with primary winding of the transformer whereas
the load is connected to the secondary winding of the transformer.
Let the secondary voltage of the transformer is V1 and V2 , therefore the load voltage is
V = √ ( V1 )2 + ( V2 )2 + 2V1V2sinα
Where α = firing angle of inverter
If α = 0o
V = √ ( V1 )2 + ( V2 )2 + 2V1V2
= ( V1 + V2 )2
OR
( V1 + V2 )
If α = π
V = √ ( V1 )2 + ( V2 )2 – 2V1V2
= ( V1 – V2 )2
OR
V = ( V1 – V2 )
The load voltage can be changed by changing the firing angle of the inverter.
The constant DC input voltage is applied at the input of the inverter and output voltage is
controlled by switching semiconductor device of the inverter in this method.
As the low order harmonics ( 3rd, 5th ) reduces whereas higher order harmonics ( 7th ,
9th and 11th ) are filter out, less requirement of filter.
The output voltage of the inverter can be controlled by controlling width of pulse.
Figure A shows the gate signal and output voltage waveform for single phase full bridge
inverter.
The width of gate pulse can be varies from 0o to 180o by controlling the reference signal
from 0 to VR.
The frequency of the output voltage depends upon frequency of reference signal.
M = VR / VC
The analysis of waveform shown in the figure A is done by fourier series.
The output voltage becomes maximum when the width of pulse becomes π radian.
VL = 4VDC / π ............................................(1)
RMS output voltage
VRMS = VDC √ d / π....................................(2)
And maximum value of nth harmonic
VLn = 4VDC / nπ ( Sin nd / 2 ) ..................(3)
From equation (1) and (3)
VLn / VL = Sin ( nd / 2) / n ......................(4)
The graphical representation of pulse width in degree ( x – axis ) and n = 1, 3, 5 and 7 ( y –
axis ) is shown in the figure B.
When a value of the fundamental component becomes equal to 0.143, the third, fifth
and seventh harmonics becomes equal.
This will conclude the higher harmonics remains present when the output voltage is low.
These gate pulses are used to control output voltage of inverter as well as reduce
harmonics.
The magnitude and width of the pulses are equal in this method.
The reference signal and higher frequencies carrier signals are compared in this method
in order to generate more than one gatting pulses.
The number of gate pulses depends upon carrier frequencies whereas the output voltage
depend frequencies of reference signal.
From figure J,
Carrier frequency = fC in Hz
Reference frequency = fR in Hz
1 / fC = π / 3..................................................(5)
OR
TC = π / 3
Similarly
1 / 2fR = 1 / π .............................................(6)
OR
TR = π / 2
Number of pulses per half cycle ( NP ) = Length of half cycle reference signal / Length of one
cycle triangular waveform
= ( f R / 2 ) / ( 1 / fC )
NP = fC / 2 fR
Number of generated pulses NP = ( 3 / π ) × π [ from equation (5) and (6) ]
=3
The RMS voltage when pulse width is equal to d
VRMS = VDC √ ( NP × d / π )
As the number of pulses increases in the each half cycle, lower order harmonics reduces
but higher order harmonics increases.
It is to be noted that the switching losses of the semiconductor devices increases as there
are more number of pulses per half cycle.
The width of pulse in the SINPWM is not equal due to reference signal is taken as
sinusoidal waveform.
The width of gate pulse is determined by intersect point of the sinusoidal waveform and
triangular waveform.
The frequency of inverter output voltage depends upon frequency of reference signal
fR and amplitude of reference signal VR controls the modulation index ( M ).
The number of pulses per half cycle when the amplitude of triangular waveform becomes
maximum and sinusoidal waveform becomes zero.
NP = fC / 2 fR
Where
fC = Carrier wave frequency = 3 / π
fR = Reference wave frequency = 1 / 2π
Therefore
NP = ( 3 / π ) × ( 2π / 2 ) = 3
The number of pulses per half cycle when the amplitude of triangular waveform and
sinusoidal becomes zero at same time.
NP = ( fC / 2 fR – 1 ) = 2
When the value of modulation index is less than one, the maximum harmonic number in
the output voltage is
fC / fR ± 1
OR
2NP ± 1
Where NP = Number of pulses per half cycle
As the number of pulses per half cycle increases, the higher order harmonics also
increases.
Let NP = 4, it will generates 7th harmonic and 9thharmonic but higher order harmonics are
easily filtered out.
As the number of pulses increases per half cycle, the switching losses also increase and it
will affect the efficiency of inverter.
When the modulation index is greater than one, lower order harmonics induces in the
output of the inverter.
Neutral Point Clamped (NPC) inverters are a family of multilevel power converters that are
characterized by the use of clamping diodes for guaranteeing the proper voltage sharing across
the power switches. NPC inverters were simultaneously introduced by Baker [1] and Nabae et. al
[2] in 1981. Today, they remain the most well-known and widespread multilevel converter
topology, as they offer very attractive performance with limited complexity.
Neutral Point Clamped inverters offer superior waveform quality (to two-level inverters), leading
to reduced filtering requirements. They are often present in medium voltage applications, where
their superior blocking voltage capability is also an essential requirement. However, the
industrial use of NPC-type inverters is mostly limited to three-level topologies, due to the
complex mechanical arrangement of the power devices with a higher number of levels (presence
of non-symmetrical elements).
Each leg of the NPC inverter has 4 transistors that can be controlled, giving 2 4=16 total possible
states. However, only 3 of these states are feasible, since others create short-circuits on the DC-
link. The three feasible states give three different output voltages:
VDC/2
−VDC/2
0V
The table below shows the conductivity of transistors to get the desired output voltage:
OFF ON ON OFF 0V 0
Numerous modulation strategies have been proposed for Neutral Point Clamped Inverters.
Among them, the selection of the optimum strategy is influenced by numerous factors, such as i)
balancing of the neutral point voltage, ii) minimization of the total losses, iii) distribution of
losses among the power switches, or iv) AC-side harmonic performance.
This example focuses on the basic implementation of two common techniques, namely carrier-
based PWM (
CB-PWM) as well as space vector modulation (
SV-PWM). More subtle implementations can be considered, which typically also integrate
balancing considerations for the DC midpoint voltage. Interesting information can notably be
found in [1-2] as well as in
TN129.
Carrier-based PWM
This technique is relatively simple to implement. Its principle consists in taking the desired
inverter voltages (sometimes also designated as electromotive forces) Eabc∗, normalizing and
comparing them to two triangular carriers in order to generate the states of the four transistors
of each leg. The normalized voltages have to be in the form:
Eabc,norm∗=m⋅sin(ωt+ϕ)
m=Eabc,peak∗Vdc/2≤1
For each phase, the normalized voltage is compared to the upper carrier, in order to get the
state of the transistor T1, and is also compared to the lower carrier to get the state of the
transistor T2. The states of the transistors T3 and T4 are the complementaries of T1 and T2
respectively.
Typical carrier-based PWM waveforms for a three-level Neutral Point Clamped Inverter
Fig. 1 shows one phase of a three-level flying capacitor inverter. Each switch S1, S2, S21 and S11
consist of a power semiconductor switch and an anti-parallel diode. The switches Sl and S11 are
complementary to each other. Thus if Sl is ON, S11 is OFF and vice-versa. Similarly the switches
S2 and S21 are complementary. Each capacitor shown in the figure is of equal voltage rating. The
capacitors C1 constitute the main dc-link. whose voltage is required to be regulated externally.
Therefor either a battery of suitable rating is connected in place of CI,or C1, without the battery
connected across it is regulated around a reference de-link voltage using the real power ex-
change from the line as will be discussed in Section III. For a 3-phase inverter two more phases of
the same configuration are coupled to the same de-link. C2 is the flying capacitor that provides
the multilevel voltage ability to the converter. The flying capacitor of one phase is independent
from those of other phases. If the voltage Vcl is Vdc, then the voltage Ve2 will be Vdcl2.
For any initial state of flying capacitor voltage the inverter output voltage is given by,
In Fig. 1 and Equation (1), the switching states S1 and S2 take the value 1 if the corresponding
switch is conducting and otherwise. Based on (1), the switch combinations given in Table I are
used to synthesize the output voltage Van of phase a with respect to the neutral point n. Table I
also indicates the states of the flying capacitor corresponding to the switching combinations
chosen. The state NC indicates that the capacitor neither charges nor discharges in this mode.
The states + and denote the charging and discharging respectively of the corresponding
capacitors. The switching states given are for the positive half cycle of the current waveform
(indicated as out- going current ia in Fig. 1). The capacitor states (+ and -) will reverse for the
negative half cycle of the current.
The output voltage for an n-Ievel inverter can similarly be defined. In general, an n-Ievel FCMLI
requires (n-I) pairs of power semiconductor devices and (n-I)x(n-2)/2 clamping capacitors per
phase leg in addition to (n-I) main de bus capacitors provided all the capacitors are of equal
value. The number of capacitor requirements can be reduced by sizing the capacitors in a single
clamping leg as an equivalent capacitor. The size of the voltage increment between two
consecutive clamping legs defines the size of voltage steps in the output waveform. The voltage
of the innermost clamping leg (e.g. C2 in Fig. 1) clamping the innermost two devices is Vdj(n-I).
The voltage of the next innermost clamping leg will be Vdj(n-I) + Vdj(n-I) = 2Vdj(n-I) and so on.
Thus, each next clamping leg will have the voltage increment of Vdj(n-I) from its immediate inner
one. The voltage stress across each capacitor is Vdj(n-I). The voltage levels and the arrangements
NC
of the flying capacitors in the FCMLI structure assure that the voltage stress across each main
device is same and is equal to Vdj(n-I). The line-to-line output voltage of the inverter varies from
+Vdcto - Vdcand has (2n-I) levels in the output, while the phase voltage varies from +Vdc/2to -
Vdj2 with n-Ievels. It can be seen from Table I that the structure offers two switching
combinations for Van = O. As such redundancies are available, one can choose a preferential
switching state that
will help in maintaining the capacitor voltages constant. B. Modulation scheme Of the various
strategies developed to improve the output voltage and reduce the harmonics, sinusoidal pulse
width modulation (SPWM) strategy is employed here. In this method for an n-Ievel inverter, (n-I)
carrier waves are compared with a controlled sinusoidal modulating signal. All of the carriers
have the same frequency and the same amplitude. The outputs of each comparator for each
phase are combined to produce the corresponding decision signals for the switches to synthe-
size the output voltage of that phase. The output signal of the comparator resembles with the
output voltage waveform of the inverter and decides the voltage level that must be generated at
a particular instant, as evident from Fig. 2.
where Am is the amplitude of the modulating signal and Ac is that of one carrier wave (peak to
peak). Some researches have been reported about the relations between the phases and
frequencies of the carrier waves and the shape of the modulating signal to reduce the output
voltage harmonics of the multilevel inverters. Here, the frequency of the carrier waves are taken
nc times of the modulating signal frequency. n; is an integer in multiples of three so that triplen
harmonic cancellation takes place across the three-phase inverter load.
One of the basic and well-known topologies among all multilevel inverters is Cascaded H-Bridge
Multilevel Inverter. It can be used for both single and three phase conversion. It uses H-Bridge
including switches and diodes.
At least three voltage levels are required for a multilevel inverter. This can be accomplished by a
single H-Bridge unit in Cascaded H-Bridge Multilevel Inverter. To keep the discussion snappy and
clear I will go with the major points of this topology and also its advantages and disadvantages
compared to other topologies.
H-Bridge Cell
Each H-Bridge Cell consists of four switches and four diodes as shown in the picture.
Like every H-Bridge, different combinations of switch positions determine different voltages
such as V+, V- and 0.
Two switching combinations are present for 0 volts.
S1 and S2 are connected to positive voltage and S3 and S4 are connected to negative
voltage.
Single Phase Multilevel Inverter
The number of output levels from a multilevel inverter depends upon the number of
separate DC sources attached to it.
The relation is m=2s+1
All the outputs from H-Bridges should be quarter symmetric to generate a sin like wave.
No even harmonics are present.
Three-Phase Multilevel Inverter
Three-phase Multilevel Inverter is simply like three single phase inverters connected in wye
configuration. Three H-Bridges are connected together.
Delta configuration can also be used.
Maximum number of line voltages is 2m+1 where m=no. of phase voltages.
Triple harmonics are eliminated themselves.
Real Time Switching
In ideal cases the switching time is considered zero and the switching devices turn on and off as
soon as you command. But in real time application, switching time is an important phenomenon.
To avoid this Blanking time is introduced. The switch turns off just immediately, but the other
switch turns on after a certain delay.
Separate DC Source
One of the major issues with Cascaded H-Bridge Multilevel Inverters is that we need separate DC
sources with each leg. Well it might look that separate DC source will create a mess or increase
the components, but it is fairly necessary. Because same DC sources can give multiple
configurations that result in short circuit.
However this issue has also been resolved. Now lesser number of DC sources can be used and
SDC topology has also been proposed.
As the name suggests this multilevel inverter uses full H-Bridges connected is series to produce
inverted AC from separate DC sources. These DC sources can be any natural resource such as
sunlight or wind energy or anything.
1. Low cost
2. Low maintenance
3. Simple construction
4. Reliability and high efficiency
There are following methods of speed control of three phase induction motor.
The output torque of the three phase induction motor is directly proportional to square
of supply voltage for a given slip.
The torque – slip characteristics of three phase induction motor is shown in figure A.
As the supply voltage increases for a given constant torque, the slip decreases.
T α sV2 / R
Where
T = Torque
R = Rotor resistance and
s = Slip
There is one resistor connected between stator terminal and supply voltage.
The speed control of the motor is achieved by adjusting the resistor but there are higher
heat losses in this method and eventually the efficiency decreases.
If the speed control of the induction motor is done by thyristor control, it will result in
low losses, high efficiency, less weight and smooth control.
T α I22 R2 / s
The stator current of the induction motor is sum of magnetizing current and reflected
rotor current. If the magnetizing current is neglected at very low voltage
T α I12 R2 / s
The stator and rotor current is inversely proportional to √ R2 for a given constant torque.
I1 α I2 α √ ( s / R2 )
Therefore we conclude that rotor resistance play important role to determine rotor
current.
The squirrel cage induction motor draws high current particularly at starting and low
speed.
The stator voltage control method is applicable for small and medium HP induction
motor.
The stator voltage is adjusted by controlling the firing angle of two anti parallel SCRs.
The voltage and current waveform gets distorted particularly at low speed.
This method is rarely used in the industries because the induction motor draws heavy
current from the supply.
Ns = 120f / P
Where
f = Supply frequency
P = Number of poles and
Ns = Synchronous speed
The speed of the three phase induction motor can be changed from above or below
normal speed by changing in the frequency.
The ratio of voltage to frequency is kept constant in order to keep flux constant in the
three phase induction motor.
The air gap flux of the induction motor increases if the frequency decreases and voltage is
kept constant.
This will result in saturation of the core and magnetizing current and stator losses
increases. Therefore the motor efficiency decreases.
If the supply frequency increases (or flux decreases) in the three phase induction motor,
it affects the torque.
The supply voltage should not increase beyond certain limit in order to consider
insulation of the stator winding.
If the speed control of the induction motor is done by frequency, the ratio of voltage to
frequency must be constant.
There are several methods to control speed of induction motor by variable voltage and
variable frequency ( Figure A ).