A High-performance Universal Miniature

Radar System
Ting Jin*, Hong-Xian Wang∗, Hong-Wei Liu*
* National Laboratory of Radar Signal Processing, XiDian University, Xi’an, China, [email protected]

Abstract: This paper proposes the design and realization of a Vehicle), miniaturization is necessary. Therefore, the detailed
high-performance universal miniature radar system. It presents technology at board level such as the board layout or PCB
a well solution to the main challenges of the radar system routing need to be specially designed.
including extremely huge data flow and calculating burden, Dealing with the issues mentioned above, we discuss the
the traditional custom-built pattern of radar system, and the method of designing and realizing a kind of high-performance
strict limitations for the size, weight and power consumption universal miniature radar system in this paper.
of the airborne or space-borne real-time Synthetic Aperture
Radar(SAR) signal processing systems. The system has II. THEORY ANALYSIS OF SYSTEM STRUCTURE
showed the virtues of standardization, modularization, A. Module of Parallel Structure
stability, reconstruction, good adaptability due to the
Although the chip technology and processing power have
combined application of the distributed parallel architecture,
increasingly enhanced, single chip still cannot satisfy the
latest interconnection standard and processor. By the
operation requirements of 10GFLOPS or even 100GFLOPS in
successful application cases of airborne SAR/GMTI and
the real-time imaging cases. Thus the parallel processing
space-borne imaging, its high-performance universality and
would be imperative for the sake of the high-performance. The
miniature property could be adequately proved.
parallel processing structure, which is mainly embodied in the
Keywords: High-performance; miniature; universal; radar
chip-level and system-level parallelism, directly decides the
system; distributed parallel processing
performance of the system. The most common two kinds of
I. INTRODUCTION the parallel processing are shown as followed. (P(processor),
M(Memory))
With the enhanced quality and widespread application of the P P P
radar system including geological mapping, marine research, P P P
Bus/
military surveillance etc., higher and stricter requirements have Switch M M M
been put forward.
M M I/O
High-performance radar system is urgently needed by the Network

large scale of data flow and calculation burden, especially in Fig. 1. Shared Bus Sturcture&Distrubuted Bus Sturcture
the real-time signal processing cases. The selection of chips,
the design of processing structure and the realization of In the shared bus structure, every processor could equally
interconnection framework would all directly influence the visit all the space of the shared memory through high speed
system performance. bus. Concretely, the shared memory could be visited by all the
To achieve the universality, one is breaking the bondage of processors synchronously. It fits for the slim granularity,
traditional mode that the design of radar system is subject to small-scale parallel processing. However, along with the
the algorithm. The other is building the universal radar system increasing number of processors and the frequent data
to lower the design cost, cycle. From the software aspect, exchange among processors, bus competition would cause the
universality means providing a hardware platform, on which bottleneck for the data communication. Meanwhile, the bus is
diverse arithmetic complexity and different data granularity lack of scalability, once it has been made, it is hard to be
could perform well. From the hardware aspect, by the way of expanded.
modularized design, universality could be obtained. Namely, In distributed parallel structure, every processing node has
we could design and optimize every unit of radar system such physical distributed memories. And multiple processing nodes
as the signal processing part, AD/DA part, storage part, could form the larger processing scale through the
respectively. Then according to the different function combination of the network which have the high
characteristics and design ideas, diverse radar system could be communication bandwidth and low lingering customized
finished by extending, reconstructing or updating these communication link. The distributed parallel structure adopts
modularized units. The modularized design is benefit for to carry through wide granularity processing and could
system universality, extension, flexibility and reconstruction, flexibly design system framework, conveniently expand or cut
especially for saving the cost and cycle of design substantially. processors. In fact, the large-scale distributed system in the
Limited by requirements on the weight, volume and power Fig.2 may consist of multiple independent distributed
consumption of the special application platform such as the systems[7].
space-borne, airborne, especially the UAV(unmanned Aerial
 P P P P P P precision, the DA module in the system could reach
Network Network
5GSPS (2 channels) 14bits.

Network

Network Network

P P P P P P
Fig. 3. AD Board&Storage Board
Fig. 2. Large-scale Distribute System Structure
B. Storage Subsystem
From the analysis above, it is obvious that the distributed There are 2 Storage Board, each of them has 1GB/s storage
parallel structure could meet the demands of scalability, rate and 2T storage capability. These key features enable the
flexibly, high-performance better. So our system is built based radar system better used in plenty application cases.
on the distributed parallel structure.
C. Signal Processing Unit
B. Interconnection Structure
x DSP+FPGA Structure
In the large-scale complex distributed parallel structure
systems, multiple data streams such as the high-speed original In radar signal processing system, there are always
data streams, pre-processing data streams and the resulting some huge but relatively simple operations such as
data streams need real-time transactions. Meanwhile, diverse multiply, accumulation or FFT. Their strict demand of
synchronization and control signal flows among multiple tasks the processing speed and the computation complexity
are suitable to be realized by the FPGA.
or processors are existed. Their different transmission
Correspondingly, as for the complex arithmetic
bandwidth and delay put forward plenty of requirements to the implementation, it adapts to be realized by DSP chip
interconnection structure. which is in high operation speed, has flexible manner
Therefore, in order to solve the issues of the system of searching for address and powerful correspondence
multiple processing nodes, the high-speed serial data mechanism. Therefore, we choose the DSP+FPGA
interconnection and a variety of data streams, signal flows, we structure to finish the signal processing. FPGA is
proposes a distributed system architecture based on VPX. It responsible for the pre-processing, DSP accomplishes
has the bandwidth up to 6.25GB/s, uses the multi-switched most part of the high-level calculating.
network structure, and supports the modules that are not
compatible with various manufactures in engineering. Its x Processing Capability
appearance is of great importance for the development of the We selects TMS320C6678 as the basic processing
radar system. node in the processing element, which is a high
performance fixed-point and floating–point DSP based
III. SYSTEM STRUCTURE on the C66x series. It integrates eight C66x cores into a
The high-performance miniature universal radar system device, with each core running at a speed up to
consists of digital processing units which include the signal 1.25GHz, so the device can reach a peak performance
acquisition (AD) and storing module, signal processing of 320GMACS or 160GFLOPS[3]. As coprocessor, we
module, waveform generating element(DA), power-supply selects the large scaled FPGA V6 series XC6VLX240T
module and system console. Meanwhile, there are diverse of which is produced by Xilinx Inc. It can integrate 768
data communication network such as high-speed serial data dedicated multiplier. A single signal processing plate
switching network, strict synchronization timing buses, low consists of 2 pieces of DSP, each of them has 2GB
DDR3 memory storage power.
latency real-time control signal transfer network, etc. The
entire system hardware boards use 3U VPX standard (100mm
by 160mm).
Moreover, the diverse functional module are centrally
mapping to the different board obeying the principle of
modularization and reconfiguration. It makes the updating and Fig. 4. Signal Processign Board
reconstructing of the system easier than ever.
D. Multi-layer Interconnectin
A. AD/DA high frenquency module
Though system-level high speed serial networks, rich
x In the ADC module, there are 2 pieces of AD , each of interfaces of the processing nodes, the synchronization timing,
them could reach 1.8GSPS(1 channel ), 3.6GSPS(2 control bus and the external interfaces connecting to the RF
channels). Therefore, as for the AD module, it could component or PC host, the radar system comprises different
reach 7.2GSPS(4 channels) 12bits precision totally to layer networks. The multi-layer interconnection satisfies the
achieve the system data sampling and collection. corresponding transmission requirements of different type data
x In the DAC module, it presents 2 pieces of DA which streams and the instruction flows.
are responsible for waveform generation, each of them
has transmission rate up to 2.5GSPS and 14bits
 PC Main Their sound cooperation guarantees the entire system to be in
Controller RS422 Bus ideal state and to work together at the same pace.
GbE
In general, the multi-layer interconnection provides an
FPGA1 DA excellent solution to the complex connection needs.
High
h Speed
S GPIO Meanwhile, it guarantees the realization of the
Interface Bo
B
SRIO&PCIE
Board
oard
d
GbE
high-performance universal miniature radar system.

GPIO GPIO
E. Power subsystem
High
g Speed
S d High
Hi h Speed
S d G
Gb
GbE
High
i h Speed
S d GbE
Gb High
Hi h Speed
S
DSP
DSP
P DSP
D
DSSP DSP
DSP DSP
D SP FPGA0
GA
The power subsystem provides the system stable,
Analog Sampling
Interface
AD FPGA0
PGA
M M M M
configurable, multiple power supply, which could not only
M M M
Network Sync
y Network Sync y Network Sync
y Network Sync
y
assure the system operation normal, but also could be easily
AD Board
rd
d Processing
Processi
P
Pro siiingg P
Board
B
Processing
Pro
ro
occcessin
o
Bo
ingg
oard
Board
S orage
St
Storage
Board
d
e
adjusted by the software programming according to different
Control Bus
application cases.
F. Display and Console software
Synchronization Timing Bus
In order to achieve the result display and console, related soft
Fig. 5. Structrue of Radar System platforms have been designed.

The task of the connection to the RF components is

performed by the RS422 bus connected with AD module and
the analog sampling interface connected with DA module.
Likewise, the communication through the GbE bus between Fig. 6. Display&Controlling Software
the FPGA1 on the interface board and the PC could implement
the human-computer interactions and rapid display of the IV. OTHER DESIGN
processing results such as the real-time SAR/GMTI image,
A. Heat Dissipation Design
GMTI detection result, etc.
The configurable high-speed serial RadipIO(6. 25Gbps) and Both cooler heat conductivity and forced-air-cool are used
PCIE(5Gbps) networks are mainly used to implement the for the heat dissipation design. In addition, experiments
transaction of the original data, pre-processing data, resulting have shown that the cooler can bear vibration and
data and control instructions. It supplies the sufficient ruggedize the system boards.
bandwidth for processing elements and storages. As shown in
Fig.5, every module in the system including the storage
module, signal processing module, AD/DA module connects
to the FPGA1(named as Link Switch) on the interface board
through SRIO, PCIE. This makes the data among every
module of the system could be exchanged through the SRIO Fig. 7. Systme Heat Dissipation Design
and PCIE networks under the control of Link Switch. At the
same time, main controlling module could totally realize the B. Assistant Debugging Software
controlling on every module of the system through this layer With the purpose of simplifying debugging and accelerating
of interconnection. development process, we have also written a series of assistant
The DSP TMS320C6678 has rich peripheral interfaces, debug software tools.
which ensure flexible data transmission whether among the
board or between the boards. Apart from the realized SRIO,
PCIE interfaces, GbE and GPIO of every DSP have connected
to the Link Switch(FPGA1) on the interface board. The tight
interconnection between the multiple DSP processors and
Fig. 8. Assistant Debugging Software
Link Switch makes the transiting of the resulting data more
flexible. In addition, two pieces of 6678 which are on the
V. APLLICATION
same processing board couple together through their
Hyperlink interface(with 12.5Gbps transmission rate). With the high-performance universal miniature radar
Moreover, this interconnection structure makes it possible to system, different applications have been implemented
form virtual processing nodes and be suitable for large-scale including the GMTI, real-time airborne SAR imaging and the
calculating occasions. real-time space-borne SAR imaging. Then we would present
The synchronization timing network and the control bus the implement of the well-performing airborne real-time
performed by bottom board, are used respectively to realize multi-mode multi-polarization high-performance SAR
the strict synchronization timing control and underlying imaging system.
hardware control instruction among each part of the system.
A. Imaging Alogithm x Spotlight 0.2m*0.2m single polarization mode
Concerning the air-borne platform, especially the UAV In the large-scale spotlight mode, each of the processing
(unmanned Aerial Vehicle) platform which could be easily node finishes one real-time image of 32K*16K (4GB)
influenced by the air-stream or the other bad flight complex points with 23.89s.
environment and the calculating complexity, stability, an x Detailed strip 0.3m*0.3m dual-polarization mode
improved RD algorithm [2] has been chose to adopt the
real-time imaging platform. In the detailed strip mode, each of processing node
Raw Date
finishes a dual-polarization real-time image and each of the
DSP is responsible for one polarization image(16K*16K
Data Reuse&
Parameter Corner Turning Corner Turning
Doppler
Frequency Rate
complex points, 4GB total for the dual-polarization image)
Reading Estimation complex points with 23.76s.
Rang Cell
Range Range Migration Azimuth
Compression Compensation Correction Compensation

Corner Turning Multi-look

Corner Turning Corner Turning
Processing

Doppler
Azimuth IFFT Quantization&
Frequency Rate Azimuth FFT
Compression
Estimation

Output
Image

Fig. 9. Imaging Algirithm

B. Data Flow Fig. 12. 0.2m*0.2m Spotlight&0.3m*0.3m Strip Mode Fusion Images
In the real-time system, the speed of signal processing
should be faster than that of the signal acquisition to ensure C. Rescoures Utilization
that all the continuous echo data could be processed. As a The utilization ratios of multiple hardware resources under
result, the virtual single node is realized to meet the real-time different system working modes are demonstrated in Fig.13.
requirement and the huge amount of echo data in the According to the Fig.13, it is known that processing capability,
high-resolution SAR mode. In our system, the signal working speed of AD/DA, I/O module usage and the
processing module contains 2 pieces of processing board, and high-speed bus bandwidth are not used adequately. Thus the
each of them has been regarded as a virtual single node. system are scalable to fit more complex algorithms and
Each of the virtual single node consists of two DSPs imaging modes.
connected by the Hyperlink. The processing procedure is 1

shown in the Fig.10. Ping node executes the same program as 0.8
Best Performance
Pong node and processes a data frame independently. These 0.6

nodes process in pipeline parallel method. Meanwhile, inside 0.4

0.2m*0.2m Spotlight Mode

of the processing node, each DSP process a portion of the 0.2 0.3m*0.3m strip mode
whole data frame in parallel. The data flow of the system 0

processing is shown in the Fig.11. These structure brings the AD High Speed Calculating
Bus
DA I/O Module

matching quality of processing, transmitting and the memory

capability into play fully. Fig. 13. Hardware Resources Utilization Ratio
PING PONG
DDR3 DDR3 VI. CONCLUSION
Echo DSP1 DSP1
Based on the distributed parallel structure and 3U VPX
Data HyperLink HyperLink connection standard, our system designed a high-performance
DSP2 DSP2
universal miniature radar system. The system has the
characters of multi-layer interconnection, standardization,
DDR3 DDR3
modularization, scalability, restructure. In practice, the
SRIO SWITCH
high-resolution real-time SAR has performed well based on
VPX Bus GbE SWITCH
. our system. Therefore, the virtues of the system could be
validated.
Fig. 10. Processign Structure
ACKNOWLEDGMENT
Data
Acquisition
Ping Pong Ping Pong
The author would like to extend the sincere thanks to
Data Ping Pong Ping Pong Professor Hong-Xian Wang, for his patient guidance. Special
Processing Node Node Node Node
thanks should go to all members of the project team who have
Result
Output
put a lot of efforts into the project. It is my great honor to be a
member of them. The paper belongs to them too.
Fig. 11. Data Flow
 [5] Yuan J-Q and Huang P-K, "Design of real-time digital signal processing
[1] Mehrdad Soumekhg, Synthetic Aperture Radar Signal Processing with system based on DSP and FPGA", Journal of Systems Engineering and
MATLAB algorithm, Wiley-Interscience, April 1999. Electronics, 2004,26(11):1561-1563.
[2] I. G. Cumming and F. H. Wong, “Digital Processing of Synthetic [6] Shan-qing Hu, Teng Long, Design and realization of high-performance
Aperture Radar Data: Algorithms and Implementation”, Norwood, MA: universal radar signal processing system,International Conference on
Artech House, 2005. Signal Processing,pp.2254-2257,Oct 26-29,2008..
[3] Texas Instruments, Inc. TMS320C6678 Multicore fixed and floating [7] Tao Su, Xue-hui He, Lin-xia Liu, Real-Time Signal Processing System,
point Digital Signal Processor. Data Manual. Rev 1.0 November 2010. Xidian University Press,2006
[4] David E. Culler, Parallel Computer Architecture: A Hardware/Software
Approach, China Machine Press, Beijing, 2002.