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18 views3 pages

3151105 (1)

Uploaded by

Dev Nagar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Enrolment No.

/Seat No_____________

GUJARAT TECHNOLOGICAL UNIVERSITY


BE - SEMESTER–V (NEW) EXAMINATION – SUMMER 2024
Subject Code:3151105 Date:23-05-2024
Subject Name:VLSI Design
Time:02:30 PM TO 05:00 PM Total Marks:70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.
MARKS
Q.1 (a) Compare semicustom and Full custom VLSI design style. 03
(b) Discuss following approaches used to reduce complexity of IC design 04
i) Hierarchy ii) Regularity iii) Modularity iv) Locality
(c) Draw and explain various fabrication steps for CMOS inverter with 07
proper notations at each fabrication steps.

Q.2 (a) Explain MOSFET capacitance in brief. 03


(b) Derive the drain current equation for MOSFET using Gradual Channel 04
Approximation (GCA)
(c) Find the depletion layer width, depletion region charge and threshold 07
voltage with no substrate bias with the following physical parameters.
Physical parameters
VSB=0, for silicon gate n channel MOS transistor, with the following
parameters:
Substrate doping density NA=1.5 x 1016 cm-3,
Gate donor doping ND = 1018 cm-3,
Gate oxide thickness tox = 400A,
Nss = 10 x 1010 cm-3.
Consider Boltzmann Constant = 1.38 x10-23 (J/K),
Electron charge = 1.6 x 10-19 C,
Intrinsic Silicon carrier concentration ni= 1.45 x 1010 cm-3,
εSi = 1.035 x 10-12 F/cm
ε0 = 8.85x10-14 F/cm,
εox = 0.345 x 10-12 F/cm.

OR
(c) For an enhancement type NMOS transistor has its source terminal connected 07
to ground and 3 V connected to ground and 3 V connected to the gate. NMOS
has VT= 2 V , = 0.04 1/V , n *Cox=20A/V2, W= 200m and L =10m , VG=
3V , VD=0.5 V and 1 V. Calculate Drain Current ID.
Physical constants :
Thermal voltage =KT/q = 0.026 volt.
Energy Gap of silicon (Si) =Eg = 1.12 Ev.
Intrinsic Carrier Concentration of silicon=ni=1.45x1010cm–3 .
Dielectric constant of vaccume =εo=8.85 x 10-14F/cm.
Dielectric constant of silicon =εsi= 11.7 xεoF/cm.
Dielectric constant of silicon dioxide =εox= 3.97 xεoF/cm

Q.3 (a) What is meant by static and dynamic power dissipation? 03


1
(b) Define propagation delay and derive the expression for pHL for 04
CMOS inverter. Assume ideal step as an input to CMOS inveter.
(c) Consider a resistive load inverter circuit with VDD=5 V, Kn’ =10A/V2 07
VTO=0.8V,RL=400kΩ and W/L=2.Calculate the critical Voltages
(VOH,VOL,VIL and VIH) on the VTC and find the noise margins of the
circuit.
OR
Q.3 (a) Draw CMOS inveter. Explain its voltage transfer characteristic. Also 03
explain the NML and NMH noise margins with respect to this transfer
characteristic
4.4.13
(b) Draw the inverter circuit with depletion type nMOS load. Mention the 04
operating regions of driver and load transistors for different input
voltages. Derive critical voltage points VOH, VOL , VIH and VIL for
depletion- load nMOS inverter
(c) Consider a CMOS inverter with the following parameters: 07
𝑉𝐷𝐷=3.3 𝑉, 𝑉𝑇0,𝑛= 0.6 𝑉, 𝑉𝑇0,𝑝= −0.7 𝑉 ,𝑘𝑛= 200 𝜇𝐴/𝑉2 and
𝑘𝑝= 160 𝜇𝐴/𝑉2
Calculate the noise margins of the circuit. Consider 𝑘𝑅=2.5 𝑉 and
𝑉𝑇0,≠|𝑉𝑇0,𝑝| as it is not a symmetric CMOS inverter.

Q.4 (a) What are the limitations of Dynamic circuits? Discuss the effect of 03
charge sharing and charge leakage in dynamic pass transistor logic.
(b) Two nMOS transistors (M1 and M2) connected in series is shown in 04
Figure 1. The power supply is VDD =3.3 V and the nMOS threshold
VTN = 0.55 V. Find the output voltage at node b. Consider i) Va = 2.7 V
and ii) Va = 3V.

Figure 1
(c) Explain the Euler path approach to find the optimized stick-diagram for 07
any CMOS logic circuit. Draw the optimized stick-diagram for the
following Boolean function (CMOS Logic), F= (A(D+E)+ BC)’.
Explain the importance of Euler path approach.
OR
Q.4 (a) What do you mean by stick diagram? Implement the following Boolean 03
function using stick diagram.
Y = (A*(D+E)+B*C)’

(b) Explain the need of Voltage bootstrapping? Derive the mathematical 04


expression for dynamic Voltage bootstrapping circuit.
(c) For the Exclusive OR function , draw with following realization 07
1. Static CMOS realization
2. Pseudo nMOS gate
3. CMOS Transmission Gate(TG)

Q.5 (a) Compare FinFET and Planner MOSFET 03


(b) Draw transistor level circuit diagram of NAND based SR latch using 04
CMOS.

2
(c) What is clock-skew? Explain on-chip clock generation and distribution. 07
OR
Q.5 (a) Draw and discuss three stage ring oscillator 03
(b) Implement and Describe CMOS clocked SR flip-flop 04
(c) What is need of Design of Testability (DFT) in VLSI IC design and 07
explain Built in Self Test (BIST) techniques of DFT

*************

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