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24mv06 Assigment2

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thiruthani9053
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23 views7 pages

24mv06 Assigment2

Uploaded by

thiruthani9053
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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ROLL NO:24MV06

NAME: THIRUTHANI N

CLASS: ME VLSI DESIGN

DESIGNING WITH FPGA

ASSIGNMMENT – 2

1.SEQUENCE DETECTOR 11010:

`timescale 1ns / 1ps

module seq_det_10110(out,in,rst,clk);

input in,clk,rst;

parameter s0 = 3'b000;

parameter s1 = 3'b001;

parameter s2 = 3'b010;

parameter s3 = 3'b011;

parameter s4 = 3'b100;

reg [2:0] ps,ns;

output reg out;

always@(posedge clk,posedge rst)

begin

if(rst)

begin

ps <= s0;

end

else

ps <= ns;

end

always@(*)

begin

case(ps)

s0: begin

out <= 1'b0;

if(in == 1'b1)
begin

ns <= s1;

end

else

begin

ns <= s0;

end

end

s1: begin

out <= 1'b0;

if(in == 1'b0)

begin

ns <= s2;

end

else

begin

ns <= s1;

end

end

s2: begin

out <= 1'b0;

if(in == 1'b0)

begin

ns <= s0;

end

else

begin

ns <= s3;

end

end

s3: begin
out <= 1'b0;

if(in == 1'b0)

begin

ns <= s2;

end

else

begin

ns <= s4;

end

end

s4: begin

out <= 1'b0;

if(in == 1'b0)

begin

ns <= s2;

out <= 1'b1;

end

else

begin

ns <= s2;

out <= 1'b0;

end

end

endcase

end

endmodule
OUTPUT:

2.CARRY LOOK AHEAD ADDER:

module cla (a,b,cin,sum,cout);

input [3:0] a, b;

input cin;

output [3:0] sum;

output cout;

wire [3:0] p, g;

wire [2:0]c;

wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10;

and a1(g[0],a[0],b[0]);

and a2(g[1],a[1],b[1]);

and a3(g[2],a[2],b[2]);

and a4(g[3],a[3],b[3]);

xor x1(p[0],a[0],b[0]);

xor x2(p[1],a[1],b[1]);

xor x3(p[2],a[2],b[2]);

xor x4(p[3],a[3],b[3]);

and(w1,p[0],cin);

and(w2,p[1],g[0]);

and(w3,p[1],p[0],cin);

and(w4,p[2],g[1]);
and(w5,p[2],p[1],g[0]);

and(w6,p[2],p[1],p[0],cin);

and(w7,p[3],g[2]);

and(w8,p[3],p[2],g[1]);

and(w9,p[3],p[2],p[1],g[0]);

and(w10,p[3],p[2],p[1],p[0],cin);

or o1 ( c[0],g[0],w1);

or o2 ( c[1],g[1],w2,w3);

or o3 ( c[2],g[2],w4,w5,w6);

or o4 ( cout,g[3],w7,w8,w9,w10);

xor x5(sum[0],p[0],cin);

xor x6(sum[1],p[1],c[0]);

xor x7(sum[2],p[2],c[1]);

xor x8(sum[3],p[3],c[2]);

endmodule

OUTPUT:

3. VENDING MACHINE:

module vending_machine(

input clk,

input rst,

input [1:0] amt,


output reg [1:0]product,

output reg [1:0] balance

);

reg [5:0] total;

always @(posedge clk or posedge rst) begin

if (rst) begin

total <= 0;

end else begin

case (amt)

2'b00: total = 0;

2'b01: total = 6'd10;

2'b10: total = 6'd20;

2'b11: total = 6'd50;

default total = 0;

endcase

end

end

always @(*) begin

product = 0;

balance = 2'b00;

if (total == 20 | total == 50 | total == 10) begin

product = 1;

if (total > 30) begin

balance = 2'b10;

end

end

end

endmodule
OUTPUT:

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