Date. Page FI Se es muttipurpoue. integrated cireatt that is_regicter haved, clock dsiven_and programmable: __ bl Processes cata as per the cet Of instructions or programs. __ OI Peripheral companents are input, memoy and output LIL micoprocessor is a single chip containing AL antic oF CPU. G | microcontroller fe a single _chtp consisting of MPU, Menor ioterfacy circuits: — lo and ng Meu i Micro processing ‘Snlt_— comple te Processing nD. =a = O4-]]| Define. microprocessor: Describe the. Maoprece scat Destribe the evolution of mfcropracessor 3 microprocessor is an integrated creat (2) that. is muttipurpose, Clock diiven register based and made from silicon chip that _ frmperates core. functions of computers: cpu: Tracephs binary dota _as_an input and provides ‘eutpul offer processing i it as per the instructions stored fo memo te _ ic Evolution of microprocessor = _ 5 We evolution and chevelopment OF mferopracessor can hE groctpect int BI ; Aistinct_genera¥ons hased on the KEY technological aduancernents _ Ord changes in drchftecture : ! 45° Generation 2 The ~ beatnni na Dkey chip: Tntel 4004 (199!) ~PTechnelg 14 ‘bit processors S charactersties could perform baste arithmetic and control funck hod fao-transictors (about 21800 19 4004)Date ag! &ed Rarty pour (late 19305 - 19806) ___ _|| Skey chips :_Tntel_soag (1932), Tntel SOO U9R#)————___ mi STechnetegyy B-bit_ processor ; charactensitas * allewed mare _cempiet_cperantens, improvement memory_cddressing and computing abiliisy. —_ L Generation: | and 32-bit transition _UMid i9g0. to 1990) MEL BORE /goee 1978)5 Intel _BO2K6 (4982), Tme\ 80386 (1985) —-—_____ _ Technolog sy: Transttion fom 16-bit to 32-bit procescor tasking ‘and memory protection: RE , 32-bit processor is capable pping more - complex. _operating systen Uke carly vetsion_of Windeun- | __> Rersormance beast j altewing, Sor_mar powerful pereonal_ computer 1 | Fourth. Generation, super performance (1940s ~ Early 20008) |/b key chips Tntel_Pentiam (993) , AMD k5 (1996) & Technology. Superscatar architecture, Intreduction of : multimedfa_exctension: (MIM) % charactenstias’ > Fenttum processors added support for multiple thsttuctions per clock, cyte _(super scalar Agsign) ‘ i _ > The Pentium MMnradclecl special insttuctions to handle multimedia tack Ulke audios vedio and 3d gyaphicc’ 7 +) Big leap _in_ speed ,ability to tuo more complex Softuas,wow a, | ete Generation + Mut (2000°2.0 10% OTe, and Energy Lff tcieny : ~~] brey chips: Thtel core 2 vue (2006), Intel core 17 (2008), _ 2006) — — AM > Ryzen (2019) - 4 jSTechnolegs, 2. Multi_core processors 4 §4 bit architecture = y chavactensticss _ an ee “DUAL core _proxessors enabled computets 40 handle cmultiple SASKS_t_the same Kine moe efficient 3 Rise of SNeKppy - efficient chips, particularly tn_mobtle devices DARM chips started Ko dominate mobile devices - ¢ | Sixt Generation: AT and specialized process! 20204 ~Precen)) Okey chipe: Apple. M1(2020), AMD Ryrem SOO6 (2091) ,Thtel Alder lake Afechnology- ‘Thegration Of AT, haterogeneous Onchitecrres, Inn ond. Sin processor: Soharacters fies = Pons on AT and. machine \eamnfng aecleration with dedicatect neural process om 2-1 Eaplain the Afferent components of the nicropracessor_baseck system with HECESsary Figure: Differentiate Letween mfaoprecessor ancl mlaocntrolter [2076 (Batsakti] ee 3{ Te block dfagiam of © typical microprocessor eantains ue mayor posts. _ 2]Me_finst park includes mfcroprocessor, second Treludes typutl output — devices nck third Includes (read lutte) MEMONY) where Ali part _ Works togetter to‘ execute tasks NG process doto: —— These components are _erganived around o common commountecrtion [patty callect ao bys wyFig:- Mfcroprocess ot Ba sect Sy.ctem with Bus ae > Tie. Atafog_ ond excite unit generates contral seal equated for the _mfcroprecessor to operte - ___|| Bascription’, = 4) || Mfcxoprocescor ‘ Tk consists of following parts Q) ANthmeife ond legfealunitCAlu): | S The ALY performs the comprting gunctions: 9 Tt includes Accumulator, temporary register the orithneltc and legfe. circuits ond the’ flage : \) Performs ciyithmetfe _operections such as addition, sublraction od _legico.\ operation such a AND. OR -voR, e4:< a b) Re array! - q : % Primarily used to_ctore. dato temporarily dusing the execute ot program and are accible to user through tnstrurctied % can be identigied by letters suchas BC, 0,£Hand tTPage —__ aT et a Sa ONerpernrerusramiearameetat . MV mMides necessary sion Ard ccMtrol_6igna\s to alt We operations Ts coctsede fous of < vi fpheral.! oe A sortie Sees ef dota Lelucen micmpecesseh, CEMONY Ord perfphe i \ \ | HENCe, micropracescor fs capable of _pert ing VONOUS _comMpating ‘Sy -fureKions_ancd maring decisions Ao_change. the. Sequence _of cr” }-POQTAM Sxecntion . Sa Memory % wtoxec binary inomation is D_Qe fnstructions, dato ANd provides *nat information vo. mcr DPICCESCOT_WHENRVEr Necessary > _ © T has two vections: Read only memory CROP): Used to ctore pagiaMs tat do net HRecl alternations and Con_ony be Yeack ©)_Random access (Read !urite) memory CRAM): Also ENoWN as We Memory caich is Used to gtore User greqrams Ada. dota: We infrrmation gtored_ tp EMI can be Sasily seach and altered Input] output: Tt_cornmunicates uth the outside worlel uding two devices inpe and output which _ove also ENOWN as peripherals _ __ The fnpud devices such ag Keyboard guittches arc analog to _ diital_ converter transfer binary information - fom “ouside worl te _mfcroprocessor — The cutput devices tansfer dato from the _pfcroprcessor Outside world" They inclucle je devices such as LEO. CRT. digital Yo enalog. converter, printer etic 3Date Page —__ System Bus!- Tis a cromantatin gah bekoees te wiemmiessr ant — — peripherals specifically a grup of wires xo wi ie TW fs _surther claccftied into Address Buss Dato Bus ard’ Control Bus - —lilsomrece ssor Tie difierences between rofemproceassof and rnfeto controller ate: jet eae > Micro controller is an TC that contin Mictoprecescor Ts osilicon chfP. Gogable cf performing. qnthmeti¢ CPL, soakchpad: RAM register array, timer ana _intemupt contra wits ANS logtcal operations cco Predefined vet cf insinrctions: and dedicate To 2 patton singlets 2&9 Hl Oseck for compte, high petformar > Used for specific eaial orient Jasks (€g: PCs laptops, cened | tacks (€q: home appliances, Es e-1) 31 Kqher power consumption dueto | > lower power Consumption as itis external component and high _| optimized for embedded Clock. _cpeect + Opelicartions: LA target system ste ast > compact dze dus to depends an_exiemnal_componente+ Linxegration ot components _ | Higher cost due to neect for 3 More cost effective fer secific yASk - additional components Geral fun nin oe SAE tse Oops i M1s_dopendent usit > Ik fs _a set contained units3 DetiNe Me stored progiann concept “Wow does Horwesd meet [Architecture After ror Vvonh- Neumann Archftecture! (RFF chaita eee . - _ | The—stered_mrepnin concept §s_a fundamental princiole of modem . re, tahere_Tostnrctions (py s)_ond_datastored Aogetner WO the, same. memory ‘This concept allows a cormputer to WIG O Sequence Of instructions ory, whch can be TeMeved AN exceccitect by the processat: THs “Rey featuwes ares onitied tora, program flexcfoility, sequential excecetion ‘Sra _dypanic functionality: —_» — ¢ from _Nenn- NewMmann Osi. Noon Newmann A teeters Harvad Architecture - : Ae _f_ancient computer architecture Lf pe te MedeTO _copMPLer gschitectere base on the ctored pr Based on Horvord Mark Liela, | Compurer__conep4 i | based meddle) a SAME _pnycfeal memory acldress [31 Geparate Phy staal mematy Address is used for data and instruction | fs used for data ond instructing | Here, Fs _O cormmon bus for [3 Separate buses Gre usec Aor. ANA Togtractlon transfer. | Aranstering AoW and instructor fTwO clock. cycles ene required |4] An Inetructton Te _excecerteck Tin te erecnie A single fnstructa, A single cycie: T “It is _cheaper_i S1t Ss more costly: ‘Ihe CR comet access instructial 6} The cbO can acesc tnstructio a1 lustre ALa same time: | fand readlurie at came time. TA ts Used tn personal LF] Te te used ty mfero controllers: Computers aed emai) computer! | and siqnol processing ~ + =[bare What fs bus? Explain the Bus organtadiion ox trie_mfcoprc -oith_o diogram. ca\utate the_memery handing. capacity ~Ahe_proceesor_aving an_odaress bus of % Mings and __* data bus of 16 Lines — Bus Ts a common channel thmegh which bits from any scree con_be bansferrech jo the destination: 2 Abus cocure, conststs of wer of cemmon Lines,ore for cach _ aT, Aor ore at a time: a BIT of a register, through which binary infomation i bansfered _ Bus Ciganization of Mcaoprocesso Tt Yefere to “the Faw of dota and’ A Instructions cata ety) -2-_ control sfyrals : Rigi Bact dioqarn OF afghial computer. aDate Page | Pesclption; J] Topal bot e o function, Aeceprs darer ancl Ymutructlons Ayer the ayer : 2 fo worming tn Comers the data ancl nclwuctione pple es preter ——|-— Yeaclable format and ranger ‘them to CPO" __— }-2 Grampless: keyboard, mouse , scanner: 2} CenvaL Pocecsing ont CCPL) || ‘The. (P0_t¢ she tata Of Computer, ancl it conshsle of Ure corsgenes- | oAuithme te lege unit (Aly): “Performs avtibmette operations (eg adkdttion , subtvactian) anc logical Operections (eg conrparicion): 2 contiol_onis (Cv): | Wohects the Moc.of dato bevecen the. C0, rrerrony and TIO dover -Tetnterpretis Angtructtans AN eyeaves preper execcticn ao Recyister [Merrory- AANA + |) Primony memory, RAT onrct Con): Femporcuy ancl permement Storage for tmrnecdiate access by the CPO a ®) secorday rngrony¢ Useel for ong. Les elorage 9’ HDD S5D,¢4Ly = Output uot: _ ee eFunction: converts processeck date Aro 1 he PD inte © humn— Teadable form © Examples: Montior, prtoter, ajgakev— ee Gyctem Bus 1. oFunction: povtder a communication patwoay rN data, instiuctions, anc control iignabs rob ara. | Memory and (0 aunties Types = fale bus, address Pu, control bus + The imemal araitecture of AORG Miseprecessor | 2 ADilowing. blocks’ pte AyTinmMetfe_ and. topic, ont (awe), Performs mo’ Nica coraputing functions ke addition subtraction, logical functlons_itke” ND \D.OR, shifting ete. ___ passes to the instruction dee Temporary registers are used to_fpld We cata durin fi operation And result is stored ip _occurmulater Flags are. cer or reset Scantling eset Ae result Of operation. | Tastruction. _Aegjter TR) and Recieves the opcode of operation cesie, “of fnstouction and — TR decodes the opcode _ A ANE _Microprcascot Knows which _— aye OL 1086 Xo be perforMmeck during exerction « a ‘Thase_ Ceqisters_ O12 _nol_accassiA® _to_preqramncer —THPMPU LST Fo SUH LOI9) Aiogiad ops weer ta FHHDOUY SY 3G SAS VAHNNVY. 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