Marks ~ 44. Unit-I- 3036 16 bit Microprocessor * Introduction ( 2086 Microprocessor ) ~~ -808G is the first 16 bit Mictopracesset develope: by Intel. & Launched in 1478 ~ — = R086 Microprocessst__haS.a much. mare. power _ ful instuction set a _— -I+ is available in a 40 pin ICY operates _ —at § Volt dc Supply a — _-I4+!'5 electronic civcujtary consist of 249000 _ transistor & available in. 3 version that i5— = __g0xe (SMH2) » 8086-2(8MHz)» 8086-4 CloMHz) _ = $086 have_20 Address _Line—using which we can interface 2*° =4 MB__of _Memorey mean jt can address up +o 4 MB Memorey——.— = Out of 20 Address Line, 6 Address “Line are _multipleced — with data Line &name_as Ade =—AD5_.__— ee . _= Remaining 4. Address Lines ate-also multi plexed _Twith Status Signal : _ __ Silent _ Features of 8086 Microprocesser -_ - Provide. 20 Address Lines. So, 4 byte ofa — _Memorey_can_be addressed» ___________ Multiplex _\e—bit address & data must —— ADo—Adi\s to_minimizeno-ofpins—on Ic _____ = Operating Clock frequency are 5MH2,8MH2.— eee 1 el on ae _- Arithmetic operation—can beperformed on - 2 bit or je bit signed Uumsignednurmbera including —MulHpli cation division —————__* =} the. Postouadiin. acd. 1a powerful _-£ texible > Provide 256 types of vector Software (tturmups | ___= Provide 6 byte instruction quevefor—pipeling of _imstructlon— ex ecucbiom ——— |= Genevabe ¢ hit ov_le bitin pub ottpuk | address eS nl (Sup pert_Multie pragrarn-mitng —— ides eprate Instruction for string Manial a | | _* 2086 IC* 2086 TC - ___-- _ i oo niet Aldea tees a TT AW sy Rie 195 cr Aig 750 = BHE 167 SIM] Pix © Select Min) TT RD Max Mode “ TReTate CHold) RG TET CHEORT TH 6 CALEY a EA) a a Pin 2- 46 8.39) = ~ This Lines are Hame multiplex bs jrectional —__— address or. data bus —— ~~ = ADo te ADz— Lines Carr y- “Lower_order— bytes of data &- ADS +o ADs — Caen “higher order _of data oluti, Aye/53 te Aig | 9e~ ddvess _and Stab” - _ 2 this. Lines are time smulti plex __._Lines—- Se ane _—. a and 55 1S.an interrupt enable Status Signa ~ _- $3 & 54 Tro 1 55 “Segment reqist _—iiiy BHe./$7-C Bus high enable) [Gtatus Signal) —— BHE—Signal_is used to-indicate the transfer _— of_data over higher order (De- Ds) data bus —— _ + Tt goes low for the. data +transf er_over Dg -Dy-——~ _- BHE_13congection— pin —with— ABo_determimes———— __whether_a byte or _Word_twi Ibe transfer frar—— ___tw0e Memorey— ee erg ee eee Gee = During yo 6-74 the status slanal 47 is <—— Sromataibted on this Line -_ 3 ia _ ene Agiuct sea. ss fe ——W ord {Byte acceso ut -—word_fyom_eve: ef upper bye fram [to 04 addition lewer byte from —+o-even_add None-——~ivy RD (Read output). - -- . ee TH isan active Low Read signal & used to. ead _ device- which are connected tothe 2ox6. __.._Lecal—bus——— : se ne Tt is an_active high-input signal, it indicates thot the peripheral _device—is aeady _to rans fer the data. —_— oe ~ Wi Reset = — es T+ is a_system reset signal Tt js-an—active — high signal -—___— a a ____NiiINTR (Interrupt Signal.) Pin no-|2=—_——- —_ fthisisa-level_trigget interrupt —request_ input i is check during. the last cloch— of each jms-— “yruction to determined the availability—of +the— request ony = Tf _an_interrupt— enter the interru pi—a cknowledge—cycle yequest js_occurs the. processor viii, NMT_CN on Mashable Interrupt) =———— _- This_is_an_edge trig gered _in put— interrupt _——— request which_causses _Coccur)a—ty pe two. Interrupt > The .NMI [5 _not-maskable by Software ——— hy = caf the test Signal. goes Lows execution —wil|—1 “continue “else. the pe __ state no) = — st ana “des “the. fae Hing fa This—clock imp pr es pro cessor—operation— & bu 5 control actly —_>— _ cane . Tr > xi vee —____—— _ 48 volt DC pawer-s4pply- “Fox the opetation of —__imbernal clreult: ee eae Gnb=Cénound) Pinno— “4 20 = Ground for the imternal circuit N/ Mx. thle pin_indicates the operating mode of Sore — ——=Thelr_ate tune” operating —™ ae deine ee Tt i pin in rl hen Lew te tise —— =r i a s_an_active Low o eaneoane ese wmlceopaaconset ecleven IN =, : Microprocessor __Com pl plete cu’ Ce —_— cycl : cycle — ears 4 bi —4 enerating this —cy!xv) ALE- ae - st cP tt js an_actve high-pin—which. is used_t+o-+1a - msfer valid address. on. the ADo-ADjs-———— Fee ae cma sears aes —=T4 ja an_active Low pin-& which_is_used +o — transfer. of Valid data—over—ADo-ADIs.———— aly pt /R_C ata “Hranamitted_/ Recieve) =——_— = This is output signal is used _to—decide the __ divection of _data io eee “_reciever__CAransmitter_or_reciever)— ta_output— _-When the Microprocessor Send — da? _this—siqni lo high ohen_M icfoprocesser_—_——— _ recieve. data then this_sig j-2_Low—-——___— yxy 75S = Cotes Signal) C Memes [Ea Or wtput- _devices) = = When the _signol. js high- Memorey—t 4 accessed = by _Micro processor when the signal ist ow jmpuf-—_output __devices— is accessed_by micro=— processst _———~ Tx AR Cubtite) 2 i OS cam active Low signal > to write—data— e __ $0_Memorey- or-inp ~oufputdevice depending _ _om_the status signal. of _M/ to__signal —__— “yy HLDA. Held acknowledge) = “2 this is an-active—high—opace ssot- “af peter y seciewing— a, ~ Generated by the pee the Holi goal a ee —— ee se cnt —__| t— on xxi Hal = is anatase icsaas wend hese gaerabethe the carol _bus—in— to the —— 2s an a = This tines Pie ge en — oxi 50,5, 5 - — ‘aba sgn aeied Thc ype af opal bsoO { \ Holl \ ° o op-code felch \ © \ Memorey tead \ 1 o Memorey Write ! { ! Passive: xxiv). Tock - = When it goes Low all interiupl are Masked & hold request is nok granted» xxv) RG / GiTe yRO/GTy (request / grant) = = This pins are use by other local bus in maximun mode to force the processor te release the Lo bus at the end of the microprocessor current us cycle- _--This pin are by divectional with RG | GTo having higher priority than RO /ati _ .“genalion =——— Te Physical Mermorey Addness _generoton=—— — oO 1s ° ir a —_™ I$ 2000! S45 : ited |_offie | [sent —f het address | addvess | i It ae _ ; Adder SU [Peis = +8026 bas 2obit address bus,s0 it can addee atte acne te Ca ia oobi ress address fromthe effective addrecg. —_& Instruction Pointer (Tp) eeeseeneneeeees = The jmstruc+tion ointer register helds thi le bi 4 oddvesa af then eats are the co. —Seqment + ot = Th «Value stored in Ip is called geo pot ———or_displacement_ # a _OF Shack Pointer (oP) ~The physical_address of the Stac _ing_or-Writing the word_is_produced by adding - _ the content of +he Stack _peintet_to—the Sstack— _____ Segment _base register —— — — = = The content of 5+ ack base segment Tegister15— — gifted left by 4 bits. for_example,assume—S$— contains GoooH..&.SP. contains —FFEOH This 54 is shified Left 4 bit —position.to— ive GoooeH 2 After adding 2p thats offset inte —i+ the - wesultant— physical_address for_the-te p-of — the stack wil ba GffEoH as shown 1n— Figure: oot sax __Architecture of gose/ Block diagram of 2086 - - Execution Uni _ = The function—of. Execution. unicorns _@ To. tell B1U-where to $s fiteh the _insttuction. of data form - _— _—' heen seem: —@ To-ducedy the fraction — __@_Toexecupe the-insdruction—— = The execulion indeed. contain the : circuitry to_perform— various—inter | operahions on ; = execution has_{e— bit ALU. 4 : Ty, _at ithmatic glo 4 jeal_o perationson-#—bit daly slo bit, - Bla register in_execulton—umid—h Soren this register "contain 3 actlve flags oe "© Flog Register Format of 2086= __ Dis | Du! Dia Dia Duy Duo] Dg Og Dr De/Ds D4 D3 D2 Di de - SPP or pe ine ite SF 2F | AFI NTPEIN Cer _— Overflow Flag — TTT TP Direction Flag a 2 eto—Auxi ary Carry __— _ _Tntertypt |__| Flag Flag —__| Flag —_— ___Flag__Sign ! py Oy By Carry Flag C a __ m4 = Tt is set tod if thelr j sof the - eb positien thal ie resulting “fh ee - or if berrow_ is needed of MeR duxi y-— /eoaeee Tf their_is_mo_cavry— She ee or bit result the carry fiag te, #™ foe ily Auwilary Cory Flag CABJ= a TE the operation’ perfsrmed Im AL ge : ‘ _- rates 0. CATTY 0 Borrow Crom i, = rT_ ‘Nibble to. upper. Nibble “the AF. Flag is. sete : Tiiy Bavity Flag COR)= oo = This Flag — is used to indicate the the —parity— of the result: -_-__--_________— 5 gare Flay a= 2 Te js set if the result of avithmabic_or— Jogical operatlen is —2e%e — otherwise jt wil| be reset — Ny Sigqn—Fl ag “CSF eee os, — esult_of operation of _ [| -~ If the — iy Overflow Flag. “Ceple -“Im_case_of_Si qned_grithmeti tion the — —_averflowFilag—is— set jf the result is +oo—— —lorge2———- zi eS _ _ ep ae If i+ js set—theMas hable_imterrupt—INTAL of 2or6_is enable ¥- if it is reset the interrupt ja disable. ——______——— TMi) Dixection lag COF)= eration Lf it is—set yk is used in String—opers otring byte aveacces® trom nighey mMemo- _ ey address to-lower _Memorey 0 ioe - sii “Jaq CTF)" i Me ed vp Flag is set te gone u automatically do a-+y . pet _@ | Grenevol purpose Register = Execution unit—has 8 general-purpose TeHist HAL, BHs BL, CH, CL»-PH be —_— arte yeqisters can be—Us 68-bit regista — _._imdividually.or can-.be use as Sé bit —In_pair_ to have Ax, Bx»Cx-&Dx——— ——————__. AL Register is called as Accumulator: a In addition +o +the general purpose_job Some ___teqi ster — have Special_task sucha 6 Cx Is morally use—as—the Counter-— Bx canbe used as Pointer = _Dx_can be used as — input—outpu + address: sto—hold the_inpuk,_cutp + address = 8P_& Pp_ate._pointer register uh ich halde— LB bit of: £_set_within the_partt ‘alae —-—— segment a as ig SI_& Pt are the tndex register : Heer__ Concept. of Pipelining __ = On a-—-Non—pipelining— process nine —cy Py aes “the -techniq mstruction_-Fo complete— with —each—clack- cycle — cle are required — Por the —individual Fetch ,decode __& execute— cyel as. Shown —in figure @-— + _-.on—pipeline__process— &y execute _.opetation—are- required Fo-execute— _ +he.—Same—- instruction as-Shown. in Figure es for the three— instructon— 7 Oe soe pipeline -is_ implemented — —Se Shere. a5 beng as rH peniing G byte queue ‘be stored . ten ins byte —— instruction..can- a advance 4— then —only aby a tru _ction "goes Por-decoding — rg ie “Memoxey Seq mentatlons—— —— ight adn ee ; __ a a |] Bo =8000H — | eget t____ Ot —_—_——— a __t a eT booH = == Shen it ° °}_—_—__—— ee { Data al i S=il0c 1 arn {Segment TS GK _ = Im this the complete visili mplete visibile available Mexor —— th Mainly devided inte 1. ~A_9 o0F Log iceal Seq ment: a= Each_seqment js _ & i £4 KB in size & addve ——_ome_of the. “Segment tegister ec ——Thee_hit contains Af 4 ——detual ly point nto the Spent eg ing ee particular —__peq ister —tecabion_ofe la addres: Pent as wit hina Seqmnent uae te_Merng: e acati ——OF— 4 Isplacement ae ode Le ee= The offset addvess is also te bit Long-.S0,-. that Maximum of f set value can be49 FH 2 — - Maximuyn size of any seqment, is thus..64 kB — Memerey—Locabion — pr se oThe cpu. 8es6is able to. addressed a MB of - physical Memorey pt ao 2 -The complete 1 MB Mernerey can be _devided— __imto je Seament—as Shown in_Figuye= a Ty Advantages.of_Seqinentation = —— _ = Segmentation can. be used bn —Mul4tie user Ame _ Sharing System. —— os Program, data can —be stored _Seprately from each other _in_seqment- —_ - fagoendation allow -+wo processor Share _data - = ice eee eee _SeqmentaHon—allew you to_ex-tend the —_ addressbility of a_precesser.