Chapter 5

Interface
What is Interface?

Interface refers to the path for communication between two components of a microprocessor.

For the better understanding let, us see how the 8086 microprocessor PIN diagram looks like.

Fig 5.1 pin diagram for 8086 microprocessor

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Description

A16/S3, A17/S4, A18/S5, A19/S6: The specified address lines are multiplexed with corresponding
status signals.

BHE (Active Low)/S7 (Output) : Bus High Enable/Status. During T1 it is low. It is used to enable
data onto the most significant half of data bus, D8-D15. 8-bit device connected to upper half of
the data bus use BHE (Active Low) signal. It is multiplexed with status signal S7. S7 signal is
available during T2, T3 and T4.

RD (Read) (Active Low) : The signal is used for read operation. It is an output signal. It is active
when low.

READY : This is the acknowledgement from the slow device or memory that they have completed
the data transfer. The signal is active high.

INTR-Interrupt Request : This is a triggered input. This is sampled during the last clock cycles
of each instruction to determine the availability of the request. If any interrupt request is pending,
the processor enters the interrupt acknowledge cycle. This signal is active high and internally
synchronized.

NMI (Input) –NON-MASKABLE INTERRUPT : It is an edge triggered input which causes a

type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system
memory. NMI is not maskable internally by software. A transition from LOW to HIGH initiates
the interrupt at the end of the current instruction. This input is internally synchronized.

INTA: INTA: Interrupt acknowledge. It is active LOW during T2 ,T3 and Tw of each interrupt
acknowledge cycle.

MN/MX MINIMUM/MAXIMUM :This pin signal indicates what mode the processor is to operate in.

RQ/GT RQ/GT0 : REQUEST/GRANT: These pins are used by other local bus masters to force
the processor to release the local bus at the end of the processor's current bus cycle. Each pin is
bidirectional with RQ/GT having higher priority than RQ /GT1.

LOCK: Its an active low pin. It indicates that other system bus masters are not to allowed to gain
control of the system bus while LOCK is active LOW. The LOCK signal remains active until the
completion of the next instruction.

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TEST : This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will
continue, else the processor remains in an idle state. The input is synchronized internally during
each clock cycle on leading edge of clock.

CLK- Clock Input : The clock input provides the basic timing for processor operation and bus
control activity. Its an asymmetric square wave with 33% duty cycle.

RESET (Input) : causes the processor to immediately terminate its present activity. The signal
must be active HIGH for at least four clock cycles.

Vcc – Power Supply ( +5V D.C.)

GND – Ground

QS1,QS0 (Queue Status) These signals indicate the status of the internal 8086 instruction queue
according to the table shown below

DT/R : DATA TRANSMIT/RECEIVE: This pin is needed in minimum system that desires to use an
8286/8287 data bus transceiver an used to control the direction of data flow through the transceiver.

DEN: DATA ENABLE .This pin is provided as an output enable for the 8286/8287 in a minimum system
which uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles.

HOLD/HOLDA : HOLD indicates that another master is requesting a local bus .This is an active HIGH.
The processor receiving the ``hold'' request will issue HLDA (HIGH) as an acknowledgement in the middle
of a T 4 or T 1 clock cycle.

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 In micro processer interfacing is of two types, memory interfacing, and I/O interfacing.

5.1 Memory Interface

Memory Interfacing occurs when we need the microprocessor to access the memory for reading
instruction codes and the data stored in the memory. For this, both the memory and the
microprocessor requires some signals to read from and write to registers. The interfacing process
includes some key factors to match with the memory requirements and microprocessor signals.
The interfacing circuit therefore should be designed in such a way that it matches the memory
signal requirements with the signals of the microprocessor

5.1.1 Memory Devices

Simple or complex, every microprocessor-based system has a Memory system. Almost all
systems contain four common types of memory:

 Read only memory (ROM)

 Flash memory (EEPROM) ( Electrically Erasable Programmable Read-Only Memory)
 Static Random access memory (SARAM) Sequential Access Random Access Memory
 Dynamic Random access memory (DRAM).
 What are the differences between: RAM and ROM?
 What is the difference between: Static RAM and Dynamic RAM?

A general form diagram of ROM and RAM show in figure below. Pin connections common to all
memory devices are:

 Address connections: All memory devices have address inputs that select a memory
location within the memory device. Address inputs are labeled (A0–An)
 Data connections: All memory devices have a set of data outputs or input/outputs. Today
many of them have bi-directional common I/O pins.
 Selection connections: Each memory device has an input that selects or enables the
memory device. This kind of input is most often called a chip select (CS) , chip enable
(CE) or simply select (S) input
 Control connections: The control input most often found on the ROM is the output enable
(OE) or gate (G) this allows data to flow out of the output data pins of the ROM.

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 Fig 5.2 general form diagram of ROM and RAM

5.1.2 8086 Memory Organization

The memory address space of the 8086-based microcomputers has different logical and physical
organizations.

Logically, memory is implemented as a single 1M × 8 memory bank. The byte-wide

storage locations are assigned consecutive addresses over the range from 00000H through
FFFFFH 8086 Memory Organization (a) Logical memory organization, and (b) Physical
memory organization (high and low memory banks) of the 8086 microprocessor.
Physically, memory is implemented as two independent 512 Kbyte banks: the low (even)
bank and the high (odd) bank

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5.2 I/O Interface

I/O Interfacing indicates the various communication devices like the keyboard, mouse, printer, etc.
When we need to interface the keyboard and other devices with the microprocessor by using
latches and buffers. This type of interfacing is known as I/O interfacing

☞ A latch is a digital gate that transparently and continuously passes input to output.

☞ A buffer is a temporary holding area for data while it's waiting to be transferred to another location

5.2.1 Interfacing I/O Devices

 Using I/O devices data can be transferred between the microprocessor and the outside world.
 This can be done in groups of 8 bits using the entire data bus. This is called parallel I/O.
 The other method is serial I/O where one bit is transferred at a time using the SID and SOD
pins on the Microprocessor.
 8088/8086 architecture implements independent memory and input/output address spaces
 Memory address space- 1,048,576 bytes long (1M-byte): 00000H--FFFFFH
 Input/output address space- 65,536 bytes long (64K-bytes):0000HFFFFH Interfacing I/O Devices
 I/O devices can be interfaced in two ways
Isolated mapped I/O
Memory mapped I/O
Isolated Input/output
 It treats them separately from memory.
 I/O devices are assigned a “port number” within the 8-bit address range of 00H to FFH.
 The user in this case would access these devices using the IN and OUT instructions only.

Fig 5.3 isolated I/O

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Memory-mapped Input/output
It considers them like any other memory location.
They are assigned a 16-bit address within the address range of the8086.
The exchange of data with these devices follows the transfer of data with memory. The
user uses the same instructions used for memory.

Fig 5.4 Memory-mapped I/O

5.2.2 Analog-to-Digital (ADC)

The analog to digital converters is treaded as an input device by the microprocessor that sends an
initializing signal to the ADC to start the analogy to digital data conversation process. The start of
conversation signal is a pulse of a specific duration.

The process of analog to digital conversion is a slow process, and the microprocessor has to wait
for the digital data until the conversion is over. After the conversion is over, the ADC sends End
Of Conversion (EOC) signal to inform the microprocessor that the conversion is over and the
result is ready at the output buffer of the ADC. These tasks of issuing an Start Of Conversion
(SOC) pulse to ADC, reading EOC signal from the ADC and reading the digital output of the ADC
are carried out by the CPU using I/O ports

The time taken by the ADC from the active edge of SOC pulse until the active edge of EOC signal
is called as the conversion delay of the ADC. It may range anywhere from a few microseconds
in case of fast ADC to even a few hundred milliseconds in case of slow ADCs.

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The available ADC in the market use different conversion techniques for conversion of analog
signal to digitals are two types. Successive approximation and Dual slop technique.

1. Successive approximation techniques

A successive approximation ADC is a type of analog-to-digital converter that converts a

continuous analog waveform into a discrete digital representation via a binary search through all
possible quantization levels before finally converging upon a digital output for each conversion..
It comprises a comparator, digital to analog converter, register, and a control circuit. The shown
below:

Fig 5.5 Successive approximation techniques

2. Dual slope integration techniques

In dual slope type ADC, the integrator generates two different ramps, one with the known analog
input voltage VA and another with a known reference voltage –Vref. Hence it is called a Dual
slope ADC. The logic diagram for the same is shown below.

Fig 5.5 Dual slope integration techniques ADC