CEG2136: Computer Architecture I

CEG2536: Architecture des Ordinateurs I

MIDTERM EXAMINATION

Profs. Voicu Groza and Rami Abielmona

Duration: 1 hour and 20 minutes November 3, 2012, 9:00

Name: _____________________________________________________

SID: __________________________________________

Signature:__________________________________________________

 Closed book exam. All electronic devices including calculators are not allowed.
 If in doubt how to interpret a question, make an assumption and elaborate your solution
based on this hypothesis. Explain all your assumptions and clearly define the symbols
used.
 If you finish 10 minutes or less before the due time, remain seated until the end of the
exam.

Question 1.1 (26) Question 2.2 (6)

Question 1.2 (12) Question 3 (30)

Question 2.1 (6) Question 4 (20)

Total (100)

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Question 1

1.1 (26 points )

The two’s complement representation of signed numbers is employed in four 11-bit registers
A, B, C and D. Registers A and B carry the following signed numbers: A = 01000001111
and B = 01000000110.
a. (4 pts) Compute C = B − A. Show your work in detail. The result is an 11-bit signed
number and is stored in the 11-bit register C. What is the content of C after the operation?

C = B – A = B + (-A) = 010 0000 0110 + 2’s compl (01000001111) =

Carry: 0 0 0 0 0 0 0 0 0 0 0 Verification in decimal: Not required!

B 0 1 0 0 0 0 0 0 1 1 0 =512+4+2 = 518
-A 1 0 1 1 1 1 1 0 0 0 1 =‐(010 0000 1111)=‐(512+15)= ‐527
C 1 1 1 1 1 1 1 0 1 1 1 ‐9

b. (4 pts) Convert the content of the register C to its equivalent decimal number. Show your
work in detail.
In 2’s complement representation:
C = 111 1111 0111 represents a negative number (say – c) since the msb, the sign bit = 1.
The magnitude of C, i.e., c = - (-c) = - C = 2’s complement (C) = 000 0000 1001 = 910
=> C = -9, which is confirmed by performing B-A in decimal

c. (4 pts) How would a computer detect an overflow in this operation? Justify your answer.
OFL = Cy12 XOR Cy11 = 0
or
OFL = if the operands have the same sign bit, but different from the result’s sign bit

d. (4pts) Compute D = A + B. Show your work in detail. The result is an 11-bit signed
number and is stored in an 11-bit register D. What is the content of D after the operation?

Carry: 0 1 0 0 0 0 0 1 1 1 0
A 0 1 0 0 0 0 0 1 1 1 1
B 0 1 0 0 0 0 0 0 1 1 0
D 1 0 0 0 0 0 1 0 1 0 1

e. (4pts) Convert the content of the register D to its equivalent decimal number. Show your
work in detail.

D = 100 0001 0101 represents a negative number (say – d) since the msb, the sign bit = 1.
The magnitude of D, i.e., d = - (-d) = - D = 2’s complement (D) = 011 1110 1011 =
011 1111 1111 – 000 0001 0100 = (210 -1) – (16+4) = 1023 – 20 = 1003
=> D = -1003 ≠ 1045 !!!

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 f. (6pts)
i. How would a computer detect an overflow in this operation (A+B)?

OFL = Cy12 XOR Cy11 = 1

or
OFL = if the operands have the same sign bit, but different from the result’s sign bit

ii.Applying that reasoning to this case, would an overflow be detected? Justify your
answer.
YES. Some explanations in the line with the following would be OK
Carry: 0 1 0 0 0 0 0 1 1 1 0 Verification in decimal: !
A 0 1 0 0 0 0 0 1 1 1 1 =512+15= 527
B 0 1 0 0 0 0 0 0 1 1 0 512+4+2 = 518
D 1 0 0 0 0 0 1 0 1 0 1 = -1003 ≠ 1045 > 1023  Overflow
10 10
D’s range is [-2 , 2 -1] = [-1024, 1023], so 1045 cannot be represented by D.

1.2 (12 points)

The 2's complement representation is used in an 8-bit register which contains the binary value
10011100.
a. What is the register value after an arithmetic shift right? Give your result both in binary
and decimal.

R 1 0 0 1 1 1 0 0
R >> 1 1 0 0 1 1 1 0

b. Starting again from the initial number 10011100, determine the register value after an
arithmetic shift left, both in binary and decimal.

R 1 0 0 1 1 1 0 0
<< R 0 0 1 1 1 0 0 0

c. Is there any overflow? Justify your answer.

Shifting to the left is equivalent to multiplication with 2, which may create overflow.
If signed numbers => here changes the sign => BAD! OFL
If unsigned numbers, the shifted number is smaller than the initial value => BAD, OFL

d. What arithmetic operations are performed by these shifts?

a = division by 2
b = multiplication by 2

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Question 2

2.1 (6 points)

You have a SRAM memory chip with a capacity of 64k x 8

a) How many data lines does it have?

Answer a) .......8......................
b) How many address lines does it have?
Answer b) ...16 (from 26 x 210 = 216 ..
c) What is its capacity expressed in "bits"?
Answer c) ... 216 x 23 = 219 = 210.x.
29.= 512 kb...........

2.2 (6 points)

A digital computer has a common bus system for 16 registers of 32 bits each.
The bus is constructed with multiplexers.

a. How many selection inputs are there in each multiplexer?

Answer a. ..4 since 16 = 24 data inputs ...........................
b. How many data inputs are there in each multiplexer?
Answer b. ..16 = since 16 sources of data (registers) are to be multiplexed...........................
c. How many multiplexers are there in the bus?
Answer c. . 32 16-input multiplexers, i.e., 1 for each bit of a register (see below), or
one 16-input multiplexer with each input 32 bits wide............................

b0
R1 b0
b1
R1 b1
b30 b0
R1 b30
b31
R1 15
R15 b1 b31
R1
b0
b30
R1 b1
b31 14
R14
b30
b0
R1 b31
b1
R1
b30 b0
R1 R1 1
b31 b1
R1 R1
b30
R1 0
b31
R0
4
S3‐S0
 Question 3 (30 points)

Design a 3-bit multi-function register R (R2R1R0) whose operation is described in the following
table, where K1 and K0 are two control bits.
Use in your design JK flip flops, logic gates and any digital components (encoders, decoders,
multiplexers, etc.); draw a detailed diagram of the logic circuit of the multi-function register.

Function table of 3-bit register R.

D2 D1 D0
Clock K1 K0 Operation
K1
↑ 0 0 No change K0
Register R

↑ 0 1 Loading external inputs, say D2 D1 D0

↑ 1 0 Increment by 3 R2 R1 R0

↑ 1 1 Decrement by 1

Characteristic Excitation
Table Table
J K Q(n) Q(n+1) Q(n) Q(n+1) J K Remember the generation of the FF excitation equations:
0 0 0 x 0 0 0 x  Copy to J the next state Q(n+1) if Q(n)=0
0 1 1 x 0 1 1 x
1 0 x 1 1 0 x 1  Copy to K the complement of the next state Q(n+1) if Q(n)=1
1 1 x 0 1 1 x 0  J and K should be “x” otherwise

C1 C0 = 00 => no change <=> Ai (n+1) = Ai (n) ; i= {0,1,2}

=> J2 = 0; K2 = 0; J1 = 0; K1 = 0; J0 = 0; K0 = 0.

C1 C0 = 10 =>Increment by 3
Present State Next State FF Inputs
R2 (n) R1 (n) R0 (n) R2(n+1) R1(n+1) R0(n+1) J2 K2 J1 K1 J0 K0
0 0 0 0 1 1 0 x 1 x 1 x
0 0 1 1 0 0 1 x 0 x x 1
0 1 0 1 0 1 1 x x 1 1 x
0 1 1 1 1 0 1 x x 0 x 1
1 0 0 1 1 1 x 0 1 x 1 x
1 0 1 0 0 0 x 1 0 x x 1
1 1 0 0 0 1 x 1 x 1 1 x
1 1 1 0 1 0 x 1 x 0 x 1

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J2 K2
R1 R0 00 01 11 10 R1 R0 00 01 11 10 J2 = K2 = R0 + R1
R2 R2
0 0 1 1 1 0 x x x x J1 = K1 = R0’

1 x x x x 1 0 1 1 1 J0 = K0 =1

C1 C0 = 11 =>Decrement by 1
Present State Next State FF Inputs
R2 (n) R1 (n) R0 (n) R2(n+1) R1(n+1) R0(n+1) J2 K2 J1 K1 J0 K0
0 0 0 1 1 1 1 x 1 x 1 x
0 0 1 0 0 0 0 x 0 x x 1
0 1 0 0 0 1 0 x x 1 1 x
0 1 1 0 1 0 0 x x 0 x 1
1 0 0 0 1 1 x 1 1 x 1 x
1 0 1 1 0 0 x 0 0 x x 1
1 1 0 1 0 1 x 0 x 1 1 x
1 1 1 1 1 0 x 0 x 0 x 1

J2 K2
R1 R0 00 01 11 10 R1 R0 00 01 11 10 J2 = K2 = R0’ R1’ = (R0 + R1)’
R2 R2
0 1 0 0 0 0 x x x x J1 = K1 = R0’

1 x x x x 1 1 0 0 0 J0 = K0 =1

C1 C0 = 01 =>Load D2D1D0 to R2R1R0:

<=> Ri (n+1) = Ii (n) ; i= {0,1,2}

Ri(n) Di Ri(n+1) Ji Ki
0 0 0 0 x
0 1 1 1 x
1 0 0 x 1
1 1 1 x 0

Ji = Ki = Di xor Ri or
Ji = Di ; Ki = D1’
or …

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Conclusion
(T FF approach, i.e., J = K = T):
K1 K0 J2 = K2 J1 = K1 J0 = K0
0 0 0 0 0
0 1 D2 xor R2 D1 xor R1 D0 xor R0
1 0 R0 + R1 R0’ 1
1 1 R0‘ R1’ R0’ 1

D FF + adders approach: CLK

C1C0
R+3 = R+011 C1
0
R- 1 = R+111 0 Cout2 0
J Q
2M
1
1 Σ2 R2
Cin2
3
U
D2 1
X K Q

Cout1 0
1 J Q
Σ1 2M R1
Cin1
3
U
D1 1
X K Q

Cout0 0
1 J Q
Σ0 2M R0
Cin0
3
U
0 X K Q
D0 1

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 Comprehensive description but longer approach:

Control Present State Next State FF Inputs FF input equations

C1C0 R2(n) R1(n) R0(n) R2(n+1) R1(n+1) R0(n+1) J2 K2 J1 K1 J0 K0
00 0 0 0 0 0 0 0 x 0 x 0 x
0 0 1 0 0 1 0 x 0 x x 0 J2 = K2 = 0
0 1 0 0 1 0 0 x x 0 0 x
0 1 1 0 1 1 0 x x 0 x 0 J1 = K1 = 0
1 0 0 1 0 0 x 0 0 x 0 x
1 0 1 1 0 1 x 0 0 x x 0 J0 = K0 = 0
1 1 0 1 1 0 x 0 x 0 0 x
1 1 1 1 1 1 x 0 x 0 x 0
01 0 0 0 I2 I1 I0 I2 x I1 x I0 x
0 0 1 I2 I1 I0 I2 x I1 x x I0’ J2 = D2
0 1 0 I2 I1 I0 I2 x x I1’ I0 x K2 = D2’
0 1 1 I2 I1 I0 I2 x x I1’ x I0’ J1 = D1
1 0 0 I2 I1 I0 x I2’ I1 x I0 x K1 = D1’
1 0 1 I2 I1 I0 x I2’ I1 x x I0’ J0 = D0
1 1 0 I2 I1 I0 x I2’ x I1’ I0 x K0 = D0’
1 1 1 I2 I1 I0 x I2’ x I1’ x I0’
10 0 0 0 0 1 1 0 x 1 x 1 x
0 0 1 1 0 0 1 x 0 x x 1 J2 = K2 = R0 + R1
0 1 0 1 0 1 1 x x 1 1 x
0 1 1 1 1 0 1 x x 0 x 1 J1 = K1 = R0’
1 0 0 1 1 1 x 0 1 x 1 x
1 0 1 0 0 0 x 1 0 x x 1 J0 = K0 =1
1 1 0 0 0 1 x 1 x 1 1 x
1 1 1 0 1 0 x 1 x 0 x 1
11 0 0 0 1 1 1 1 x 1 x 1 x
J2 = K2 = R0’ + R1’ =
0 0 1 0 0 0 0 x 0 x x 1
(R0R1)’
0 1 0 0 0 1 0 x x 1 1 x
0 1 1 0 1 0 0 x x 0 x 1 J1 = K1 = R0
1 0 0 0 1 1 x 1 1 x 1 x
1 0 1 1 0 0 x 0 0 x x 1 J0 = K0 =1
1 1 0 1 0 1 x 0 x 1 1 x
1 1 1 1 1 0 x 0 x 0 x 1

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Question 4 (20 points)
A 3-bit arithmetic circuit takes three control bits, x, y and z, and two 3-bit data inputs, A and
B. The operations supported by the arithmetic unit are described in the following table.
Draw a detailed logic diagram of the circuit using 1-bit full adders and the digital components of
your choice (encoders, decoders, multiplexers, etc.)
(Note: X’ is the 1’s complement of X)

xy z=0 z=1
00 F = A + B (add) F=A+B+1
01 F = A + B’ F = A - B (subtract)
10 F = A (transfer) F = A + 1 (increment)
11 F = A - 1 (decrement) F = A’ + 1 (2’s complement)

xy z= 0 z= 1
00 A3 A2 A1 A0 + B3 B2 B1 B0 + 0 A3 A2 A1 A0 + B3 B2 B1 B0 + 1
01 A3 A2 A1 A0 + B3’B2’B1’B0’+ 0 A3 A2 A1 A0 + B3’B2’B1’B0’+ 1
10 A3 A2 A1 A0 + 0 0 0 0 + 0 A3 A2 A1 A0 + 0 0 0 0 + 1
11 A3 A2 A1 A0 + 1 1 1 1 + 0 A’3A’2A’1A’0+ 0 0 0 0 + 1