Laptop Chip Level Repair Guide 362

Chapter 16

Analysis of APPLE A1286

(HM5x) Timing Sequence

Apple A1286 (K18), the mainboard part number is 820-2850, it's the product
used Intel 5 series chipset. In this chapter, detailed analysis of the standby and
power- on timing sequence of Apple laptop.

16.1: G3 State
First insert the adapter to produce PPDCIN_G3H, is shown in figure 16-1.

Figure 16-1: The adapter enters to a circuit

The adapter access socket of Apple needs a small adapter, the access of the
power head (connector) is the magnet attracting type. There have 5 contacts:
both ends are grounded, the middle most is the adapter ID information
identification and the other two roots are the positive & negative of the power
supply, the specific kind is shown in figure 16-2.

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Figure 16-2: The kind of the Apple adapter

PPDCIN_G3H through the body diode of Q7080 to produce
PPDCIN_G3H_OR_PBUS is shown in figure 16-3. (In the battery mode, the battery
through the body diode of Q7055 and through the top tube Q7030 of the charging
circuit, then through the body diode of Q7085D to supply the power to
PPDCIN_G3H_OR__PBUS).

Figure 16-3: The production circuit of PPDCIN_G3H_OR_PBUS

PPDCIN_G3H_OR_PBUS supplies the power to VIN of U6990 (IT3970),and is
added to EN directly, the chip outputs PP3V42_G3H,is shown in figure 16-
4.This is a step-down switching regulator, internal integrates the booster and the
clamping diodes. The pin definition VIN means the power supply, EN means
the open, and RT means the oscillation setting. BOOST means start boot-strap
pin, SW means phase/output pin. FB means feedback, BD connects the internal
boost diode and the voltage regulator.

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Figure 16-4: The production circuit of PP3V42_G3H

PP3V42_G3H supplies the power to VR5020, VR5020 outputs
PP3V3_S5_AVREF_SMC, is shown in figure 16-5.
PP3V42_G3H supplies the power to AVCC of EC, PP3V3_S5_AVREF_SMC
supplies the power to AVREF of EC, is shown in figure 16-6.

Figure 16-5: The circuit screenshot of VR5020

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Figure 16-6: EC received the power supply

After EC receiving the standby power supply, to supply the power to Y5010,
and produces 20MHz clock to EC, is shown in figure 16-7.

Figure 16-7: The standby clock of EC

PP3V42_G3H inputs the voltage to U5000, U5000 is a voltage detection/delay
chip, the chip through C5001 charging delayed, when the voltage rises above
the threshold value, OUT pin open drain outputs, SMC_RESET_L is pulled up
to be 3.42V by R5000 to EC reset, is shown in figure 16-8

Figure 16-8: The production circuit of EC reset

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In the figure 16-8, there have a circuit of hand reset EC: when EC program is
disordered, we can achieve the mandatory reset EC through the circuit of U5001
and Q5032 (shown in figure 16-9).while pressing the left SHIFT key, the left
OPTION key and CONTROL key, sends to U5703 to produce the low level of
SMC_TPAD_RST_L. Then press the switch to produce the low level of
SMC_ONOFF_L, together with SMC_TPAD_RST_L to send to U5001,
outputs the high level of SMC_TPAD_RST, controls Q5032 conducted, and
pulls SMC_RESET_L low.

Figure 16-9: The circuit screenshot of U5703

After the EC standby power supply, clock and reset all being normal, it will
reads their own program.
When insert the adapter, PPDCIN_G3H through D7005 and R7005 to supply
the power to DCIN of the charging chip ISL6259, and through R7010 and
R7011 partial pressure to ACIN, is shown in figure 16-10. After ACIN voltage
being higher than 3.2V, ISL6259 outputs the low level of AGATE to make
Q7085 conducted, and start PWM control produce the common point
PPBUS_G3H with 12.6V(the common point voltage setting: PP3V42_G3H
through R7012 to pull up CELL to set to be 12.6V). After the charging chip
detecting that the current flowed through R7020 is higher than 0.4A (the adapter
current sense resistor R7020 voltage drop 8mV), drive SGATE is low level;
when the current is less than 0.15A (the adapter sense resistor R7020 voltage
drop 3mV), drive SGATE is high level.

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Figure 16-10: The screenshot of the charging chip circuit & location

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The common point production method is different with other brand machines.
In the figure 16-11, it is adopts a hybrid power supply scheme: the voltage of
the adapter needs to be regulated by the charging chip to produce a common
point, the voltage is equal to the battery voltage. The advantage is that it no
needs to change any circuit and directly support Intel core technology.

Figure 16-11: The production method for Apple Laptop Common Point
After U7000 detecting that ACIN is higher than 3.2V, it will open drain output
SMC_BC_ACOK. One path of SMC_BC_ACOK is sent to EC, means that the
adapter inserted, another path is sent to OR GATE U6901 to produce
SMC_BC_ACOK_VCC to supply the power to MAX9940 (U6900), is shown in
figure 16-12.

MAX9940 is a signal line over-voltage protector, the simple principle: DC over-

voltage protection, when EXT voltage is higher than VCC +0.26V (the
threshold value is shown in figure 16-13), the chip disconnects 4 pin and 5 pin,
that is to say,5 pin of the adapter interface J6900 isolated from SYS_ONEWIRE
of EC, to prevent damage to EC; when VCC= 0V, EXT has the protective range of
-0.7~28V; the chip can prevent ±4kV static electricity.

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ONE-WIRE is a single wire serial bus, is used to transfer the adapter

information. After EC reading the parameter of the adapter through ONE-WIRE
bus, the green light on the adapter is on.

Figure 16-12: The circuit screenshot of MAX9940

Figure 16-13: The screenshot of the description of the electrical features of EXT
threshold value in the MAX9940 data manual

Figure 16-14: The internal structure of the MAX9940

Tips: ONE-wire is a unique single bus (l-Wire Bus) technology launched by the
US Maxim wholly owned subsidiaries Dallas Semiconductor Corporation,
Dallas (DALLAS SEMI CONDUCTOR).This technology is different with
SPI,PC,SCI bus, it adopts the a single signal line, it can transmit the clock and
the data, and the data transmission is bidirectional, so the single bus technology

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has the advantages of simple circuit, low hard overhead, low cost, convenient
for bus expansion and maintenance, etc.

16.2: RTC Circuit

The origin of VCCRTC of this machine is supplied the power directly by
PP3V42_G3H, no CMOS battery, is shown in figure 16-15.

Figure 16-15: The power supply of VCCRTC

RTCRST# and SRTCRST# comes from the delayed of the following circuit,
other two signals of RTC circuit are INTRUDER# and INTVRMEN#, is pulled
up by 3.42V, is shown in figure 16-16.

Figure 16-16: The screenshot of RTC circuit

RTC crystal 32.768KHz of PCH is Y2810, is shown in figure 16-17.

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Figure 16-17: RTC Crystal circuit

16.3: S5 State
After EC detecting that the adapter exists (SMC_BC_ACOK is high level),
sends the high level of SMC_PM_G2_EN,at the same time, it will send
SMC_ADAPTER_EN to PCH, to tell PCH that the adapter has inserted, is
shown in figure 16-18.

Figure 16-18: EC sends SMC_PM_G2_EN signal

SMC_PM_G2_EN is sent to ENO of TPS51125 through R7272, as a linear

open, is shown in figure 16-19.The common point voltage PPBUS_G3H is sent to
16 pin VIN as the main power supply, TPS51125 outputs two paths of linear
power supply, VREG3 and VREG5. VREG3 is not to be used, VREG5 output
voltage is PP5V_S5.

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Figure 16-19: The circuit screenshot of standby power supply

PP5V_S5 through R2400 to produce PP5V_S5_PCH_V5REFSUS, is shown in

figure 16-20. PP5V_S5_PCH_V5REFSUS supplies the power to 5V standby
voltage V5REF_SUS of the bridge.

Figure 16-20: The production circuit of PP5V_S5_PCH_V5REFSUS

SC_PM_G2_EN also converted to be P3V3S5_EN, is shown in figure 16-21.

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Figure 16-21: The production of P3V3S5

The high level of P3V3S5_EN controls 6-1 pin of Q7211 to be conducted,3-4
pin will be cut off,6 pin ENTRIP2 of TPS51125 will be grounded through the
resistance R7206,sets the over current protection threshold value of the second
path PWM controller, is shown in figure 16-22.

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Figure 16-22: The control circuit of the standby chip ENTRIP2

TPS51125 internal supplies pull-up to ENTRIP2.partial pressure with R7206
into a high level to open the second path PWM of the chip. Produces PP3V3_S5,
is shown in figure 16-23. (There is only a 3.3V inductance power on when this
machine is in standby. And 5V inductance is no power. PP3V3_S5 is sent to
VCCSUS3_3 of PCH at last; as the standby power supply of the bridge.

After PP3V3_S5 being normal, U7940 through 5 pin to detect PP3V3_S5, is

shown in figure 16-24.

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Figure 16-23: The production circuit of PP3V3_S5

Figure 16-24: PP3V3_S5 detection circuit

According to the pin definition of TPS3808G33 (shown in figure 16-25), 5 pin

is the voltage detection pin. When this pin is less than the threshold value VIT
, RESET* is effective.

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Figure 16-25: The screenshot of the pin definition of TPS3808G33

The threshold value of TPS3808G33 detection voltage is 3.07V, is shown in

figure 16.26.

Figure 16-26: The screenshot of description of the electrical features of the

voltage detection threshold value in the TPS3808G33 data manual
The high level of RSMRST_PWRGD is sent to EC, after EC receiving
RSMRST_PWRGD, sends PM_RSMRST_L to the bridge, is shown in figure
16-27.

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Figure 16-27: The related circuit of RSMRST#

In the figure 16-27, there is a power-on condition of PCH: BATLOW*.This

signal is low battery indicator. When this signal is low level, PCH forced to
enter S5 state. When it works normally, it must be high level, is pulled up by
PP3V3_S5, and controlled by EC. EC needs to detect the battery, and then it
will set high PM_BATLOW_L, is shown in figure 16-28.

Figure 16-28: BATLOW# circuit trigger

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16.4: Trigger
The power switch of this machine is on the keyboard, is shown in figure 16-29,
press the switch, producing the low level of pulse signal SMC_ONOFF_L.

Figure 16-29: The keyboard interface

SMC_ONFF_L is sent to J4 pin of EC, after EC receiving SMC_ONOFF_L,

sends PM_PWRBTN_L from D10 pin, is shown in figure 16-30.

Figure 16-30: EC received the trigger signal

PM_PWRBTN_L is sent to PWRBTN* pin of PCH, is shown in figure 16-31.

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Figure 16-31: PCH received the trigger signal

16.5: S3 and S0 State

After the bridge receiving PM_PWRBTN_L, it will send SLP_S5#, SLP_S4#,
SLP_S3#, SLP_M#, is shown in figure 16-32. This machine not supports Intel
AMT, SLP_M# is not used.

Figure 16-32: PCH send each power-on signal

PM_SLP_S5_L is sent to EC; PM_SLP_S4_L is also sent to EC, at the same
time sent to Q7812 through converted control to produce PP3V3_S3 voltage, is
shown in figure 16- 33.

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Figure 16-33: The production circuit of PP3V3_S3

PM_SLP_S4_L also converted to be P5VS3_EN and DDRREG_EN, is shown
in figure 16-34.

Figure 16-34: PM_SLP_S4 renamed

DDRREG_EN is sent to S5 pin of TPS51116, this is a typical memory power
supply chip, and it will output PWM power supply PP1V5_S3 and
PPVTTDDR_S3, is shown in figure 16-35. After the memory main power
supply and the reference voltage being normal, TPS51116 will output
DDRREG PGOOD.

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Figure 16-35: The memory power supply circuit

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P5VS3_EN is converted to control 1 pin of TPS51125, is used to control

produce PP5V_S3, is shown in figure 16-36. After PP5V_S3 being normal,
TPS51125 will send P5V3V3_PGOOD (after previous PP3V3_S5 producing,
PG of TPS51125 will not output, only when 5V is normal, it will open drain
outputs PGOOD).

Figure 16-36: The production circuit of PP5V_S3

PM_SLP_S4_L is also sent to Q4690, it is used to control produce USB power

supply PP5V_S3_RTUSB_A_ILIM, PP5V_S3_RTUSB_B_ILIM, is shown in
figure 16-37.

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Figure 16-37: The production circuit of USB power supply

The bridge sends SLP_S3#, it is renamed to be PM_SLP_S3_L, in addition to
EC, it is also sent to the following places.
Control the production of PP3V3_S0, is shown in figure 16-38. Control
production of PP5V_S0, is shown in figure 16-39.

Figure 16-38: The production circuit of PP3V3_S0

Figure 16-39: The production circuit of PP5V_S0

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Control to open the 3.3V network card power supply PP3V3_ENET, and
produce PM_ENET_EN, is shown in figure 16-40.Here refers only in the
condition of the function of the network awaken been closed to be used to open
the network card power supply. If open the function of network awaken, and is in
the adapter state, Q7920 will be conducted, and pull PM_ENET_EN_L low, and
open ENET voltage.

Figure 16-40: The control of the network card power supply

Controlling open U9480 to produce PP3V3_SO_DPPWR to DP interface J9400

power supply (J9400 is Mini Display Port), is shown in figure 16-41.

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Figure 16-41: The production of DP interface power supply

Controlling 5315 conducted, converted the common point voltage PPBUS_G3H
to be PPBUS_G3H_VSENSE, then through partial pressure to produce
SMC_PBUS_VSENS to EC, is used to detect the common point voltage, and is
shown in figure 16-42.

Figure 16-42: The screenshot of the common point voltage detection circuit

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PM_SLP_S3_L through the resistance R3210 to pull up MEMVTT_EN, when

the subsequent platform reset PIT_RESET_L is effective, control 3 pin and 4
pin of Q3210 to be conducted, or ISOLATE_CPU_MEM_L is the high level to
control Q3200 conducted, and produces the low level of MEMVTT_EN_L to
control 6 pin and 1 pin of Q3210 cut off, MEMVTT_EN is pull up by
PM_SLP_S3_L, is sent to U7300, and U7300 receives PP0V75_S0_DDRVTT
output from VTT of 24 pin.
0

Figure 16-43: The control circuit of the memory VTT voltage

PM_SLP_S3_L will also through the circuit in the figure 16-44 to
convert to P1V8S0_EN, P1V2S0_EN, CPUVTTS0_EN and PlV5CPU_EN, is
shown in figure 16-45.

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Figure 16-44: PM_SLP_S3_L renamed

Figure 16-45: The production of P1V5CPU_EN

P1V8S0_EN is sent to U7720 to open PP1V8_S0, is shown in figure 16-46.

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Figure 16-46: The production circuit of PP1V8_S0

P1V2S0_EN is sent to U7850, makes it send the control signal of 7 pin to drive
Q7850 to produce PPlV2_S0, is shown in figure 16-47.

Figure 16-47: The production circuit of PP1V2_S0

In the figure 16-47, the output voltage 1V2_ENET of Q7850 is output by

PM_ENET_EN controlling U7760, is shown in figure 16-48.

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Figure 16-48: The production circuit of PP1V2_ENET

CPUVTTS0_EN is sent to U7600 control output PPlV05_SO, is shown in

figure 16-49.

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Figure 16-49: The production circuit of PP1V05_S0

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P1V5CPU_EN is sent to U7801, controls Q7801 to convert PP1V5_S3 power

supply of the memory to be PP1V5_S3RS0 to supply the power to CPU, is
shown in figure 16-50.

Figure 16-50: The production circuit of PP1V5_S3RS0

After the previous voltage all being normal, U7971detects PP3V3_S0,
PP1V5_S3RS0, PP1V05_S0, and after being higher than each threshold value,
RST# open drain outputs S0PGOOD_PWROK, is shown in figure 16-51.

Figure 16-51: The voltage detection circuit

S0PGOOD_PWRO phased with PG output by other power supply chip, and is

pulled up to be S0_PWR_PGOOD by PP3V3_S0, is shown in figure 16-52.
S0_PWR_GOOD is sent to U7980, phase with ALL_GFX_PGOOD pulled up
by PP3V3_S5 (R7991 did not install parts), and commonly produce
ALL_SYS_PWRGD to EC. This circuit can be called as "Big OR GATE".

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Figure 16-52: The "Big OR GATE" circuit

One path of ALL_SYS_PWRGD is sent to EC, after EC receiving
ALL_SYS_PWRGD, then sends CPUIMVP_VR_ON, is shown in figure 16-53.

Figure 16-53: EC sends CPUIMVP_VR_ON

CPUIMVP_VR_ON is sent to 35 pin of U7400 TPS51621, opens the CPU

power supply PPVCORE_S0_CPU, is shown in figure 16-54. After CPU power
supply being normal, sends CPUIMVP_PGOOD and CPUIMVP_CLK_EN_L.

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Figure 16-54: The production circuit of CPU power supply

In the circuit of power supply, after the bus power supply producing, supplies
power to CPU, CPU will send GFX_VR_EN to open CPU internal integrated
graphics power supply, is shown in figure 16-55.

Figure 16-55: CPU sends GFX_VR_EN

GFX_VR_EN is sent to 25 pin of U7500 TPS51981, the power supply chip

outputs the integrated graphics power supply PPVCORE_SO_GFX. After the
integrated graphics power supply being normal, the chip open drain outputs PG
but the resistance connected to this pin is not installed, it means that it does not
use this path of PG is shown in figure 16-56.

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Figure 16-56: The integrated graphics power supply circuit

16.6: The Clock, PG and The Reset

After CPU power supply being normal, the power chip sends
CPUIMVP_PGOOD to send to U2850 and phase with ALL_SYS_PWRGD, to
form PM_PCH_PWRGD to send to the bridge, to three PG pins of the bridge:
SYS_PWROK, PWROK, MEPWROK(SYS_PWROK means that CPU power
supply is normal).PWROK means that other SO voltage is normal, MEPWROK
means that the voltage opened by SLP_M# is normal, but SLP_M# is not used
in this machine, so directly connected by PG of the SO voltage), is shown in
figure 16-57.

Figure 16-57: PM_PCH_PWRGD is sent to PCH

CPUIMVP_CLK_EN_L through U2790 the NAND gate inverted is sent to
U2700 clock chip to open each clock (27MHz of the clock chip is controlled by
16 pin, haven't open temporarily), is shown in figure 16-58.

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Figure 16-58: The clock circuit

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After PCH satisfying the power supply, the clock and PG sends
DRAMPWROK, PROCPWRGD to CPU, is shown in figure 16-
59.

Figure 16-59: Send DRAMPWROK & PROCPWRGD to CPU

PCH sends PLTRST# and PCIRST#, the PCIRST is vacant and not to be used.
It is shown in figure 16-60.

Figure 16-60: PCH send the reset

PLT_RESET_L converted to each kinds of RESET, sends to onboard chip, is
shown in figure 16-61. PLT_RESET_L is also sent to U2880 to phase with
PP3V3_S0 to produce PLT_RST_BUF_L.

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Figure 16-61: PLTRST_RESET_L conversion circuit

PLT_RST_BUF_L through R1125 and R1126 partial pressure to be 1.1V to
send to CPU reset pin RSTIN# is shown in figure 16-62.

Figure 16-62: CPU reset circuit

Finally, the hard reset is completed now.

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