eGaN® FET DATASHEET EPC8009

EPC8009 – Enhancement Mode Power Transistor

VDS , 65 V D

G
RDS(on) , 130 mΩ EFFICIENT POWER CONVERSION

ID , 4 A S
HAL

Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very
low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG
and zero QRR. The end result is a device that can handle tasks where very high switching frequency,
and low on-time are beneficial as well as those where on-state losses dominate.

Maximum Ratings EPC8009 eGaN FETs are supplied only in

PARAMETER VALUE UNIT passivated die form with solder bars
Drain-to-Source Voltage (Continuous) 65
Die Size: 2.1 mm x 0.85 mm
VDS V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 125°C) 78 Applications
Continuous (TA = 25°C, RθJA = 33°C/W) 4 • Ultra High Speed DC-DC Conversion
ID A
Pulsed (25°C, TPULSE = 300 µs) 7.5 • RF Envelope Tracking
Gate-to-Source Voltage 6 • Wireless Power Transfer
VGS V
Gate-to-Source Voltage –4 • Game Console and Industrial Movement
TJ Operating Temperature –40 to 150 Sensing (Lidar)
°C
TSTG Storage Temperature –40 to 150 Benefits
• Ultra High Efficiency
• Ultra Low RDS(on)
Thermal Characteristics • Ultra Low QG
PARAMETER TYP UNIT • Ultra Small Footprint
RθJC Thermal Resistance, Junction-to-Case 8.2
RθJB Thermal Resistance, Junction-to-Board 16 °C/W
RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 82
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details

Static Characteristics (TJ= 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 µA 65 V
IDSS Drain-Source Leakage VDS = 52 V, VGS = 0 V 50 100 µA
Gate-to-Source Forward Leakage VGS = 5 V 100 500
IGSS µA
Gate-to-Source Reverse Leakage VGS = -4 V 50 100
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.25 mA 0.8 1.4 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 0.5 A 90 130 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 2.2 V
Specifications are with substrate connected to source where applicable.

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eGaN® FET DATASHEET EPC8009

Dynamic Characteristics (TJ= 25˚C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CISS Input Capacitance 45 52
COSS Output Capacitance VGS = 0 V, VDS = 32.5 V 19 28 pF
CRSS Reverse Transfer Capacitance 0.5 0.8
RG Gate Resistance 0.3 Ω
QG Total Gate Charge 370 450
QGS Gate-to-Source Charge 120
VDS = 32.5 V, VGS = 5 V, ID = 1 A
QGD Gate-to-Drain Charge 55 94
pC
QG(TH) Gate Charge at Threshold 96
QOSS Output Charge VGS = 0 V, VDS = 32.5 V 940 1400
QRR Source-Drain Recovery Charge 0
Specifications are with substrate connected to source where applicable.

Figure 1: Typical Output Characteristics at 25°C Figure 2: Transfer Characteristics

8 8
VGS = 5 25˚C
7 VGS = 4 7 125˚C
VGS = 3
6 VGS = 2 6 V DS = 3 V
ID– Drain Current (A)

ID– Drain Current (A)

5 5

4 4

3 3

2 2

1 1

0 0
0 0.5 1 1.5 2 2.5 3 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VDS– Drain-to-Source Voltage (V) VGS– Gate-to-Source Voltage (V)

Figure 3: R DS(on) vs. VGS for Various Drain Currents Figure 4: R DS(on) vs. VGS for Various Temperatures
400 400
ID= 0.5 A 25˚C
350
RDS(on) – Drain-to-Source Resistance (mΩ)
RDS(on)– Drain-to-Source Resistance (mΩ)

ID= 1.0 A 350 125˚C

300 ID= 1.5 A ID = 1 A
300
ID= 2.0 A
250
250
200
200
150
150
100

50 100

0 50
2.0 2.5 3.0 3.5 4.0 4.5 5.0 2 2.5 3 3.5 4 4.5 5
VGS– Gate-to-Source Voltage (V) VGS– Gate-to-Source Voltage (V)

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 eGaN® FET DATASHEET EPC8009

Figure 5: Capacitance (Linear Scale) Figure 5A: Capacitance (Log Scale)

102
50

40
101

C – Capacitance (pF)
C – Capacitance (pF)

COSS = CGD + CSD

30 CISS = CGD + CGS COSS = CGD + CSD
CRSS = CGD CISS = CGD + CGS
CRSS = CGD
20
100

10

0 10-1
0 10 20 30 40 50 60 0 10 20 30 40 50 60

VDS– Drain-to-Source Voltage (V) VDS– Drain-to-Source Voltage (V)

Figure 6: Gate Charge Figure 7: Reverse Drain-Source Characteristics

5 8
ID= 1 A
7 25˚C
VDS = 32.5 V 125˚C
4
ISD– Source-to-Drain Current (A)

6 VGS = 0 V
VG– Gate Voltage (V)

3 5

4
2
3

2
1
1

0 0
0 100 200 300 400 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
QG– Gate Charge (pC) VSD– Source-to-Drain Voltage (V)

Figure 8: Normalized RDS(on) Figure 9: Normalized Threshold Voltage vs. Temperature

1.8
ID = 1 A 1.3 ID = 0.25 mA
Normalized On-State Resistance - RDS(on)

VGS = 5 V
Normalized Threshold Voltage (V)

1.6
1.2

1.1
1.4
1.0

1.2 0.9

0.8
1
0.7

0.6
0.8
0 25 50 75 100 125 150 0 25 50 75 100 125 150
TJ– Junction Temperature (°C) TJ– Junction Temperature (°C)

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eGaN® FET DATASHEET EPC8009

Figure 10: Gate Current Figure 11: Smith Chart

1.4
S-Parameter Characteristics
25˚C VGSQ = 2.36 V, VDSQ = 30 V, IDQ = 0.50 A
1.2 125˚C Pulsed Measurement, Heat-Sink Installed, Z0 = 50 Ω

1
IG– Gate Current (mA)

1.0
0.9

1.2
0.8

1.4
0.7

1.6
0.6

1.8
0.8

2.0
S11 – Gate Reflection

0.5
0.4
S22 – Drain Reflection

0
3.
0.3 EPC8009
0.6
4.0

5.0
0.2
6.0

3 GHz
GHz 8.0
10

0.4
0.1

20

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8
0.9
1.0

1.2

1.4

1.6
1.8
2.0

3.0

4.0

5.0

10
0
20

0.2 0.1
10
8.0

6.0
0.2
5.0
RF Café
2002

0 0.3
4.0

0 1 2 3 4 5 6

0
3.
0.4

VGS– Gate-to-Source Voltage (V) 200 MHz

0.5
200 MHz

2.0
1.8
0.6

1.6
0.7

1.4
0.8

1.2
0.9

1.0
All measurements were done with substrate shortened to source.

Figure 12: Gain Chart Figure 13: Device Reflection

Amplitude Gmax
[dB]
45 1.6
40 1.4
35 1.2
30 1
25 0.8
20 0.6 Z DS
15 0.4
Z GS
10 0.2
5 0
0 –0.2
100 1000
Frequency (MHz) Figure 14: Taper and Reference Plane details – Device Connection
Micro-Strip design: 2-layer
½ oz (17.5 µm) thick copper
30 mil thick RO4350 substrate
914 355
Frequency Gate (ZGS) Drain (ZDS)
All dimensions in µm
[MHz] [Ω] [Ω]
914
200 1.98 – j8.58 16.83 – j11.29
500 1.87 – j2.15 10.69 – j9.69
1621

1000 1.39 + j2.14 5.22 – j5.45

271

1200 1.21 + j3.56 3.53 – j3.42

271

1500 1.01 + j4.96 2.35 – j0.81

1621

2000 0.83 + j7.83 1.57 + j3.52

1000

2400 0.73 + j10.14 1.54 + j6.19

3000 0.58 + j14.27 1.84 + j10.20 Device Outline
149
S-Parameter Table - Download S-parameter files at www.epc-co.com Gate Circuit Drain Circuit
Reference Plane Reference Plane

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eGaN® FET DATASHEET EPC8009

Figure 15: Transient Thermal Response Curves

Junction-to-Board
1
Duty Factors:

ZθJB Normalized Thermal Impedance

0.5

0.2
0.1
0.1
0.05 T
0.02 P DM
tp
0.01 0.01
Single Pulse Notes:
Duty Factor = tp/T
0.001
Peak TJ = PDM x ZθJB x RθJB + TB
10-5 10-4 10-3 10-2 10-1 1 10 100
tp– Rectangular Pulse Duration (s)

Junction-to-Case
1
Duty Factors:
ZθJC Normalized Thermal Impedance

0.5
0.2
0.1
0.1
T
0.05 P DM
tp
0.02
0.01 0.01
Notes:
Single Pulse Duty Factor = tp/T
Peak TJ = PDM x ZθJC x RθJC + TC
0.001
10-6 10-5 10-4 10-3 10-2 10-1 1 10
tp– Rectangular Pulse Duration (s)

Figure 16: Safe Operating Area

10
ID - Drain Current (A)

1 Pulse Width (s)

100 ms
10 ms
1 ms
100 µs
0.1
0.1 1 10 100
VDS – Drain Voltage (V)

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eGaN® FET DATASHEET EPC8009

TAPE AND REEL CONFIGURATION

4mm pitch, 8mm wide tape on 7”reel Loaded Tape Feed Direction
d e f g

7” reel Die
b orientation
dot
ZZZZ
c Gate
a YYYY pad bump is
under this
8009 corner

Die is placed into pocket

EPC8009 (note 1) solder bump side down
Dimension (mm) target min max
(face side down)
a 8.00 7.90 8.30
b 1.75 1.65 1.85
c (see note) 3.50 3.45 3.55
d 4.00 3.90 4.10
e 4.00 3.90 4.10
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
f (see note) 2.00 1.95 2.05
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
g 1.5 1.5 1.6 not the pocket hole.

DIE MARKINGS

8009
YYYY
Laser Markings
ZZZZ Part
Part # Lot_Date Code Lot_Date Code
Die orientation dot Number
Marking Line 1 Marking line 2 Marking Line 3
Gate Pad bump is
under this corner EPC8009 8009 YYYY ZZZZ

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eGaN® FET DATASHEET EPC8009
DIE OUTLINE A
Solder Bar View Micrometers
d e e f Dim
Min Nominal Max
A 2020 2050 2080
B 820 850 880
3 5 C 555 580 605

X2
i
d 400 400 400
1 2 e 600 600 600
C
B

j
f 200 225 250
4 6 g 175 200 225
h 425 450 475
i 175 200 225
g h i
j 400 400 400
x2
Pad no. 1 is Gate
Pad no. 2 is Source Return for Gate Driver
Pad no. 3 and 5 are Source

(685)
Side View

815 Max
Pad no. 4 is Drain
Pad no. 6 is Substrate*

100 +/- 20
Seating Plane *Substrate pin should be connected to Source

RECOMMENDED LAND PATTERN (measurements in µm)

2050
The land pattern is solder mask defined.
400 600 600 Solder mask opening is 5 µm smaller per side than bump.

4 6 Pad no. 1 is Gate

Pad no. 2 is Source Return for Gate Driver
1 2
400
570

850

Pad no. 3 and 5 are Source

Pad no. 4 is Drain
3 5 Pad no. 6 is Substrate*
190

190

190
*Substrate pin should be connected to Source
440

RECOMMENDED STENCIL DRAWING (measurements in µm)

2050

4 6
250

272

1 2
200

200
592

850
R60

3 5

325 200 245 230 450 275 272 Blue = bump, Gray = stencil

Recommended stencil should be 4 mil (100 μm) thick, must be laser cut, openings per drawing. Intended for use with SAC305 Type 3 solder, reference 88.5% metals content.
Additional assembly resources available at: https://epc-co.com/epc/design-support/assemblybasics

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability,
function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it Information subject to
convey any license under its patent rights, nor the rights of others. eGaN® is a registered trademark of Efficient Power Conversion Corporation. change without notice.
EPC Patent Listing: https://epc-co.com/epc/about-epc/patents Revised July, 2023

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