6-Channel, Serial Input

Master/Balance Volume Controls

SSM2160
FEATURES FUNCTIONAL BLOCK DIAGRAM
Clickless Digitally Controlled Level Adjustment
SSM2160: 6 Channels
V+
7-Bit Master Control Gives 128 Levels of Attenuation POWER
SUPPLY AND
CH1 IN
5-Bit Channel Controls Give 32 Levels of Gain V– REFERENCE
GENERATOR
Master/Channel Step Size Set by External Resistors VREF VCA CH1 OUT
100 dB Dynamic Range
Automatic Power-On Mute 5-BIT
Excellent Audio Characteristics: CHANNEL
DAC
0.01% THD+N CH2 IN
0.001% IMD (SMPTE)
–90 dBu Noise Floor VCA CH2 OUT
–80 dB Channel Separation
90 dB SNR
5-BIT
Single-and Dual-Supply Operation CHANNEL
DAC

APPLICATIONS CH3 IN

Home Theater Receivers

Surround Sound Decoders VCA CH3 OUT

Circle Surround® and AC-3® Decoders

DSP Soundfield™ Processors 5-BIT
CHANNEL
HDTV and Surround TV Audio Systems DAC
Automotive Surround Sound Systems CH4 IN
Multiple Input Mixer Consoles and Amplifiers
VCA CH4 OUT

GENERAL DESCRIPTION
5-BIT
The SSM2160 allows digital control of volume of six audio CHANNEL
DAC
channels, with a master level control and individual channel
CH5 IN
controls. Low distortion VCAs (voltage controlled amplifiers) are
used in the signal path. By using controlled rate-of-change drive
VCA CH5 OUT
to the VCAs, the “clicking” associated with switched resistive
networks is eliminated in the master control. Each channel is
5-BIT
controlled by a dedicated 5-bit DAC providing 32 levels of gain. CHANNEL
A master 7-bit DAC feeds every control port giving 128 levels of DAC
CH6 IN
attenuation. Step sizes are nominally 1 dB and can be changed by
external resistors. Channel balance is maintained over the entire
VCA
master control range. Upon power-up, all outputs are automati- CH6 OUT

cally muted. A 3-wire or 4-wire serial data bus enables interfacing

with most popular microcontrollers. Windows® software and an 5-BIT
CHANNEL
evaluation board for controlling the SSM2160 are available. DAC
CH SET
STEP SIZE
The SSM2160 can be operated from single supplies of +10 V to 7-BIT ADJUST MSTR SET
+20 V or dual supplies from ± 5 V to ±10 V. An on-chip reference MASTER
DAC MSTR OUT
provides the correct analog common voltage for single-supply
applications. The SSM2160 comes in a SOIC package; see the CLK
SHIFT REGISTER
Ordering Guide for details. DATA AND
ADDRESS
LD DECODER SSM2160
WRITE

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com
registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
SSM2160–SPECIFICATIONS (VR ==10ⴞ6k⍀,V, Tunless
= 25ⴗC, A = 0 dB, f
otherwise noted.)
S
L
= 1 kHz, f A V AUDIO CLOCK = 250 kHz,

Parameter Symbol Conditions Min Typ Max Unit

AUDIO PERFORMANCE
Noise Floor NFL VIN = GND, BW= 20 kHz, AV = 0 dB1 –90 dBu
Total Harmonic Distortion + Noise THD+N Second and Third Harmonics Only,
VOUT = 0 dBu2
AV = 0 dB 0.01 0.035 %
Channel Separation Any Channel to Another 80 dB
Dynamic Range NFL to Clip Point 100 dB
ANALOG INPUT
Maximum Level VIN max VS = ± 10 V 1.8 V rms
Impedance ZIN Any Channel 10 kΩ
ANALOG OUTPUT
Maximum Level3 VS = ± 10 V, All Conditions of Master
Attenuation and Channel Gain 1.8 V rms
Impedance ZOUT 10 Ω
Offset Voltage 20 mV
Minimum Resistive Load RL min 10 kΩ
Maximum Capacitive Load CL max 50 pF
MASTER ATTENUATOR ERROR Measured from Best Fit of All Channels
from 0 dB and –127 dB (or Noise Floor)
AV = 0 dB Channel Gain = 0 dB ± 0.5 dB
AV = –20 dB Channel Gain = 0 dB ± 1.0 dB
AV = –40 dB Channel Gain = 0 dB ± 2.0 dB
AV = –60 dB Channel Gain = 0 dB ± 2.5 dB
CHANNEL MATCHING ± 1.0 dB
CHANNEL GAIN ERROR Master Attenuation = 0 dB
AV = 0 dB ± 0.5 dB
AV = 10 dB ± 1.0 dB
AV = 31 dB ± 2.0 dB
MUTE ATTENUATION VIN = 0 dBu –95 dB
VOLTAGE REFERENCE VREF
(V +) +(V – )
Accuracy Percent of ±5 %
2
Output Impedance 5 Ω
CONTROL LOGIC
Logic Thresholds
High (1) Re: DGND 2.0 V
Low (0) 0.8 V
Input Current ±1 µA
Clock Frequency 1 1000 kHz
Timing Characteristics See Timing Diagrams
POWER SUPPLIES
Voltage Range
SSM2160 VS Single Supply 10 20 V
SSM2160 V+, V– Dual Supply ±5 ± 10 V
Supply Current No Load 20 28 mA
NOTES
1
Master = 0 dB; Channel = 0 dB.
2
Input level adjusted accordingly. 0 dBu = 0.775 V rms.
3
For other than ± 10 V supplies, maximum is V S/4.
Specifications subject to change without notice.

–2– REV. A
 SSM2160
TIMING CHARACTERISTICS
Timing
Symbol Description Min Typ Max Unit
tCL Input Clock Pulsewidth, Low 200 ns
tCH Input Clock Pulsewidth, High 200 ns
tDS Data Setup Time 50 ns
tDH Data Hold Time 75 ns
tCW Positive CLK Edge to End of Write 100 ns
tWC Write to Clock Setup Time 50 ns
tLW End of Load Pulse to Next Write 50 ns
tWL End of Write to Start of Load 50 ns
tL Load Pulsewidth 250 ns
tW3 Load Pulsewidth (3-Wire Mode) 250 ns
NOTES
1. An idle HI (CLK-HI) or idle LO (CLK-LO) clock may be used. Data is latched on the negative edge.
2. For SPI™ or Microwire™ 3-wire bus operation, tie LD to WRITE and use WRITE pulse to drive both pins. (This generates an automatic internal load signal.)
3. If an idle HI clock is used, t CW and tWL are measured from the final negative transition to the idle state.
4. The first data byte selects an address (MSB HI), and subsequent MSB LO states set gain/attenuation levels. Refer to the Address/Data Decoding Truth Table.
5. Data must be sent MSB first.

0
CLK
1

1
DATA D7 D6 D5 D4 D3 D2 D1 D0
0

1
WRITE
0

1
LD
0

tCH tCL
1
CLK
0
tDS
tDH
1
DATA D7
0
MSB
tWC tCW
1
WRITE
0

1 tL
LD
0
tWL tLW

Figure 1. Timing Diagrams

REV. A –3–
SSM2160
ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATION
Supply Voltage 24-Lead SOIC
Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Single2 (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5 V V+ 1 24 CH SET

Operating Temperature Range . . . . . . . . . . . . . . . 0°C to 70°C AGND 2 23 MSTR OUT

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C VREF 3 22 MSTR SET

Junction Temperature Range . . . . . . . . . . . . . –65°C to +165°C CH1 OUT 4 21 CH2 OUT

Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C CH1 IN 5 20 CH2 IN

SSM2160
CH3 OUT 6 TOP VIEW 19 CH4 OUT
ESD Ratings (Not to Scale) 18
CH3 IN 7 CH4 IN
883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . 2.5 kV
CH5 OUT 8 17 CH6 OUT
CH5 IN 9 16 CH6 IN
PACKAGE THERMAL INFORMATION WRITE 10 15 DATA

Package Type ␪JA 3

␪JC Unit LD 11 14 CLK

V– 12 13 DGND
24-Lead SOIC 71 23 °C/W
NOTES
1
Absolute maximum ratings apply at 25°C, unless otherwise noted.
2
VS is the total supply span from V+ to V–.
3
␪JA is specified for the worst-case conditions for device soldered onto a circuit
board for SOIC packages.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option
SSM2160S 0°C to 70°C 24-Lead SOIC R-24
SSM2160S-REEL 0°C to 70°C 24-Lead SOIC R-24
EVAL-SSM2160EB Evaluation Board

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
SSM2160 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

–4– REV. A
 SSM2160
PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 V+ Positive Power Supply. Refer to the Application Information section for details on the power supply.
2 AGND Internal Ground Reference for the Audio Circuitry. When operating the SSM2160 from dual supplies,
AGND should be connected to ground. When operating from a single supply, AGND should be connected
to VREF, the internally generated voltage reference. AGND may also be connected to an external
reference. Refer to the Application Information section for more information on the power supply.
3 VREF VREF is the internally generated ground reference for the audio circuitry obtained from a buffered
divider between V+ and V–. In a dual-supply application with the AGND pin connected to ground,
VREF should be left floating. In a single-supply application, VREF should be connected to AGND. Refer
to the Application Information section for more information on the power supply.
4 CH1 OUT Audio Output from Channel 1
5 CH1 IN Audio Input to Channel 1
6 CH3 OUT Audio Output from Channel 3
7 CH3 IN Audio Input to Channel 3
8 CH5 OUT Audio Output from Channel 5
9 CH5 IN Audio Input to Channel 5
10 WRITE A logic low voltage enables the SSM2160 to receive information at the DATA input (Pin 15). A logic
high retains data at their previous settings (Figure 1). Serves as CHIP SELECT.
11 LD Loads the Information Retained by WRITE into the SSM2160 at logic low (Figure 1).
12 V– Negative Power Supply. Connect to ground in a single-supply application. Refer to the Application
Information section for details on the power supply.
13 DGND Digital Ground Reference. This pin should always be connected to ground. All digital inputs, including
WRITE, LD, CLK, and DATA are TTL input compatible; drive currents are returned to DGND.
14 CLK Clock Input. It is positive edge triggered (Figure 1).
15 DATA Channel and master control information flows MSB first into the DATA pin. Refer to the Address/Data
Decoding Truth Table, Figure 7, for information on how to control the VCAs.
16 CH6 IN Audio Input to Channel 6
17 CH6 OUT Audio Output from Channel 6
18 CH4 IN Audio Input to Channel 4
19 CH4 OUT Audio Output from Channel 4
20 CH2 IN Audio Input to Channel 2
21 CH2 OUT Audio Output from Channel 2
22 MSTR SET Connected to the inverting input of an I-V converting op amp. It is used to generate a master control
voltage from the master control DAC current output. A resistor connected from MSTR OUT to
MSTR SET reduces the step size of the master control. See the Master/Channel Step Sizes section for
more details. A 10 µF capacitor should be connected from MSTR OUT to MSTR SET to eliminate
the zipper noise in the master control.
23 MSTR OUT Connected to the output of the I-V converting op amp. See MSTR SET description.
24 CH SET The step size of the channel control can be increased by connecting a resistor from CH SET to V+.
No connection to CH SET is required if the default value of 1 dB per step is desired. Minimum of 10 Ω
external resistor. See the Master/Channel Step Sizes section for details.

REV. A –5–
SSM2160–Typical Performance Characteristics
10 1.0 0.5
TA = 25ⴗC TA = 25ⴗC
VS = 10V
VS = ⴞ6V DUAL-SUPPLY OPERATION
VIN = 0dBu VIN = SINEWAVE @ 1kHz
VS = 15V RL = 10k⍀, CL = 50pF
1.0 RL = 10k⍀
MASTER/CHANNEL = 0dB
CL = 50pF 0.1 0.1

THD+N – %
THD+N – %

THD+N – %
VS = 20V
0.1

VS = ⴞ12V
0.01 VS = ⴞ6V
0.01 TA = 25ⴗC
SINGLE-SUPPLY OPERATION
VIN = SINEWAVE @ 1kHz 0.01 VS = ⴞ5V
RL = 10k⍀, CL = 50pF
0.001 0.001 MASTER/CHANNEL = 0dB
0.005
–70 –60 –40 –20 0 10 20 0.01 0.1 1.0 10 0.05 0.1 1.0 10
GAIN – dB INPUT VOLTAGE – V rms INPUT VOLTAGE – V rms

TPC 1. THD vs. Gain TPC 2. THD+N % vs. Amplitude TPC 3. THD+N % vs. Amplitude

0.1 –40 –40

TA = 25ⴗC TA = 25ⴗC TA = 25ⴗC
DUAL-SUPPLY OPERATION –50 VS = ⴞ6V VS = ⴞ6V
–50
CHANNEL SEPARATION – dB

VIN = 300mV rms@1kHz VIN = 1V rms @ 1kHz

VIN = 1V rms @ 1kHz
RL = 10k⍀, CL = 50pF RL = 10k⍀, CL = 50pF
–60 VIN = GND (NONSELECTED CH) –60
MASTER/CHANNEL = 0dB
RL = 100k⍀, CL = 50pF
LPF: < 22kHz

OUTPUT – dB
–70 LPF: < 22kHz
THD+N – %

–70
VS = ⴞ12V
0.01 –80 –80
VS = ⴞ6V
–90 –90

–100 –100

–110 –110

0.001 –120 –120

20 100 1k 10k 30k 20 100 1k 10k 20k 20 100 1k 10k 30k
FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

TPC 4. THD+N % vs. Frequency TPC 5. Channel Separation TPC 6. Mute vs. Frequency
vs. Frequency

–60
TA = 25ⴗC
–65 VS = ⴞ6V
–70 VIN = GND

–75
NOISE – dBu

–80

–85

–90

–95

–100
–105
–110
–70 –60 –40 –30 –20 –10 0 10 20 30 40
GAIN – dB

TPC 7. Noise vs. Gain

–6– REV. A
 Typical Performance Characteristics–SSM2160
0 0 0
–10 TA = 25ⴗC TA = 25ⴗC
–10 TA = 25ⴗC –10
VS = ⴞ12V VS = ⴞ12V
–20 VS = ⴞ12V –20 –20
VIN = –31dBu @ 1Hz VIN = –31dBu @ 1kHz
–30 VIN = 0dBu @ 1kHz –30 –30
RL = 100k⍀ RL = 100k⍀
RL = 100k⍀ –40
–40 MASTER = 0dB –40 MASTER = 0dB

AMPLITUDE – dBu

AMPLITUDE – dBu
AMPLITUDE – dBu

MASTER = 20dB
–50 –50 CHANNEL = 0dB –50 CHANNEL = 31dB
CHANNEL = 0dB
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
–130 –130 –130
–140 –140 –140
0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20 22
FREQUENCY – kHz FREQUENCY – kHz FREQUENCY – kHz

TPC 8. THD vs. Frequency (FFT) TPC 9. THD vs. Frequency (FFT) TPC 10. THD vs. Frequency (FFT)

0.100 0 –20
TA = 25ⴗC TA = 25ⴗC
–10 VS = ⴞ12V TA = 25ⴗC
VS = ⴞ12V
–20 RL = 100k⍀ –30 VS = ⴞ6V ⴞ 10%
SMPTE 4:1
IM-FREQ 60Hz/7kHz –30 A MASTER = 0dB LPF = <22kHz
CHANNEL = +31dB –40 MASTER = 0dB
AMPLITUDE – dBu

RL = 100k⍀ –40
1MD (SMPTE) – %

0.010 B MASTER/CHANNEL = 0dB CHANNEL = 0dB PSR–

–50
–50

PSR – dB
–60
–70 –60
–80
A PSR+
–90 –70
0.001
–100
–80
–110
–120 –90
–130
B
0.0001 –140 –100
0.05 0.1 1.0 5.0 0 2 4 6 8 10 12 14 16 18 20 22 20 100 1k 10k 30k
INPUT AMPLITUDE – V rms FREQUENCY – kHz FREQUENCY – Hz

TPC 11. SMPTE IM vs. TPC 12. Noise Floor FFT TPC 13. PSR vs. Frequency
Amplitude V rms

25

24
23
SUPPLY CURRENT – mA

22
21
20

19
18
17

16
15
ⴞ4 ⴞ5 ⴞ6 ⴞ7 ⴞ8 ⴞ9 ⴞ10 ⴞ11 ⴞ12 ⴞ13
SUPPLY VOLTAGE – V

TPC 14. ISY vs. VS

REV. A –7–
SSM2160
APPLICATIONS INFORMATION Dual Power Supplies
General As shown in Figure 2, the AGND pin should be connected to
The SSM2160 is a 6-channel volume control intended for ground and VREF should be left floating. The digital ground pin,
multichannel audio applications. While dual-channel controls DGND, should always be connected to ground for either single-
sufficed for stereo applications, rapidly emerging home theater or dual-supply configurations. Pins 1 and 12 should each have a
surround sound and auto sound venues demand both 4-channel 10 µF capacitor connected to ground, with a 0.1 µF capacitor
and 6-channel high performance controls. Line level signals are fed placed as close as possible to the SSM2160 to help reduce the
to the six high impedance inputs. The system microcontroller effects of high frequency power supply noise. When a switching
sets the gain of the six channels via a 3-wire or 4-wire data bus. power supply is used, or if the power supply lines are noisy,
In a home theater receiver, the outputs may be fed to the power additional filtering of the power supply lines may be required.
amplifiers or buffered and connected to pre-out/amp-in ports on
the rear panel. Refer to Figure 5 for a typical signal chain using
the SSM2160. The master control serves the volume control 1
V+ V+
function, and the channel control serves the balance function.
+
The 6-channel capability allows complete control of the front left, 10␮F 0.1␮F SSM2160
front right, center, rear left, rear right, and sub-bass audio channels. 2
AGND
Power Supplies vs. Signal Levels
The SSM2160 can be operated from dual supplies from ± 5 V to
VREF
± 10 V and from single supplies from +10 V to +20 V. To keep
power dissipation to a minimum, use the minimum power supply
12
voltages that will support the maximum input and output signal V– V–

levels. The peak-to-peak output signal level must not exceed 1/4 10␮F
of the total power supply span, from V+ to V–. This restriction + 0.1␮F
13
DGND
applies for all conditions of input signal levels and gain/attenuation
settings. Table I shows supply voltages for several typical output
signal levels for the device. An on-chip buffered voltage divider
provides the correct analog common voltage for single-supply Figure 2. Dual-Supply Configuration
applications. Single Power Supply
When a single supply is used, it is necessary to connect AGND
Table I. Signal Levels vs. Power Supplies (Pin 2) to VREF (Pin 3), as shown in Figure 3. VREF supplies a
voltage midway between the V+ and V– pins from a buffered
Max Output, Max Output resistive divider. When supplying this reference to stages ahead
V rms (V p-p) (dBu) Single +VS(V) Dual ⴞVS(V) of the SSM2160 (to eliminate the need for input dc blocking
0.9 (2.5) +1.3 10 ±5 capacitors, for example), the use of an additional external
1.1 (3.0) +3.0 12 ±6 buffer, as shown in Figure 4, may be necessary to eliminate any
1.3 (3.7) +4.5 15 ± 7.5 noise pickup.
1.8 (5.0) +7.3 20 ± 10

1
V+ V+
+
10␮F 0.1␮F SSM2160
2
AGND

3
VREF
+
10␮F
0.1␮F
12
V–

13
DGND

Figure 3. Single-Supply Configuration

–8– REV. A
 SSM2160
Digital Control Range Plan
V+
1
V+ The SSM2160 may be modeled as six ganged potentiometers
+ followed by individual programmable gain channel amplifiers, as
10␮F 0.1␮F SSM2160
shown in Figure 6. In actuality, each channel’s signal level is set by
2 CHn IN
AGND a VCA that can give gain or attenuation, depending upon the control
voltage supplied. The input potentiometers have a maximum
REF
gain 0 dB (unity), a minimum gain of –127 dB, and change in
OUT
VREF 1 dB steps. The channel amplifiers each have minimum gain of
3
+ 0 dB and a maximum gain of 31 dB and also change in 1 dB steps.
10␮F 0.1␮F
12
The data settings for the attenuation of the master potentiometer
V–
and the channel amplifier are shown in Table II.
13
DGND INPUT
0dB
MASTER
Figure 4. Single-Supply Operation with VREF Buffer –127dB OUTPUT

Signal Chain Considerations

+31dB 0dB
The SSM2160 is capable of providing an extremely wide control
range, from –127 dB of attenuation (limited only by the noise CHANNEL

floor) to +31 dB of gain. When configuring the system, the

SSM2160 should be in the signal chain where input signals allow Figure 6. Potentiometer Representation of SSM2160
the minimum VCA gain to be used, thus ensuring the lowest (One Channel Only)
distortion operation. In consumer products, sources that supply
line level signals include FM/AM tuner, phono preamp, cassette Table II. Master and Channel Control
deck, CD, laser disk, VCR, LINE, AUX, and microphone preamp. Data
Figure 5 shows a typical application where the SSM2160 has been dB Hex Binary
placed between a surround sound decoder and the power
amplification stages. This allows the user to adjust both volume Master Min Atten 0 7F 1111111
and balance between six speakers through the use of the master Max Atten –127 00 0000000
and channel controls. Channel Max Gain +31 00 00000
POWER AMPS
Midgain +15 10 10000
FM/AM TUNER Min Gain 0 1F 11111
PHONO PREAMP
CASSETTE DECK SURROUND
COMPACT DISK MUX SOUND SSM2160 TO When using channel controls as balance controls, the center would
SPEAKERS
LASER DISK DECODER be with Channel = 10h (or 0Fh if desired). Increasing the gain
VCR
MICROPHONE to the maximum would occur at Channel = 00h. Reducing the
LINE LEVEL INPUTS – STEREO PAIRS VOLUME AND gain to minimum would occur at Channel = 1Fh.
BALANCE
CONTROLS

Figure 5. Typical Signal Chain Using the SSM2160

MSB LSB MSB LSB

ADDRESS MODE DATA MODE
SELECTION
ADDRESS DATA

7-BIT MASTER DAC 1 X X X X 0 0 0 0

5-BIT CHANNEL DAC 1 1 X X X X 0 0 1 0 1 X
5-BIT CHANNEL DAC 2 1 X X X X 0 1 0 0 1 X
5-BIT CHANNEL DAC 3 1 X X X X 0 1 1 0 1 X
5-BIT CHANNEL DAC 4 1 X X X X 1 0 0 0 1 X
5-BIT CHANNEL DAC 5 1 X X X X 1 0 1 0 1 X
5-BIT CHANNEL DAC 6 1 X X X X 1 1 0 0 1 X
NO DAC SELECTED 1 X X X X 1 1 1 0 1 X
X X X X X

X = DON'T CARE 0 = MUTE

SHADED AREA IS DATA 1 = UNMUTE

Figure 7. Interface Characteristics, DAC Address/Data Decoding Truth Table

REV. A –9–
SSM2160
Serial Data Input Format If unity overall gain is required from the SSM2160, there should
The standard format for data sent to SSM2160 is an address be no net gain between the master (loss) and channel (gain), with
byte followed by a data byte. This is depicted in the truth table, both at their lowest attenuation position. Minimum channel gain
Figure 7. Two 8-bit bytes are required for each master and each is recommended for minimum distortion.
of the six channel updates. The first byte sent contains the address
and is identified by the MSB being logic high. The second byte
contains the data and is identified by the MSB being logic low. RM

The seven LSBs of the first data byte set the attenuation level RM, RC, C C
EXTERNAL
from 0 dB to –127 dB for the master. The five LSBs of the byte
SUMMATION
set the channel gain levels from 0 dB to 31 dB. RESISTOR
R IN
MASTER
Serial Data Control Inputs DAC
SIGNAL
The SSM2160 provides a simple 3-wire or 4-wire serial inter- OUT
SSM2160 i
V+
face—see the timing diagram in Figure 1. Data is presented to IFS SET
the DATA pin and the serial clock to the CLK pin. Data may CHANNEL
be shifted in at rates up to 1 MHz (typically). DAC

The shift register, CLK, is enabled when the WRITE input is RC

low. The WRITE thus serves as a chip select input; however, the Figure 8. VCA Control Scheme
shift register contents are not transferred to the holding register
until the rising edge of LD. In most cases, WRITE and LD will Control Range and Channel Tracking
be tied together, forming a traditional 3-wire serial interface. Each channel VCA is controlled by its own DAC’s output, plus
the control signal from the master DAC. This is shown in Figure 8.
To enable a data transfer, the WRITE and LD inputs are driven Channel DACs are configured to increase the gain of the VCA in
logic low. The 8-bit serial data, formatted MSB first, is input on 1 dB steps from 0 dB to 31 dB. Thus, the midpoint (15, or 16 if
the DATA pin and clocked into the shift register on the falling preferred) should be chosen as the center setting of the electronic
edge of CLK. The data is latched on the rising edge of WRITE balance controls. Since the master DAC feeds all summation
and LD. nodes, the attenuation of all VCAs simultaneously changes from
0 dB to the noise floor.
Table III. Input/Output Levels vs. Attenuation/Gain
Maximum attenuation of all channels occurs when the master is
Input Gain/Loss Output set to –127 dB attenuation, and the channel is set to 0 dB gain.
dBu mV rms Master Channel Net dBu mV rms Minimum attenuation of all channels occurs when the master is
set at 0 dB, and the channel is set to 31 dB.
0 775 –31 31 0 0 775
–31 22 0 31 31 0 775 Once the channel-to-channel balance has been set, the master
–28 31 0 31 31 3 1100 may be changed without changing the balance. This is shown in
Figure 9.
Saturation Prevention
NET GAIN/ATTEN
Unlike a passive potentiometer, the SSM2160 can give up to 31 dB +31 +31 0 0 0 0 0
of gain, thereby creating a potential for saturating the VCAs, CHANNEL CHANNEL
+16 +16
resulting in an undesirable clipping or overload condition. Care- GAIN GAIN
0 0 11111
ful choice of input signal levels and digital gain parameters will 111111
eliminate the possibility. A few of the many acceptable gain and –16

attenuation settings that keep the signals within the prescribed –32
limits are shown in Table III. The input and output levels are –48 00000
+31
given in mV rms and dBu (0 dBu = 0.775 V rms). MASTER –64 CHANNEL
ATTENUATION +16 GAIN
Line one of the table: the master is not allowed to have less than –80 11111
0
–31 dB attenuation, and the channel is allowed +31 dB of gain. –96
Since the net gain is zero, there is no possibility of overload with –112
NOISE FLOOR
the expected maximum input signal. –128 0 0 0 0 0 0
Line two of the table shows that input signal limited to –31 dBu
will allow +31 dB of channel gain and 0 dB of master attenuation. Figure 9. Practical Control Range
With an input below –31 dBu, the output will never exceed Master/Channel Step Sizes
0 dBu, so no overloading is possible. The details of the DAC control of the channel VCAs is depicted
Line three of the table allows an input of –28 dBu, master in Figure 8. A 7-bit current output DAC and an op amp convert
attenuation of 0 dB, and 31 dB channel gain. The output is a the digitally commanded master control level to an analog voltage.
maximum of 3 dBu (1.1 V rms), which is acceptable for power A capacitor across the feedback resistor limits the rate of change
supplies of ± 6 V or more. So long as V p-p < VSUPPLY/4, there at the output to prevent clicking. A 5-bit DAC converts the digi-
will be no overloading (see Table I). tally commanded channel control level to a voltage via a resistor R.
These two control signals sum in resistor R and are fed to the
channel VCA. Although we present the attenuation and gain as
two separate items, in fact, the VCA can be operated smoothly

–10– REV. A
 SSM2160
from a gain condition to an attenuation. The master and channel could be some variation from lot to lot, so applications requiring
step sizes default to 1 dB in the absence of external components. precise step size should include a fixed resistor plus a trimmer
The step sizes can be changed by the addition of external resistors potentiometer to span the calculated value ± 25%. In this example,
if finer resolution is desired. RC is not needed since the default channel step size is already 1 dB.
Control Range vs. Step Size CH SET is left floating. With this step size, the dynamic range
Before adjusting step sizes from the standard 1 dB, consider the of the master control is
effect on control range. The master control and the channel DNR = 0.5 × 127 dB = 63.5 dB
control provide 1 dB step sizes, which may be modified by the
addition of external resistors. As the total number of steps is In this configuration, the maximum master volume is 0 dB,
unchanged, reduction of the step size results in a smaller control while the minimum volume is –63.5 dB. Since the channel
range. The range of the control is volume can still provide 0 dB to 31 dB of gain, the total system
RANGE = Step Size (dB ) × ( Number of Levels Used )
gain can vary between –63.5 dB and +32 dB. Note that a 0 dB
command setting to the master control always results in unity
Since the master volume control operates from a 7-bit word, its gain, regardless of the step size.
DAC has 128 levels (including 0). The channel volume control Channel Step Size
DAC is a 5-bit input, so there are 32 levels for volume control The channel DACs’ full-scale current is set by an internal resis-
(including 0). As can be seen in Figure 9, the practical control tor to V+. By shunting this resistor, the full-scale current, and
range is set by the noise floor. It can be advantageous to reduce therefore the step size, will increase. No provisions are available
the master step size to give finer steps from zero attenuation for reducing the channel step size. To increase the channel step
down to the noise floor. size, place a resistor, RC, from CH SET to V+. Note that a 0 dB
Reducing Master Step Size setting for a channel will always give unity gain, regardless of
To reduce the master step size, place resistor RM between how large or small the step size is. This is true for both the
MSTR SET and MSTR OUT. The master step size of the master and channel volume controls.
master volume control will then become 1.5

1700 X M
RM =
1– X M 1.4

where XM is the desired master control step size in decibels. See

CHANNEL STEP SIZE

Figure 10 for practical values of RM. Note that the step size for 1.3
the master control can only be adjusted to less than 1 dB. No
resistor is required for the default value of 1 dB per step. For
1.2
larger step sizes, use digital control. Noninteger dB step sizes can
be obtained by using digital control and a reduced step size.
1.1
1.0

1.0
0.8 101 102 103
MASTER STEP SIZE – dB

RC

0.6
Figure 11. Channel Step Size vs. RC
Example: Modifying Channel Step Size
A channel step size of 1.3 dB is desired. From Figure 11 we see
0.4
that a 40 Ω resistor (approximately) connected from CH SET to
V+ is required. As this varies from lot to lot, the exact value
0.2 should be determined empirically, or a fixed resistor plus trimmer
potentiometer should be used. Take care not to short Pin 24 to
Pin 1 as damage will result.
0
102 103 104 105
RM Muting
The SSM2160 offers master and channel muting. On power-up,
Figure 10. Master Step Size vs. RM the master mute is activated, thus preventing any transients
Example: Modifying Master Step Size to 0.5 dB from entering the signal path and possibly overloading amplifi-
A master step size of 0.5 dB is desired for the master control, ers down the signal path. Mute is typically better than –95 dB
while a 1 dB step size is adequate for the channel control. Using relative to a 0 dBu input. Due to design limitations, the indi-
the preceding equation or Figure 10, RM is found to be 1700 Ω vidual channel muting results in increased signal distortion in
and is connected between MSTR SET and MSTR OUT. There the unmuted channels. Users should determine if this condition
is acceptable in the particular application.

REV. A –11–
SSM2160
DC Blocking and Frequency Response proper bypassing. In addition, limiting the high state logic signal
All internal signal handling uses direct coupled circuitry. Although levels to 3.5 V will minimize noise coupling.
the input and output dc offsets are small, dc blocking is required Load Considerations
when the signal ground references are different. This will be the The output of each SSM2160 channel must be loaded with a mini-
case if the source is from an op amp that uses dual power supplies mum of 10 kΩ. Connecting a load of less than 10 kΩ will result
(i.e., ± 6 V), and the SSM2160 uses a single supply. If the signal in increased distortion and may cause excessive internal heating
source has the capability of operating with an externally supplied with possible damage to the device. Capacitive loading should be
signal, connect the VREF (Pin 3) to the source’s external ground kept to less than 50 pF. Excessive capacitive loading may increase
input either directly or through a buffer as shown in Figure 4. the distortion level and may cause instability in the output ampli-
The same consideration is applied to the load. If the load is fiers. If your application requires driving a lower impedance or
returned to AGND, no capacitor is required. When the SSM2160 more capacitive load, use a buffer as shown in Figure 12.
is operated from a single supply, there will be a dc output level
of +VS/2 at the output. This will require dc blocking capacitors 1/2 SSM2135
CH1 OUT
if driving a load referred to GND. CH1 OUT
When dc blocking capacitors are used at the inputs and outputs,
SSM2160
they form a high-pass filter with the input and load resistance,
both of which are typically 10 kΩ. To calculate the lower –3 dB
CH6 OUT 1/2 SSM2135
frequency of the high-pass filter formed by the coupling capacitor CH6 OUT
and the input resistance, use either of the following formulas

fC = 1 (2πRC )
Figure 12. Output Buffers to Drive Capacitive Loads
or
C = 1 (2πRfC ) Windows Software
Windows software is available to customers from Analog Devices
where
to interface the serial port of a PC (running Windows 3.1 or
R is the typically 10 kΩ input resistance of the SSM2160 or the
higher) with the SSM2160. Contact your sales representative for
load resistance. C is the value of the blocking capacitor when fC
details on obtaining the software. For details, see the Evaluation
is known.
Board section.
If a cutoff frequency of 20 Hz were desired, solving for C gives
0.8 µF for the input or output capacitor. A higher load imped- RC*
ance will allow smaller output capacitors to give the same 20 Hz
cutoff. Note that the overall low-pass filter will be the cascade of
V+ 1
the two, so the response will be –6 dB at 20 Hz. A practical and +
10µF 0.1␮F
economical choice would be 1 µF/15 V electrolytics. 2 23 +
RM*
10␮F
3 22
Signal/Noise Considerations and Channel Center Gain
The SSM2160 should be placed in the signal flow where levels OUT ** 4 21 OUT
CH 1 CH 2
are high enough to result in low distortion and good SNR but IN 5 20 IN
SSM2160
not so high to require unusually high power supplies. In a typical 6
OUT 19 OUT
application, input and output signal levels will be in the 300 mV CH 3 CH 4
± 200 mV rms range. This level is typically available from internal IN 7 18 IN

and external sources. As previously mentioned, the 31 dB of OUT 8 17 OUT

CH 5 CH 6
gain available in the VCA is usually used for balancing the various IN 9 16 IN
channels and is usually set to 15 dB or 16 dB in its center posi-
WRITE 10 15 DATA
tion. Due to the nature of VCA performance versus gain, the
minimum gain that will allow balancing the channels should be LD 11 14 CLK

used. If no balance function is required, the channel gain should V– 12 13

be set to 0 dB. Use the lowest value of centered gain when less 10␮F+ 0.1␮F
than the full balance range is needed. For example, if only ± 6 dB
channel gain variations were needed, the center could be set at **OPTIONAL SEE “CHANNEL STEP SIZE”
6 dB, giving 6 dB ± 6 dB, rather than at 15 dB ± 6 dB. This **TYPICAL 1␮F–10␮F: SEE “DC BLOCKING AND FREQUENCY RESPONSE”

would result in improved S/N ratio and less distortion. Figure 13. Typical Application Circuit (Dual Supply)
Digital Interface
Digital logic signals have fast rising and falling edges that can
easily be coupled into the signal and ground paths if care is not
taken with PC board trace routing, ground management, and

–12– REV. A
 SSM2160
Controlling Stereo Headphones Level and Balance +5V
C2 100pF
Figure 14 shows how the SSM2160 can be configured to drive a 1
V+ + R2 6k⍀
stereo headphone output amplifier. Note that the minimum 2 R1*
AGND 500⍀
load specification precludes driving headphones directly. This +5V
example assumes that audio left and right signals are being fed 15␮F*
LEFT
into Channels 1 and 2, respectively. Additional amplifiers could CH1 OUT
4 150⍀ HEADPHONE
SSM2135-A – 5V 50k⍀ 600⍀
be connected to the outputs to provide additional channels. The
SSM2160
master control will set the loudness, and the channel controls will 21 SSM2135-B +5V
CH2 OUT 150⍀ 15␮F*
set the balance. The headphone amplifiers may be connected to RIGHT
HEADPHONE
the same power supplies as the SSM2160. The stereo audio signals 600⍀
–5V – 5V 50k⍀
are directly coupled to the noninverting input of both op amps.
12 R2 6k⍀
Depending upon the headphones and the signal levels, the optional V–
+ R1*
500⍀
R1 may be selected to provide additional gain, which is deter- DGND
13
C2 100pF
mined by
 R2
AV = 1+   *SEE TEXT FOR ALTERNATE VALUES
 R1
Figure 14. Headphone Output Amplifier Configuration
As an example, suppose a high impedance headphone (600 Ω)
required a minimum of 25 mW to produce the desired loudness. EVALUATION BOARD FOR THE SSM2160
Further, suppose the system design made available an output The following information is to be used with the SSM2160
level from the SSM2160 of 300 mV. If the output were buffered evaluation board, which simplifies connecting the part into
without gain and applied directly to the headphone, the power existing systems. Audio signals are fed in and out via standard
would be RCA-type audio connectors. A stereo headphone driver socket is
V2 provided for the convenience of listening to Channels 1 and 2.
P = Microsoft Windows software is available for controlling the serial
R
data bus of the SSM2160 via the parallel port driver (LPT) of a
(0.3)
2
PC. The software may be downloaded from the Analog Devices
P = = 0.15 mW
600 website at www.analog.com. The evaluation board comes com-
This is obviously too little power, so we solve the equation for plete with the necessary parallel port cable and telephone type
the voltage required to produce the desired power of 25 mW plug that mates with the evaluation board.
Power Supplies
V = PR The evaluation board should be connected to ± 6 V supplies for
V = 0.025 × 600 = 3.9 V rms initial evaluation. If other supply voltages are planned, they can
be subsequently changed. The power configuration on the evalu-
The gain of the amplifiers must then be ation board is per Figure 2.
3.89 Signal Inputs and Outputs
AV = = 13 Input load impedances are approximately 10 kΩ, so the load on
0.3
the sources is relatively light. DC blocking capacitors are pro-
R2 vided on the evaluation board. The load impedance connected to
AV = 1 +
R1 the outputs must be no less than 10 kΩ and no more than 50 pF
R2 shunt capacitance. This enables driving short lengths of shielded
= 12 or twisted wire cable. If heavier loads must be driven, use an
R1
external buffer as shown in Figure 13. Note that 50 Ω isolation
R 2 6000 resistors are placed in series with each SSM2160 output and may
R1 = = = 500 Ω
12 12 be jumpered if desired.
If lower impedance headphones were used, say 30 Ω, the voltage Digital Interface
required would be 0.9 V rms and a gain of 3 would suffice; thus, The interconnecting cable provided has a DB25 male connector
R1 = 2.5 kΩ and R2 = 5 kΩ. for the parallel port of the PC and an RJ14 plug that connects to
The 100 pF capacitor, C2, in parallel with R2, creates a low-pass the evaluation board. This cable is all that is required for the
filter with a cutoff above the audible range, reducing the gain to computer interface.
high frequency noise. A small resistor within the feedback loop Software Installation
protects the output stage in the event of a short circuit at the If installing the software from a diskette and using Windows 3.1
headphone output but does not measurably reduce the signal or later, select the RUN command from the FILE menu of the
swing or loop gain. The dc blocking capacitor at the output Program Manager. In the command line, type a:\setup and press
establishes a high-pass filter with a –3 dB corner frequency Enter. If you downloaded the software to your hard disk from
determined by the value of C1 and the headphone impedance. the Analog Devices website to, for example, C:\SSM2160, on
With 600 Ω headphones, an output capacitor of 15 µF sets this the command line type C:\SSM2160\SETUP and press Enter.
corner at 20 Hz. Similarly, a 30 Ω headphone will require 250 µF. The software will be automatically installed and a SSM2160
CAUTION: As with all headphone applications, listening to start-up icon will be displayed. Double-click the icon to start the
loud sounds can cause permanent hearing loss. application. Under the menu item Port, select the parallel port

REV. A –13–
SSM2160
that is assigned to the connector used on your PC if different Channel Mute
from the default LPT1. Same function as Master Mute but on a channel basis. Due to
Windows Control Panel the design limitations, muting an individual channel results in
The control panel contains all the functions required to control an increased distortion level of the unmuted channels. Users must
the SSM2160, and each feature is described below. A mouse is determine if this condition is acceptable in their application.
needed to operate the various controls. It is possible to overload Channel Balance
the VCA by incorrect input levels and master and control settings. The channel balance fader adjusts all channels over their range
If you have not read the sections of the data sheet regarding without affecting the master volume setting. Relative channel
control planning, do so now. While no damage will occur to differences will be maintained until the top or the bottom of
the SSM2160, the results will be unpredictable. the range is reached. The master volume fader does the same
Master Volume function as this fader, which was made available for evaluation
The master volume fader controls the 7-bit word that deter- convenience.
mines the attenuation level. There are 128 levels (27) that range Master and Channel Fades
from 0 dB attenuation to –127 dB attenuation. To change the Both master and channel fades can be achieved by pressing the
level, simply click the up or down arrows or click in the space MEM 1 button when levels are at a desired starting position and
directly above or below the fader knob, or drag the knob up or the MEM 2 button at the desired ending position. Fade controls
down to its desired position. (Drag refers to placing the screen individual channels, and Master Fade controls the master volume.
cursor arrowhead on the control, pressing and holding the left Fade Time sets timing from 0.1 (fastest) to 9.9 (slowest). Press
mouse button while moving the arrow to the desired position.) Fade to commence operation. If Fade is pressed again, a fade
Master Mute back to the starting point will occur. The Jump button causes a
Below the master volume fader is the Master Mute button. Click direct jump to the opposite memory position.
this button to mute all channels. Clicking it again will unmute all Halt
channels. The application defaults to Mute when started. Mute Halt is a software interrupt in case of a problem or to stop a
reduces outputs to approximately –95 dB below inputs up to 0 dBu. long fade time.
Channel Volume Update
Each of the channel fader controls can be set to one of 32 levels Data currently on display is resent to the SSM2160. This is
of gain, from 0 dB to 31 dB. See the previous section on Master useful when parts are being substituted in the evaluation board,
Volume for details. or when the interface cable is changed.

–14– REV. A
 SSM2160
OUTLINE DIMENSIONS

24-Lead Standard Small Outline Package [SOIC]

(R-24)
Dimensions shown in millimeters and (inches)

15.60 (0.6142)
15.20 (0.5984)

24 13
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
1 12
10.00 (0.3937)

2.65 (0.1043) 0.75 (0.0295)

2.35 (0.0925) ⴛ 45ⴗ
0.25 (0.0098)
0.30 (0.0118)
0.10 (0.0039)
8ⴗ
1.27 (0.0500) 0.51 (0.020) SEATING 0ⴗ 1.27 (0.0500)
COPLANARITY PLANE 0.32 (0.0126)
BSC 0.33 (0.013)
0.10 0.23 (0.0091) 0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-013AD

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Revision History
Location Page
2/03—Data Sheet changed from REV. 0 to REV. A.
Removed SSM2161 model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to PACKAGE THERMAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Change to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to Power Supplies vs. Signal Levels section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Changes to Update section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

REV. A –15–
–16–
PRINTED IN U.S.A. C03366–0–2/03(A)
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