EEE441

Digital Logic Design II

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Grading :
2 Midterm exams, Lab, Final Exam
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Schedule

Synchronous Sequential Logic

• Storage Elements: Latches, Storage Elements:
Flip‐Flops
• Analysis of Clocked Sequential Circuits , State,
Design Procedure
• Registers and Counters:Ripple
Counters,Synchronous Counters
Memory and Programmable Logic
• Random‐Access Memory , Memory Decoding,
Error Detection and Correction, Read‐Only
Memory,Programmable Logic Array,
Programmable Array Logic
Design at the Register Tr a n s f e r L e v e l
• Algorithmic State Machines (ASMs) , Design
Example (ASMD Chart) Sequential Binary
Multiplier , Control Logic
• Design with Multiplexers
 Presentation Outline

❖ Introduction to Sequential Circuits

❖ Synchronous versus Asynchronous

❖ Latches

❖ Flip-Flops

❖ Characteristic Tables and Equations

 Combinational versus Sequential
❖ Two classes of digital circuits
 Combinational Circuits
 Sequential Circuits

❖ Combinational Circuit
 Outputs = F(Inputs)
Combinational
 Function of Inputs only Inputs Outputs
Circuit
 NO internal memory

❖ Sequential Circuit
 Outputs is a function of Inputs and internal Memory
 There is an internal memory that stores the state of the circuit
 Time is very important: memory changes with time
 Introduction to Sequential Circuits
A Sequential circuit consists of:

1. Memory elements: Inputs Outputs

Combinational
 Latches or Flip-Flops Logic
Present Next
 Store the Present State
State Memory State
2. Combinational Logic Elements

 Computes the Outputs of the circuit

Outputs depend on Inputs and Current State

 Computes the Next State of the circuit

Next State also depends on the Inputs and the Present State
 Examples of sequential devices
• Many real-life devices are sequential in nature:
– Combination locks open if you enter numbers in the right order.
– Elevators move up or down and open or close depending on the buttons
that are pressed on different floors and in the elevator itself.
– Traffic lights may switch from red to green
• Most importantly for us, computers are sequential! For example, key presses
and mouse clicks mean different things depending on which program is running
and the state of that program.

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 Two Types of Sequential Circuits
1. Synchronous Sequential Circuit
 Uses a clock signal as an additional input

 Changes in the memory elements are controlled by the clock

 Changes happen at discrete instances of time

2. Asynchronous Sequential Circuit

 No clock signal

 Changes in the memory elements can happen at any instance of time

❖ Our focus will be on Synchronous Sequential Circuits

 Easier to design and analyze than asynchronous sequential circuits
Sequential Circuits

Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

Synchronous
Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

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 Synchronous Sequential Circuits
Inputs Outputs
Combinational
Logic
Present Next
State Memory State
Elements

Clock
❖ Synchronous sequential circuits use a clock signal
❖ The clock signal is an input to the memory elements
❖ The clock determines when the memory should be updated
❖ The present state = output value of memory (stored)
❖ The next state = input value to memory (not stored yet)
 The Clock
Positive Negative
Clock cycle Clock cycle Pulse Pulse

Time

❖ Clock is a periodic signal = Train of pulses (1's and 0's)

❖ The same clock cycle repeats indefinitely over time

❖ Positive Pulse: when the level of the clock is 1

❖ Negative Pulse: when the level of the clock is 0

❖ Rising Edge: when the clock goes from 0 to 1

❖ Falling Edge: when the clock goes from 1 down to 0

 Clock Cycle versus Clock Frequency
Clock cycle Clock cycle Clock cycle

Time

❖ Clock cycle (or period) is a time duration

 Measured in seconds, milli-, micro-, nano-, or pico-seconds
 1 ms = 10-3 sec, 1 µs = 10-6 sec, 1 ns = 10-9 sec, 1 ps = 10-12 sec

❖ Clock frequency = number of cycles per second (Hertz)

 1 Hz = 1 cycle/sec, 1 KHz = 103 Hz, 1 MHz = 106 Hz, 1 GHz = 109 Hz

❖ Clock frequency = 1 / Clock Cycle

 Example: Given the clock cycle = 0.5 ns = 0.5 ×10-9 sec
 Then, the clock frequency = 1/(0.5×10-9) = 2×109 Hz = 2 GHz
 Memory Elements
❖ Memory can store and maintain binary state (0's or 1's)
 Until directed by an input signal to change state

❖ Main difference between memory elements

 Number of inputs they have

 How the inputs affect the binary state

❖ Two main types:

 Latches are level-sensitive (the level of the clock)

 Flip-Flops are edge-sensitive (sensitive to the edge of the clock)

❖ Flip-Flips are used in synchronous sequential circuits

❖ Flip-Flops are built with latches
 Next . . .

❖ Introduction to Sequential Circuits

❖ Synchronous versus Asynchronous

❖ Latches

❖ Flip-Flops

❖ Characteristic Tables and Equations

 What exactly is memory?
• A memory should have at least three properties.

1. It should be able to hold a value.

2. You should be able to read the value that was saved.
3. You should be able to change the value that’s saved.

• We’ll start with the simplest case, a one-bit memory.

1. It should be able to hold a single bit, 0 or 1.

2. You should be able to read the bit that was saved.
3. You should be able to change the value. Since there’s only a single bit,
there are only two choices:
– Set the bit to 1
– Reset, or clear, the bit to 0.

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 The basic idea of storage
• How can a circuit “remember” anything, when it’s just a bunch of gates that
produce outputs according to the inputs?
• The basic idea is to make a loop, so the circuit outputs are also inputs.
• Here is one initial attempt, shown with two equivalent layouts:

• Does this satisfy the properties of memory?

– These circuits “remember” Q, because its value never changes. (Similarly,
Q’ never changes either.)
– We can also “read” Q, by attaching a probe or another circuit.
– But we can’t change Q! There are no external inputs here, so we can’t
control whether Q=1 or Q=0.

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 A really confusing circuit
• Let’s use NOR gates instead of inverters. The SR latch below has two inputs S
and R, which will let us control the outputs Q and Q’.

• Here Q and Q’ feed back into the circuit. They’re not only outputs, they’re
also inputs!
• To figure out how Q and Q’ change, we have to look at not only the inputs S
and R, but also the current values of Q and Q’:

Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’

• Let’s see how different input values for S and R affect this thing.

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 Storing a value: SR = 00
• What if S = 0 and R = 0?
• The equations on the right reduce to:

Qnext = (0 + Q’current)’ = Qcurrent

Q’next = (0 + Qcurrent)’ = Q’current

• So when SR = 00, then Qnext = Qcurrent.

Whatever value Q has, it keeps.
Qnext = (R + Q’current)’
• This is exactly what we need to store values in Q’next = (S + Qcurrent)’
the latch.

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 Setting the latch: SR = 10
• What if S = 1 and R = 0?
• Since S = 1, Q’next is 0, regardless of Qcurrent:

Q’next = (1 + Qcurrent)’ = 0

• Then, this new value of Q’ goes into the top

NOR gate, along with R = 0.

Qnext = (0 + 0)’ = 1 Qnext = (R + Q’current)’

Q’next = (S + Qcurrent)’
• So when SR = 10, then Q’next = 0 and Qnext = 1.
• This is how you set the latch to 1. The S input
stands for “set.”
• Notice that it can take up to two steps (two
gate delays) from the time S becomes 1 to the
time Qnext becomes 1.
• But once Qnext becomes 1, the outputs will stop
changing. This is a stable state.

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 Latch delays
• Timing diagrams are especially useful in
understanding how sequential circuits work.
• Here is a diagram which shows an example of
how our latch outputs change with inputs SR=10.

0. Suppose that initially, Q = 0 and Q’ = 1.

Qnext = (R + Q’current)’
1. Since S=1, Q’ will change from 1 to 0
Q’next = (S + Qcurrent)’
after one NOR-gate delay (marked by
vertical lines in the diagram for clarity).
2. This change in Q’, along with R=0, causes 0 1 2 3 4
Q to become 1 after another gate delay.
S
3. The latch then stabilizes until S or R
change again. R

Q’

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 Resetting the latch: SR = 01
• What if S = 0 and R = 1?
• Since R = 1, Qnext is 0, regardless of Qcurrent:

Qnext = (1 + Q’current)’ = 0

• Then, this new value of Q goes into the bottom

NOR gate, where S = 0.

Q’next = (0 + 0)’ = 1 Qnext = (R + Q’current)’

Q’next = (S + Qcurrent)’
• So when SR = 01, then Qnext = 0 and Q’next = 1.
• This is how you reset, or clear, the latch to 0.
The R input stands for “reset.”
• Again, it can take two gate delays before a
change in R propagates to the output Q’next.

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 SR latches are memories!
• This little table shows that our latch S R Q
provides everything we need in a 0 0 No change
memory: we can set it, reset it, and 0 1 0 (reset)
remember the current value. 1 0 1 (set)

• The output Q represents the data

stored in the latch. It is sometimes
called the state of the latch.

• We can expand the table above into a Inputs Current Next

state table, which explicitly shows that S R Q Q’ Q Q’
the next values of Q and Q’ depend on 0 0 0 1 0 1
their current values, as well as on the 0 0 1 0 1 0
inputs S and R.
0 1 0 1 0 1
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 0 1 0

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 SR latches are sequential!
• Notice that for inputs SR = 00, the S R Q
next value of Q could be either 0 or 1, 0 0 No change
depending on the current value of Q.
0 1 0 (reset)
• So the same inputs can yield different 1 0 1 (set)
outputs, depending on whether the
latch was previously set or reset.
• This is very different from the
combinational circuits that we’ve seen
so far, where the same inputs always
yield the same outputs.
Inputs Current Next
S R Q Q’ Q Q’
0 0 0 1 0 1
0 0 1 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 0 1 0

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 What about SR = 11?
• Both Qnext and Q’next will become 0.
• This contradicts the assumption that Q and Qnext = (R + Q’current)’
Q’ are always complements. Q’next = (S + Qcurrent)’
• Another problem is what happens if we then
make S = 0 and R = 0 together. 0 0
Qnext = (0 + 0)’ = 1
Q’next = (0 + 0)’ = 1
0 0
• But these new values go back into the NOR
gates, and in the next step we get:

Qnext = (0 + 1)’ = 0
Q’next = (0 + 1)’ = 0
0 1
• The circuit enters an infinite loop, where Q
and Q’ cycle between 0 and 1 forever.
• This is actually the worst case, but the
1
moral is don’t ever set SR=11! 0

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 S’R’ latch
• There are several varieties of latches.
• You can use NAND instead of NOR gates to get a S’R’ latch.

S’ R’ Q
1 1 No change
1 0 0 (reset)
0 1 1 (set)
0 0 Avoid!

• This is just like an SR latch, but with inverted inputs, as you can see from the
table.
• You can derive this table by writing equations for the outputs in terms of the
inputs and the current state, just as we did for the SR latch.

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 An SR latch with a control input
• Here is an SR latch with a control input C.

C S R S’ R’ Q
0 x x 1 1 No change
1 0 0 1 1 No change
1 0 1 1 0 0 (reset)
1 1 0 0 1 1 (set)
1 1 1 0 0 Avoid!

• Notice the hierarchical design!

– The dotted blue box is the S’R’ latch from the previous slide.
– The additional NAND gates are simply used to generate the correct inputs
for the S’R’ latch.
• The control input acts just like an enable.

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 Summary S-R Latch

• SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0

R 0 0
Q

S Q
0 1

Initial Value

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 Summary S-R Latch

• SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R 0 1
Q

S Q
0 0

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 Summary S-R Latch

• SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 0
Q

S Q
0 1

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 Summary S-R Latch

• SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R 1 1
Q
0 1 1 0 1 Q=0

S Q
0 0

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 Summary S-R Latch

• SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 0
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0 Q=1

S Q
1 1

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 Summary S-R Latch

• SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 0
Q=0
1 0 1 1 0 1
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

S Q
1 0

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 Summary S-R Latch

• SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1
Q=0
0 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10

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 Summary S-R Latch

• SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R 1
Q=0
10 0 1 1 0 1
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0

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 Summary S-R Latch

• SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S R Q
Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
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 Summary S-R Latch

• SR Latch
S R Q
R Q Q0 No change
0 0
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S’ R’ Q
Q Invalid
0 0 Q=Q’=1
0 1 1 Set
Q 1 0 0 Reset
R Q0 No change
1 1
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 Summary S-R Latch

• SR Latch with Control Input

R R S S
Q Q
C C
S Q R Q
S R

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid 37
 SR Latch Operation
Set Operation Store Operation

R (Reset) 0 1 R (Reset) 0 1
Q Q

0 Q 0 Q
S (Set) 1 S (Set) 0

Reset Operation Store Operation

R (Reset) 1 0 R (Reset) 0 0
Q Q

1 Q 1 Q
S (Set) 0 S (Set) 0
 SR Latch Invalid Operation
Invalid Operation Race Condition

R (Reset) 1 0 R (Reset) 1→0 0→1

Q Q

0 Q Q
S (Set) 1 S (Set) 1→0
0→1

S = R = 1 should never be used Unknown State

If S and R change from 1 → 0 R (Reset) 0 0 or 1

Q
simultaneously then race
condition (oscillation) occurs
Final Q and Q are unknown S (Set) 0 Q
1 or 0
 Timing Diagram of an SR Latch

Set No change Reset No change Set Undefined Reset No change Set

S 1 0 0 0 1 1 0 0 0 1

R 0 0 1 0 0 1 0 1 0 0

Q 1 1 0 0 1 0 0 0 1

Q 0 0 1 1 0 0 1 1 0
Time
 Gated SR Latch (with Nor)
with Clock Enable
R (Reset) CR
Q

C (Clock)

CS Q
S (Set)

❖ An additional Clock (enable) input signal C is used

❖ Clock controls when the state of the latch can be changed
❖ When C=0, the S and R inputs have no effect on the latch
The latch will remain in the same state, regardless of S and R
❖ When C=1, then normal SR latch operation
Gated SR Latch(with Nand) with Clock Enable
S

❖ An additional Clock (enable) input signal C is used

❖ Clock controls when the state of the latch can be changed
❖ When C=0, the latch remains in the same state
❖ When C=1, then normal latch operation
The NAND gates invert the S and R inputs when C=1
 D-Latch with Clock Enable
S

❖ One data input 𝐷

D S
❖ 𝑆 = 𝐷 and 𝑅 = 𝐷 Q

❖ No undefined state
❖ Inverter can be removed Q

❖ When 𝐶 = 1, 𝑅 = 𝑆ҧ = 𝐷
ഥ C R
 Timing of a D-Latch with Clock Enable
D S
Q

D-Latch with
Clock Input
Q
C R

Q
Time
 Graphic Symbols for Latches

𝑆 𝑄 𝑆ҧ 𝑄 𝐷 𝑄
𝑆𝑅 𝑆𝑅 𝐷
𝐶 𝐶
𝐿𝑎𝑡𝑐ℎ 𝐿𝑎𝑡𝑐ℎ 𝐿𝑎𝑡𝑐ℎ
𝑅 𝑄 𝑅ത 𝑄 𝐶 𝑄

❖ A bubble appears at the complemented output 𝑄

Indicates that 𝑄 is the complement of 𝑄

❖ A bubble also appears at the inputs of an 𝑆 𝑅 latch

Indicates that logic-0 is used (not logic-1) to set (or reset) the
latch (as in the NAND latch implementation)
 Problem with Latches
❖ A latch is level-sensitive (sensitive to the level of the clock)

❖ As long as the clock signal is high …

Any change in the value of input 𝐷 appears in the output 𝑄

❖ Output 𝑄 keeps changing its value during a clock cycle

❖ Final value of output 𝑄 is uncertain

Due to this uncertainty,

latches are NOT used 𝐷 𝑄 𝑄
as memory elements in 𝐿𝑎𝑡𝑐ℎ
synchronous circuits 𝐶𝑙𝑘
𝐶 𝑄 𝑄
 Next . . .

❖ Introduction to Sequential Circuits

❖ Synchronous versus Asynchronous

❖ Latches

❖ Flip-Flops

❖ Characteristic Tables and Equations

 Flip-Flops
❖ A Flip-Flop is a better memory element for synchronous circuits

❖ Solves the problem of latches in synchronous sequential circuits

❖ A latch is sensitive to the level of the clock

❖ However, a flip-flop is sensitive to the edge of the clock

❖ A flip-flop is called an edge-triggered memory element

❖ It changes it output value at the edge of the clock

High Low Rising Falling Rising Falling

Level Level edge edge edge edge

Time
 Edge-Triggered D Flip-Flop
❖ Built using two latches in a master-slave configuration
❖ A master latch (D-type) receives external inputs
❖ A slave latch (SR-type) receives inputs from the master latch
❖ Only one latch is enabled at any given time
When Clk=0, the master is enabled and the D input is latched (slave disabled)
When Clk=1, the slave is enabled to generate the outputs (master is disabled)

𝑄𝑚
Outputs
Master Slave
𝑄𝑚 change when
Clk
Clk changes
from 0 to 1
 Negative Edge-Triggered D Flip-Flop
❖ Similar to positive edge-triggered flip-flop
❖ The first inverter at the Master C input is removed
❖ Only one latch is enabled at any given time
When Clk=1, the master is enabled and the D input is latched (slave disabled)
When Clk=0, the slave is enabled to generate the outputs (master is disabled)

𝑄𝑚
Outputs
Master Slave change when
𝑄𝑚
Clk Clk changes
from 1 to 0
 D Flip-Flop Timing Diagram
❖ The diagram shows the timing of a positive-edge D Flip-Flop

❖ The master latch changes its output Qm when the clock C is 0

❖ The rising edge of the clock triggers the D Flip-Flop

❖ Notice the slight delay in the output Q after the rising edge

Clk

Qm

Time
 Graphic Symbols for Flip-Flops

𝐷𝑎𝑡𝑎 𝐷 𝑄 𝐷𝑎𝑡𝑎 𝐷 𝑄
Flip Flip
Flop Flop
𝐶𝑙𝑘 𝑄 𝐶𝑙𝑘 𝑄

❖ A Flip-Flop has a similar symbol to a Latch

❖ The difference is the arrowhead at the clock input

❖ The arrowhead indicates sensitivity to the edge of the clock

❖ A circle at the Clk input indicates negative edge-triggered FF

 JK Flip-Flop
❖ The D Flip-Flop is the most commonly used type
❖ The JK is another type of Flip-Flop with inputs: J, K, and Clk
❖ When JK = 10 ➔ Set, When JK = 01 ➔ Reset
❖ When JK = 00 ➔ No change, When JK = 11 ➔ Invert outputs
❖ JK can be implemented using two Clocked SR latches and gates

Master Slave
𝑄1
𝑆 𝑆 𝑄
SR Latch

SR Latch
𝐽
𝐶𝑙𝑘 𝐶 𝐶
𝐾 𝑄1
𝑅 𝑅 𝑄
 T Flip-Flop
❖ The T (Toggle) flip-flop has inputs: T and Clk

❖ When T = 0 ➔ No change, When T = 1 ➔ Invert outputs

❖ The T flip-flop can be implemented using a JK flip-flop

❖ It can also be implemented using a D flip-flop and a XOR gate

 Flip-Flop Characteristic Table
❖ Defines the operation of a flip-flop in a tabular form

❖ Next state is defined in terms of the current state and the inputs

𝑄(𝑡) refers to current state before the clock edge arrives

𝑄(𝑡 + 1) refers to next state after the clock edge arrives

D Flip-Flop JK Flip-Flop T Flip-Flop

D Q(t+1) J K Q(t+1) T Q(t+1)
0 0 Reset 0 0 Q(t) No change 0 Q(t) No change
1 1 Set 0 1 0 Reset 1 Q'(t) Complement
1 0 1 Set
1 1 Q'(t) Complement
 Flip-Flop Characteristic Equation
❖ The characteristic equation defines the operation of a flip-flop
❖ For D Flip-Flop: 𝑄 𝑡 + 1 = 𝐷
❖ For JK Flip-Flop: 𝑄 𝑡 + 1 = 𝐽 𝑄′ 𝑡 + 𝐾 ′ 𝑄(𝑡)
❖ For T Flip-Flop: 𝑄 𝑡 + 1 = 𝑇 ⨁ 𝑄(𝑡)
❖ Clearly, the D Flip-Flop is the simplest among the three

D Flip-Flop JK Flip-Flop T Flip-Flop

D Q(t+1) J K Q(t+1) T Q(t+1)
0 0 Reset 0 0 Q(t) No change 0 Q(t) No change
1 1 Set 0 1 0 Reset 1 Q'(t) Complement
1 0 1 Set
1 1 Q'(t) Complement
 Timing Considerations for Flip-Flops
❖ Setup Time (Ts): Time duration for which the data input must
be valid and stable before the arrival of the clock edge.

❖ Hold Time (Th): Time duration for which the data input must
not be changed after the clock transition occurs.

❖ Ts and Th must be ensured for the proper operation of flip-flops

Rising
Edge Clock

Ts Th

Valid data-in Data Can be Modified after Th

 Summary
❖ In a sequential circuit there is internal memory
 Output is a function of current inputs and present state
 The stored memory value defines the present state
 Similarly, the next state depends on current inputs and present state

❖ Two types of sequential circuits:

 Synchronous sequential circuits are clocked (easier to implement)
 Asynchronous sequential circuits are not clocked

❖ Two types of Memory elements: Latches and Flip-Flops

❖ Latches are level-sensitive, flip-flops are edge-triggered
❖ Flip-flops are better memory elements for synchronous circuits
❖ A flip-flop is described using a characteristic table and equation