Unit – 5

Introduction to RISC and CISC: RISC

(Reduced Instruction Set Computer)

RISC stands for Reduced Instruction Set Computer. To execute each instruction, if there is separate electronic
circuitry in the control unit, which produces all the necessary signals, this approach of the design of the
control section of the processor is called RISC design. It is also called hard-wired approach.

Examples of RISC processors:

 IBM RS6000, MC88100.

 DEC’s Alpha 21064, 21164 and 21264 processors

Features of RISC Processors: The standard features of RISC processors are listed below:

 RISC processors use a small and limited number of instructions.

 RISC machines mostly uses hardwired control unit.

 RISC processors consume less power and are having high performance.

 Each instruction is very simple and consistent.

 RISC processors uses simple addressing modes.

 RISC instruction is of uniform fixed length.

CISC (Complex Instruction Set Computer)

CISC stands for Complex Instruction Set Computer. If the control unit contains a number of micro-
electronic circuitry to generate a set of control signals and each micro-circuitry is activated by a micro-
code, this design approach is called CISC design.

Examples of CISC processors are:

 Intel 386, 486, Pentium, Pentium Pro, Pentium II, Pentium III

 Motorola’s 68000, 68020, 68040, etc.

Features of CISC Processors: The standard features of CISC processors are listed below:

 CISC chips have a large amount of different and complex instructions.

 CISC machines generally make use of complex addressing modes.

  Different machine programs can be executed on CISC machine.

 CISC machines uses micro-program control unit.

 CISC processors are having limited number of registers.

Difference between RISC and CISC Processor

S.No. RISC CISC

1. RISC is a reduced instruction set. CISC is a complex instruction set.

2. The number of instructions is less as compared to The number of instructions is more as compared to
CISC. RISC.

3. The addressing modes are less. The addressing modes are more.

4. It works in a fixed instruction format. It works in a variable instruction format.

5. The RISC consumes low power. The CISC consumes high power.

6. The RISC processors are highly pipelined. The CISC processors are less pipelined.

7. It optimizes the performance by focusing on It optimizes the performance by focusing on

software. hardware.

8. Requires more RAM. Requires less RAM.

The ARM instruction pipeline

The ARM uses a pipeline to increase the speed of the flow of instructions to the processor. This
allows several operations to take place simultaneously, and the processing, and memory
systems to operate continuously.

A three-stage pipeline is used, so instructions are executed in three stages:

 Fetch
 Decode

 Execute.

The three-stage pipeline is shown in

The instruction pipeline

During normal operation, while one instruction is being executed, its successor is being
decoded, and a third instruction is being fetched from memory. The program counter points to
the instruction being fetched rather than to the instruction being executed. This is important
because it means that the Program Counter (PC) value used in an executing instruction is
always two instructions ahead of the address.

The pipeline design for each ARM family differs. For example, The ARM9 core increases the
pipeline length to five stages, as shown in Figure 2.9. The ARM9 adds a memory and writeback
stage, which allows the ARM9 to process on average 1.1 Dhrystone MIPS per MHz—an
increase in instruction throughput by around 13% compared with an ARM7. The maximum core
frequency attainable using an ARM9 is also higher.
The ARM10 increases the pipeline length still further by adding a sixth stage, as shown in Figure
2.10. The ARM10 can process on average 1.3 Dhrystone MIPS per MHz, about 34% more
throughput than an ARM7 processor core, but again at a higher latency cost.

Even though the ARM9 and ARM10 pipelines are different, they still use the same pipeline
executing characteristics as an ARM7. Code written for the ARM7 will execute on an ARM9 or
ARM10.
ARM PROCESSOR FAMILIES
ARM has designed a number of processors that are grouped into different families according to
the core they use. The families are based on the ARM7, ARM9, ARM10, and ARM11 cores. The
postfix numbers 7, 9, 10, and 11 indicate different core designs. The ascending number
equates to an increase in performance and sophistication. ARM8 was developed but was soon
superseded.

Table 2.9 shows a rough comparison of attributes between the ARM7, ARM9, ARM10, and
ARM11 cores. The numbers quoted can vary greatly and are directly dependent upon the type
and geometry of the manufacturing process, which has a direct effect on the frequency (MHz)
and power consumption (watts).
Within each ARM family, there are a number of variations of memory management, cache, and
TCM processor extensions. ARM continues to expand both the number of families available and
the different variations within each family.

You can find other processors that execute the ARM ISA such as StrongARM and XScale. These
processors are unique to a particular semiconductor company, in this case Intel.

Table 2.10 summarizes the different features of the various processors. The next subsections
describe the ARM families in more detail, starting with the ARM7 family.
ARM7 Family

The ARM7 core has a Von Neumann–style architecture, where both data and instructions use
the same bus. The core has a three-stage pipeline and executes the architecture ARMv4T
instruction set.

The ARM7TDMI was the first of a new range of processors introduced in 1995 by ARM. It is
currently a very popular core and is used in many 32-bit embedded processors. It provides a
very good performance-to-power ratio. The ARM7TDMI processor core has been licensed by
many of the top semiconductor companies around the world and is the first core to include the
Thumb instruction set, a fast multiply instruction, and the EmbeddedICE debug technology.
One significant variation in the ARM7 family is the ARM7TDMI-S. The ARM7TDMI-S has the
same operating characteristics as a standard ARM7TDMI but is also synthesizable. ARM720T is
the most flexible member of the ARM7 family because it includes an MMU. The presence of the
MMU means the ARM720T is capable of handling the Linux and Microsoft embedded platform
operating systems. The processor also includes a unified 8K cache. The vector table can be
relocated to a higher address by setting a coprocessor 15 register.

Another variation is the ARM7EJ-S processor, also synthesizable. ARM7EJ-S is quite different
since it includes a five-stage pipeline and executes ARMv5TEJ instructions. This version of the
ARM7 is the only one that provides both Java acceleration and the enhanced instructions but
without any memory protection.

ARM9 FAMILY
The ARM9 family was announced in 1997. Because of its five-stage pipeline, the ARM9
processor can run at higher clock frequencies than the ARM7 family. The extra stages improve
the overall performance of the processor. The memory system has been redesigned to follow
the Harvard architecture, which separates the data D and instruction I buses.
 The first processor in the ARM9 family was the ARM920T, which includes a separate D I cache
and an MM+U. This processor can be used by operating systems requiring virtual
+
memory support. ARM922T is a variation on the ARM920T but with half the D I cache siz e.

The ARM940T includes a smaller D I c+ache and an MPU. The ARM940T is designed for
applications that do not require a platform operating system. Both ARM920T and ARM940T
execute the architecture v4T instructions.

The next processors in the ARM9 family were based on the ARM9E-S core. This core is a
synthesizable version of the ARM9 core with the E extensions. There are two variations: the
ARM946E-S and the ARM966E-S. Both execute architecture v5TE instructions. They also support
the optional embedded trace macrocell (ETM), which allows a developer to trace instruction
and data execution in real time on the processor. This is important when debugging
applications with time-critical segments.

The ARM946E-S includes TCM, cache, and an MPU. The sizes of the TCM and caches are
configurable. This processor is designed for use in embedded control applications that require
deterministic real-time response. In contrast, the ARM966E does not have the MPU and cache
extensions but does have configurable TCMs.

The latest core in the ARM9 product line is the ARM926EJ-S synthesizable processor core,
announced in 2000. It is designed for use in small portable Java-enabled devices such as 3G
phones and personal digital assistants (PDAs). The ARM926EJ-S is the first ARM processor
core to include the Jazelle technology, which acce+lerates Java bytecode execution. It
features an MMU, configurable TCMs, and D I caches with zero or nonzero wait state
memories.

ARM10 Family
The ARM10, announced in 1999, was designed for performance. It extends the ARM9 pipeline
to six stages. It also supports an optional vector floating-point (VFP) unit, which adds a seventh
stage to the ARM10 pipeline. The VFP significantly increases floating-point performance and is
compliant with the IEEE 754.1985 floating-point standard.

The ARM1020E is the first processor to use an ARM10E core. Like the ARM9E, it includes the
enhanced E instructions. It has separate 32K D I caches, opti+onal vector floating-point unit,
and
an MMU. The ARM1020E also has a dual 64-bit bus interface for increased performance.

ARM1026EJ-S is very similar to the ARM926EJ-S but with both MPU and MMU. This processor
has the performance of the ARM10 with the flexibility of an ARM926EJ-S.

ARM11 Family
The ARM1136J-S, announced in 2003, was designed for high performance and power- efficient
applications. ARM1136J-S was the first processor implementation to execute architecture
ARMv6 instructions. It incorporates an eight-stage pipeline with separate load- store and
 arithmetic pipelines. Included in the ARMv6 instructions are single instruction multiple data
(SIMD) extensions for media processing, specifically designed to increase video processing
performance.

The ARM1136JF-S is an ARM1136J-S with the addition of the vector floating-point unit for fast
floating-point operations.

Specialized Processors
StrongARM was originally co-developed by Digital Semiconductor and is now exclusively
licensed by Intel Corporation. It is has been popular for PDAs and applications that require
performance with low power consumption. It is a Harvard architecture with separate D+ I
caches. StrongARM was the first high-performance ARM processor to include a five-stage
pipeline, but it does not support the Thumb instruction set.

Intel’s XScale is a follow-on product to the StrongARM and offers dramatic increases in
performance. At the time of writing, XScale was quoted as being able to run up to 1 GHz.
XScale executes architecture v5TE instructions. It is a Harvard architecture and is similar to the
StrongARM, as it also includes an MMU.

SC100 is at the other end of the performance spectrum. It is designed specifically for low-power
security applications. The SC100 is the first SecurCore and is based on an ARM7TDMI core with
an MPU. This core is small and has low voltage and current requirements, which makes it
attractive for smart card applications.
Thumb Instruction Set
Thumb encodes a subset of the 32-bit ARM instructions into a 16-bit instruction set
space. Since Thumb has higher performance than ARM on a processor with a 16-bit data bus,
but lower performance than ARM on a 32-bit data bus, use Thumb for memory-constrained
systems.

Thumb has higher code density—the space taken up in memory by an executable

program—than ARM. For memory-constrained embedded systems, for example, mobile
phones and PDAs, code density is very important. Cost pressures also limit memory size, width,
and speed.

On average, a Thumb implementation of the same code takes up around 30% less
memory than the equivalent ARM implementation. As an example, the same divide code
routine implemented in ARM and Thumb assembly code. Even though the Thumb
implementation uses more instructions, the overall memory footprint is reduced. Code density
was the main driving force for the Thumb instruction set. Because it was also designed as a
compiler target, rather than for hand-written assembly code, we recommend that you write
Thumb-targeted code in a high- level language like C or C++.

Each Thumb instruction is related to a 32-bit ARM instruction. A simple Thumb ADD
instruction being decoded into an equivalent ARM ADD instruction. Only the branch relative
instruction can be conditionally executed. The limited space available in 16 bits causes the
barrel shift operations ASR, LSL, LSR, and ROR to be separate instructions in the Thumb ISA.
 Thumb instruction set.

THUMB REGISTER USAGE

In Thumb state, you do not have direct access to all registers. Only the low registers r0
to r7 are fully accessible, as shown in below Table 4.2. The higher registers r8 to r12 are only
accessible with MOV, ADD, or CMP instructions. CMP and all the data processing instructions
that operate on low registers update the condition flags in the cpsr.
 You may have noticed from the Thumb instruction set list and from the Thumb register
usage table that there is no direct access to the cpsr or spsr. In other words, there are no MSR-
and MRS-equivalent Thumb instructions.

To alter the cpsr or spsr, you must switch into ARM state to use MSR and MRS. Similarly,
there are no coprocessor instructions in Thumb state. You need to be in ARM state to access
the coprocessor for configuring cache and memory management.

OTHER BRANCH INSTRUCTIONS

There are two variations of the standard branch instruction, or B. The first is similar to
the ARM version and is conditionally executed; the branch range is limited to a signed
8-bit
immediate, or 256 to−+254 bytes. The second version removes the conditional part of the
−
instruction and expands the effective branch range to a signed 11-bit imme diate, or 2048
to
+2046 bytes.

The conditional branch instruction is the only conditionally executed instruction in

Thumb state.

Syntax: B<cond> label

B label

BL label
General features of ARM 7( LPC2148) microcontroller
This ARM microcontroller is best for critical code size applications because it can
easily reduce the code size to 30% without reducing the performance. They are easily available
in tiny size and consume less power as compared to other microcontrollers. So, due to tiny size
and consume less power, these microcontrollers are ideal for that applications where
miniaturization is major requirements such as at point of sale and access control etc. It consists
of serial communication interface whose ranging from a USB 2,full speed device, multiple
UARTs, SPI,SSP to 12C bus and 8kB to, up to 40 kB on chip SRAM, all these features are so
much appropriate for communication gateway and protocol converters. Beside this, it also
consists of various 32 bit timers,10 bit DAC (Digital to analog converter),10 bit ADC (analog to
digital converter) ,PWM(pulse width modulation) channel,45 fast GPIO lines and level sensitive
external interrupts pins make this microcontroller very special for medical system and industrial
controls. The general architecture block diagram of this LPC 2148 microcontroller with all their
essential parts is shown in figure 1
Here is the general architecture block diagram of LPC 2148 microcontroller with all their
essential parts,

Figure 1 General Architecture Block Diagram of LPC 2148 Microcontroller with all their
essential parts.

Description about General Architecture of LPC 2148 Microcontroller

LPC 2148 microcontroller consist of three buses such as ARM7 Local bus, AHB ( Advanced
high performance bus) and VPB bus etc. these buses are used for performing different function
and these are also consisting of different functioning parts such as ,

GPIO pins: ARM based LPC2148 microcontroller has 45 general purpose input output pins. The
operating voltage of these input output pins is 5 volt.
On Chip Static RAM (SRAM): This on chip static ram is used for storing data or code. This
ram could be accessed as 8 bit,16 bit or 32 bit. The memory of this ram could be increased to 8
kB,16 kB or 32 kB by using USB.

On Chip Flash Program Memory: LPC 2148 microcontroller contains 512 kB on chip flash
memory this memory is used for almost data storage or code storage. The programming of this
flash memory could be accomplished with several ways.
Vectored Interrupt Controller: All input requests are received by vectored interrupt controller
(VIC) and it converts them into fast interrupt request (FIQ). So, fast interrupt request and non
fast interrupt requests are defined by programming setting in vectored interrupt controller.
Digital to analog Converter: This LPC 2148 microcontroller has one 10 bit digital to analog
converter (DAC).This converter converts the digital input into analog output. The maximum
DAC output voltages are called VREF voltages. Power down mode and buffered output is also
available in this digital to analog converter.
Analog to Digital Converter: This LPC 2148 microcontroller also contains two analog to
digital converters whose names are ADC0 and ADC0. There are 14 total number of inputs of
ADC are available and these two converters successfully converts 10 bit analog input to digital
output. The measurement rang of each convert is 0V to V REF and global star command is used for
both converters.

UART: This LPC 2148 microcontroller contains two UART whose name are UART 0 and
UART 01. These UARTs are provided the full mode control handshake interface during
transmitting or receiving the data lines. These are used 16 Byte data rate during transmitting or
receiving the data. For covering wide range of baud rate they also contain the built in functional
baud rate generator, therefore there is no need of any external crystal of specific value.
I2C Bus Serial I/O Controller: I2 C bus serial is bidirectional multi master bus. It can easily
control two or more buses which are connected to it. The data which is transferred for master bus
to slave bus is transferred through this bidirectional bus at baud rate up 400 k. Similarly the serial
clock synchronization allows the device to communicate the data of different baud rate pass
through only one serial bus. This clock synchronization could be used as handshake mechanism
for resuming or suspending the data transfer.
SPI Serial I/O Control: This SPI serial I/O control supports the duplex data transfer, means
this control supports the device for transferring the data whose range 4 kB to 16 kB from master
bus to slave bus. This operation is called synchronous serial communication operation from
master but to slave bus. This data is transmitted or received in 8 frames and each frame is
contains 4 bits to 16 bits.
Timers: This LPC 2148 microcontroller has two timers or counters. These timers are 32 bit and
are programmable with 32 bit pre scaler value as well as it also has one external event counter.
Each timer has four 32 bit capture channels which take the snapshot of timer value during the
transition of any input signal. With the help of this capture event the interruption could be also
generate.

Watch Dog Timer: This LPC 2148 microcontroller also contains the watch dog timer whose
main purposes is to reset the microcontroller with in specific amount of time during erroneous
state. After this state it again turned on the microcenter with in specific amount of time limit.
Real Time Clock (RTC): In this LPC 2148 microcontroller, the RTC is designed to set the
counters for the measuring the whole time when the controller is in operating mode or idle mode.
It has designed to consume little power which make it suitable for battery powered systems
where CPU is not continually in operating mode.
Crystal Oscillator: This LPC 2148 microcontroller contains the on chip integrated oscillator
which operate with an external crystal whose range is in between 1 MHz to 25 MHz Its output
frequency is called focs and controller clock frequency is called CCLK. These names are used for
making rate equation. These frequencies would be same when the PLL is connected and in
running position.

PLL: This LPC 2148 microcontroller contains two phase locked loops whose names are PLL0
and PLL1.The input frequency whose range is in between 1 MHz to 25 MHz is accepted by this
PLL. This frequency range could be extended from 10 MHz to 60 MHz by using the current
controlled oscillator (CCO)

LPC 2148 Microcontroller Registers: This LPC 2148 microcontroller also consists of one
program status register and 16 general purposes registers whose names are R0 to R15. These
register has wide range such as 8,16 and 32 bits. Beside this, it also consists of one shadow
register which is selected such as operation mode switch.
Interrupts : It has vectored interrupt controller. VIC can be configured sixteen configurable
priorities. LPC2148 microcontroller has 9 level or edge triggered external interrupts.
Power saving modes: It has power saving modes also like idle mode and sleep mode.