EXPERIMENT : 1

Objective: Implementation of Digital Logic Gates using Verilog.

Resources Required:

Hardware requirements: Computer System

Software requirements: XILINX VIVADO Software

Theory:

A logic gate is a device that acts as a building block for digital circuits. They perform basic logical
functions that are fundamental to digital circuits. Most electronic devices we use today will have
some form of logic gates in them. We can implement different digital circuits with the combination
of various logic gates. Types of different digital logic gates and their Boolean expression (Inputs: "a"
and "b", and Output is "f").

Verilog Code:

module basic_gates( a, b, out_and, out_or, out_not, out_nand, out_nor, out_xor, out_xnor);

input a, b;
output out_and, out_or, out_not, out_nand, out_nor, out_xor, out_xnor;
assign out_and = a&b;
assign out_or = a|b;
assign out_not = ~a;
assign out_nand = ~(a&b);
assign out_nor = ~(a|b);
assign out_xor = a^b;
assign out_xnor = ~(a^b);

endmodule

TestBench code:

module TB_basic_gates();
reg a,b;
wire out_and, out_or, out_not, out_nand, out_nor, out_xor, out_xnor;
basic_gates dut(a, b, out_and, out_or, out_not, out_nand, out_nor, out_xor, out_xnor);
initial begin
$monitor($time, " a=%b, b=%b, out_and=%b, out_or=%b, out_not=%b, out_nand=%b,
out_nor=%b, out_xor=%b, out_xnor=%b", a, b, out_and, out_or, out_not, out_nand, out_nor,
out_xor, out_xnor);
a=0;b=0;
#100 a=0; b=1;
#100 a=1; b=0;
#100 a=1; b=1;
#100 $finish;
end
endmodule

Schematic:

Timing Diagram:
Power Report:

Result:

Verilog code of digital gates was simulated and correct results were obtained for all the Boolean
operation, RTL schematic for the code and power report was generated.
 EXPERIMENT : 2

Objective: Write Verilog code for Implementation of 3:8 decoder.

Resources Required:

Hardware requirements: Computer System

Software requirements: XILINX VIVADO Software

Theory:

The combinational circuit that changes the binary information into 2 output lines is known as
Decoders. The binary information is passed in the form of N input lines. The output lines define the
2-bit code for the binary information. In simple words, the Decoder performs the reverse operation
of the Encoder. At a time, only one input line is activated for simplicity. The produced 2-bit output
code is equivalent to the binary information.

Verilog Code:

module decoder_3_8(p,q,r,out);
input p;
input q;
input r;
output [7:0] out;

assign out[0] = (~p&~q&~r);

assign out[1] = (~p&~q&r);
assign out[2] = (~p&q&~r);
assign out[3] = (~p&q&r);
assign out[4] = (p&~q&~r);
assign out[5] = (p&~q&r);
assign out[6] = (p&q&~r);
assign out[7] = (p&q&r);
endmodule

TestBench code:

module test_decoder();
reg p,q,r;
wire [7:0]out;
decoder_3_8 dut(p,q,r,out);
initial begin
 $monitor($time,"p=%b, q=%b, r=%b, out=%b",p,q,r,out);
p=0; q=0; r=0;
#100
p=0; q=0; r=1;
#100
p=0; q=1; r=0;
#100
p=1; q=1; r=1;
#100
$finish;
end
endmodule

Schematic:

Timing Diagram:
Power Report:

Result:

RTL schematic, simulation waveform and power report for a 3:8 Decoder was generated using the
Verilog code mentioned above.
 EXPERIMENT : 3

Objective: Write Verilog code for Implementation of 8:1 Multiplexer.

Resources Required:

Hardware requirements: Computer System

Software requirements: XILINX VIVADO Software

Theory:

A multiplexer, also known as a data selector, is a device that selects between several analog or
digital input signals and forwards the selected input to a single output line. The selection is directed
by a separate set of digital inputs known as select lines. A multiplexer of "2" inputs has 'n' select
lines, which are used to select which input line to send to the output.

Verilog Code:

module mux_8_1(
input [7:0] a,
input [2:0] s,
output out
);
reg out;
always@(*)
begin
case(s)
3'd0 : out = a[0];
3'd1 : out = a[1];
3'd2 : out = a[2];
3'd3 : out = a[3];
3'd4 : out = a[4];
3'd5 : out = a[5];
3'd6 : out = a[6];
3'd7 : out = a[7];
endcase
end
endmodule

TestBench code:

module test_mux();
reg [7:0]A;
reg [2:0]S;
wire f;
 mux_8_1 DUT(.a(A),.s(S),.out(f));
initial
begin
$monitor($time,"a=%b, s=%b, out=%b", A,S,f);
A = 8'b10010101;
#100 S = 3'b101;
#100 S = 3'b100;
#100 S = 3'b011;
#100 S = 3'b111;
#100 $finish;
end
endmodule

Schematic:

Timing Diagram:
Power Report:

Result:

Verilog code of 8:1 multiplexer is simulated and RTL schematic and power report was also generated.
 EXPERIMENT : 4

Objective: Write Verilog code for 4-bit Sequence Detector.

Resources Required:

Hardware requirements: Computer System

Software requirements: XILINX VIVADO Software

Theory:
A Sequence detector accepts as input a string of bits: either 0 or 1. Its output goes to 1 when a target
sequence has been detected.
There are two basic types:
 Overlap
 Non-overlap
In a Sequence detector that allows overlap, the final bits of one sequence can be the start of another
sequence.

INPUT DATA STREAM X 11011011011

1011 detector output with overlap Z 00001001001
1011 detector output with no overlap Z 00001000001

Verilog Code:

module sequence_detector(sequence_in, clk, rst, detector_out);

input sequence_in;
input clk;
input rst;
output reg detector_out;

parameter Zero = 3'b000,

One = 3'b001,
OneZero = 3'b011,
OneZeroOne = 3'b010,
OneZeroOneOne = 3'b110;

reg [2:0] current_state, next_state;

always @(posedge clk, posedge rst)

begin
if(rst==1)
current_state <= Zero;
else
current_state <= next_state;
end
always @(current_state, sequence_in)
begin
case(current_state)
Zero:
begin
if(sequence_in==1)
next_state=One;
else
next_state=Zero;
end
One:
begin
if(sequence_in==0)
next_state=OneZero;
else
next_state=One;
end
OneZero:
begin
if(sequence_in==0)
next_state=Zero;
else
next_state=OneZeroOne;
end
OneZeroOne:
begin
if(sequence_in==0)
next_state=OneZero;
else
next_state=OneZeroOneOne;
end
OneZeroOneOne:
begin
if(sequence_in==0)
next_state=OneZero;
else
next_state=One;
end
default: next_state=Zero;
endcase
end

always @(current_state)
 begin
case(current_state)
Zero : detector_out = 0;
One : detector_out = 0;
OneZero : detector_out = 0;
OneZeroOne : detector_out = 0;
OneZeroOneOne : detector_out = 1;
default : detector_out = 0;
endcase
end
endmodule

Testbench Code:

module test_seqdetect();
reg sequence_in;
reg clk;
reg rst;
wire detector_out;
sequence_detector
detect_seq( .sequence_in(sequence_in), .clk(clk), .rst(rst), .detector_out(detector_out));

initial
begin
clk = 0;
forever #5 clk = ~clk;
end

initial
begin
sequence_in = 0;
rst = 1;
#30 rst = 0;
#40 sequence_in = 1;
#10 sequence_in = 0;
#10 sequence_in = 1;
#20 sequence_in = 0;
#20 sequence_in = 1;
#20 sequence_in = 0;
end
endmodule
Schematic:

Timing Diagram:

Power Report:

Result:

Verilog code for sequence detector is simulated and RTL schematic and power report was also
generated. The above code has successfully detected 1011 in the input bit stream.
 EXPERIMENT : 5

Objective: Implementation of 4-bit adder using full adder.

Resources Required:

Hardware requirements: Computer System

Software requirements: XILINX VIVADO Software

Theory:
The full adder is a digital component that performs three numbers an implemented using the logic gates. It
is the main component inside an ALU of a processor and is used to increment addresses, table indices, buffer
pointers, and other places where addition is required.

Verilog Code:

module adder_four_bit( a, b, cin, s, cout);

input [3:0] a,b;
input cin;
output [3:0] s;
output cout;
wire c1, c2, c3, c4;

full_adder FA0(.a(a[0]), .b(b[0]), .cin(cin), .sum(s[0]), .cout(c1));

full_adder FA1(.a(a[1]), .b(b[1]), .cin(c1), .sum(s[1]), .cout(c2));
full_adder FA2(.a(a[2]), .b(b[2]), .cin(c2), .sum(s[2]), .cout(c3));
full_adder FA3(.a(a[3]), .b(b[3]), .cin(c3), .sum(s[3]), .cout(c4));
assign cout=c4;

endmodule

module full_adder(a, b, cin, sum, cout);

input a, b, cin;
output sum, cout;

assign sum = a^b^cin;

assign cout = (a&b)|(b&cin)|(cin&a);

endmodule

Testbench Code:

module adder_4bit_test();
reg [3:0] a, b;
reg cin;
 wire [3:0] s;
wire cout;

adder_four_bit testadd(.s(s), .cout(cout), .a(a), .b(b), .cin(cin));

initial
begin
a=4'b0000;
b=4'b0001;
cin=1'b1;

#30
a=4'b0001;
b=4'b0001;
cin=1'b0;

#30
a=4'b0010;
b=4'b0001;
cin=1'b1;

#30
a=4'b0100;
b=4'b0101;
cin=1'b1;

#30
a=4'b1100;
b=4'b1101;
cin=1'b1;

#30
$finish;
end

endmodule
Schematic:

Timing Diagram:

Power Report:

Result:

Verilog code for 4-bit full adder using full adder is simulated and RTL schematic and power report was
also generated. The above code has successfully added the two 4-bit numbers.
 EXPERIMENT : 6

Objective: Implementation of 1:8 Demultiplexer.

Resources Required:

Hardware requirements: Computer System

Software requirements: XILINX VIVADO Software

Theory:
A Demultiplexer is also called Demux, or data distributor and its operation is quite opposite to a multiplexer
because it is an inverse to the multiplexer. The multiplexer is a many-to-one circuit whereas the
Demultiplexer is a one-to-many circuit. By using Demultiplexer, the transmission of data can be done
through one single input to a number of output data lines. Generally, Demultiplexers are used in decoder
circuits and Boolean function generators.
Verilog Code:

module demux_1_8(y,s,a);
input a;
input [2:0] s;
output reg [7:0] y;

always@(*)
begin
y=8'b0;
y[s] = a;
end
endmodule

Testbench Code:

module test_demux();
reg a;
reg [2:0]s;
wire [7:0] y;

demux_1_8 dut(.a(a), .s(s), .y(y));

initial
begin
a=1;
s=3'd5;
 #30
a=0; s=3'd6;
#30
a=1; s=3'd3;
#30
s=3'd1;
#30
s=3'd2;
#30
$finish;
end
endmodule

Schematic:

Timing Diagram:
Power Report:

Result:

Verilog code of 1:8 Demultiplexer is simulated and RTL schematic and power report was also
generated.
 EXPERIMENT : 7

Objective: Implementation of 8:3 Encoder.

Resources Required:

Hardware requirements: Computer System

Software requirements: XILINX VIVADO Software

Theory:
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has maximum of 2n
input lines and 'n' output lines; hence it encodes the information from 2n inputs into an n-bit code. It will
produce a binary code equivalent to the input, which is active High. Therefore, the encoder encodes 2n input
lines with 'n' bits.

Verilog Code:

module encoder_8_3(y,en,a);
input [7:0] y;
input en;
output reg [2:0] a;

always @(*)
begin
if(en)
case(y)
8'b00000001 : a = 3'd0;
8'b00000010 : a = 3'd1;
8'b00000100 : a = 3'd2;
8'b00001000 : a = 3'd3;
8'b00010000 : a = 3'd4;
8'b00100000 : a = 3'd5;
8'b01000000 : a = 3'd6;
8'b10000000 : a = 3'd7;
endcase
end
endmodule

Testbench Code:
module test_encoder;
reg [7:0]Y;
reg EN;
wire[2:0]A;

encoder_8_3 uut(.y(Y), .en(EN), .a(A));

initial
begin
EN=1;
Y=8'h01;
#30 Y=8'h02;
#30 Y=8'h04;
#30 Y=8'h08;
#30 Y=8'h10;
#30 Y=8'h20;
#30 Y=8'h40;
#30 Y=8'h80;
#30 $finish;
end
endmodule

Schematic:
Timing Diagram:

Power Report:

Result:

Verilog code of 8:3 Encoder is simulated and RTL schematic and power report was also generated.
 EXPERIMENT : 8

Objective: Implementation of Universal Shift register using verilog.

Resources Required:

Hardware requirements: Computer System

Software requirements: XILINX VIVADO Software

Theory:
A Universal shift register is a register which has both the right shift and left shift with parallel load
capabilities. Universal shift registers are used as memory elements in computers. A Unidirectional shift
register is capable of shifting in only one direction. A bidirectional shift register is capable of shifting in both
the directions. The Universal shift register is a combination design of bidirectional shift register and a
unidirectional shift register with parallel load provision.

Register Operations Control Signals:

S0 S1 Register Operation

0 0 No Changes

0 1 Shift right

1 0 Shift Left

1 1 Parallel Load

Verilog Code:

module universal_shift_register(clr, clk, sel, parin,out);

input [1:0]sel;
input clr, clk;
input [3:0] parin;
output reg [3:0] out;

always@(posedge clk)
begin
if(clr)
out = 4'd0;
else
case(sel)
 2'b00 : out = out;
2'b01 : out = {parin[0],parin[3:1]};
2'b10 : out = {parin[2:0], parin[3]};
2'b11 : out = parin;
endcase
end
endmodule

Testbench Code:

module test_unsr;
reg [3:0] parin;
reg clr, clk;
reg [1:0] sel;
wire [3:0] out;

universal_shift_register uut(.sel(sel), .clr(clr), .clk(clk) , .out(out), .parin(parin));

initial
begin
clk = 0;
forever #20 clk=~clk;
end

initial
begin
parin = 4'b1011;
sel = 2'b00;
clr = 1'b1;
#50

parin = 4'b1011;
sel = 2'b00;
clr = 1'b0;
#50;

parin = 4'b1011;
sel = 2'b01;
clr = 1'b0;
 #50;

parin = 4'b1011;
sel = 2'b10;
clr = 1'b0;
#50;

parin = 4'b1011;
sel = 2'b11;
clr = 1'b0;
#50;
end

initial
#350 $finish;

endmodule

Schematic:
Timing Diagram:

Power Report:

Result:

Verilog code of Universal Shift register is simulated and RTL schematic and power report was also
generated.
 EXPERIMENT : 9

Objective: Implementation of Combinational circuit using FPGA board.

Resources Required:

Hardware requirements: Computer System

Software requirements: XILINX VIVADO Software

FPGA board family : Artix-7 Low voltage

Package : csg 324

Part: xc7a100tlcsg324-2L

Speed grade: -2L

Theory:
Nexys 4 DDR board: The Nexys4 DDR board is a complete, ready-to-use digital circuit development platform
based on the latest Artix-7T™ Field Programmable Gate Array (FPGA) from Xilinx.
The Artix-7 FPGA is optimized for high performance logic, and offers more capacity, higher performance, and
more resources than earlier designs. Artix-7 100T features include:

 15,850 logic slices, each with four 6-input LUTs and 8 flip-lорѕ

 4,860 Kbits of fast block RAM

 Six clock management tiles, each with phase-locked loop (PLL)

 240 DSP slices

 Internal clock speeds exceeding 450 MHz

 On-chip analog-to-digital converter (XADC)

Verilog Code:

module mux_on_fpga(a,s,out);
input [3:0]a;
input [1:0]s;
output reg out;
always @(*)
begin
case(s)
0 : out = a[0];
 1 : out = a[1];
2 : out = a[2];
3 : out = a[3];
endcase
end
endmodule

Constraint file (xdc format):

set_property IOSTANDARD LVCMOS33 [get_ports {a[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {a[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {s[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports out]
set_property PACKAGE_PIN H17 [get_ports out]
set_property PACKAGE_PIN H6 [get_ports {a[0]}]
set_property PACKAGE_PIN U12 [get_ports {a[1]}]
set_property PACKAGE_PIN U11 [get_ports {a[2]}]
set_property PACKAGE_PIN V10 [get_ports {a[3]}]
set_property PACKAGE_PIN U8 [get_ports {s[0]}]
set_property PACKAGE_PIN R16 [get_ports {s[1]}]

Schematic:
Implementation:

Power Report:

Result:

After completing the processes - RTL Analysis, Synthesis, Implementation, And Generating Bit Stream,
the program is burn into the FPGA. The outputs on the respective LEDS showed the correct output on
the basis of the input combinations of select lines.
 EXPERIMENT : 10

Objective: Implementation of 4*4 array multiplier using verilog.

Resources Required:

Hardware requirements: Computer System

Software requirements: XILINX VIVADO Software

Theory:
The design structure of the array Multiplier is regular, it is based on the add shift algorithm
principle.

Partial product = the multiplicand * multiplier bit

where AND gates are used for the product, the summation is done using Full Adders and Half
Adders where the partial product is shifted according to their bit orders.

In an n*n array multiplier, n*n AND gates compute the partial products and the addition of partial
products can be performed by using n* (n-2) Full adders and n Half adders.

Verilog Code:

module multiplier_4x4(product,in1,in2);
input [3:0] in1, in2;
output [7:0] product;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;

assign product[0] = in1[0]&in2[0];

HA HA1(product[1], x1, (in1[1]&in2[0]), (in1[0]&in2[1]));

FA FA1(x2, x3, (in1[1]&in2[1]), (in1[0]&in2[2]), x1);
FA FA2(x4, x5, (in1[1]&in2[2]), (in1[0]&in2[3]), x3);
HA HA2(x6, x7, (in1[1]&in2[3]), x5);
HA HA3(product[2], x15, x2, (in1[2]&in2[0]));
FA FA3(x9, x8, x7, (in1[2]&in2[3]), x17);
FA FA4(x13, x17, x6, (in1[2]&in2[2]), x16);
FA FA5(x14, x16, x4, (in1[2]&in2[1]), x15);
HA HA4(product[3], x12, x14, (in1[3]&in2[0]));
FA FA6(product[6], product[7], x8, (in1[3]&in2[3]), x10);
FA FA7(product[5], x10, x9, (in1[3]&in2[2]), x11);
 FA FA8(product[4], x11, x13, (in1[3]&in2[1]), x12);
endmodule

module HA(sout,cout,a,b);
input a,b;
output sout,cout;

assign sout = a^b;

assign cout = a&b;
endmodule

module FA(sout,cout,a,b,cin);
input a,b,cin;
output sout,cout;

assign sout = a^b^cin;

assign cout = (a&b)|(b&cin)|(cin&a);
endmodule

Testbench Code:

module multiplier_test;
reg [3:0] in1,in2;
wire [7:0] product;

multiplier_4x4 uut(.in1(in1), .in2(in2), .product(product));

initial
begin
in1 = 10;
in2 = 12;
#30;

in1 = 13;
in2 = 12;
#30;

in1 = 10;
in2 = 22;
#30;

in1 = 11;
 in2 = 22;
#30;

in1 = 12;
in2 = 15;
#30;

$finish;
end
endmodule

Schematic:

Timing Diagram:
Power Report:

Result:

Verilog code of 4*4 array multiplier is simulated and RTL schematic and power report was also
generated. The above code are successfully multiplied numbers like 10 and 12 etc.