IERG3060

Microcontrollers and
Embedded Systems

Part 10: Instructions

IERG3060 — Part 10 1
 Textbook and Reference

• “The Definitive Guide to the ARM ® Cortex-M3”

Second Edition

by Joseph Yiu

• ARM v7-M Architecture Application Level Reference Manual (ARM DDI

0405A-01)

IERG3060 — Part 10 2
 Outlines
• Assembly Basics
• List of Instruction
• Moving Data
• Processing Data
• Call and Unconditional Branch
• Decisions and Conditional Branches
• Conditional Execution Using IT Instructions
• More about Some Useful Instructions in CORTEX-M3

IERG3060 — Part 10 3
Assembly Basics

IERG3060 — Part 10 4
 Assembler Language: Basic
Syntax
• In assembler code, the following instruction formatting
is commonly used:

Label
Opcode Operand1, Operand2, … ; Comments

action Things to be acted upon

Example:

IERG3060 — Part 10 5
 Assembler Language: Use of
Suffixes
• Instructions can be followed immediately by suffixes.

Suffix Description
S Update Application Program Status register (APSR)
(flags); for example:

ADDS R0, R1 ; this will update APSR

EQ, NE, LT, GT, and Conditional execution; EQ = Equal, NE = Not Equal,
so on LT = Less Than, GT = Greater Than
For example:

BEQ <Label> ; Branch if equal

IERG3060 — Part 10 6
 Operand2 as a constant
Opcode Operand1, Operand2, … ; Comments

• The operand2 can be an immediate data (i.e., a constant).

• Some restriction on the possible number that can be used:
Operand2 occupies 12 bits ONLY. Other bits in a 32-bit instruction are used for
opcode and operand1.
• You can specify an Operand2 constant in the form:
#constant
• In ARM instructions, constants can have any value that can be produced
by rotating an 8-bit value right by any even number of bits within a 32-bit
word.
• In Thumb instructions, constants can be:
• any constant that can be produced by shifting an 8-bit number left by any
number of bits within a 32-bit word
• any constant of the form 0x00XY00XY
Q: Why such restriction?
• any constant of the form 0xXY00XY00
Q: What if we really want to have a
• any constant of the form 0xXYXYXYXY. specific number that is not listed here?
IERG3060 — Part 10 7
Unified Assembler Language (UAL)
• Unified Assembler Language (UAL) was developed to make it easier to
port applications between ARM code and Thumb code by using the same
syntax for both.
ADD R0, R1 ; R0 = R0 + R1, using Traditional Thumb syntax
ADD R0, R0, R1 ; Equivalent instruction using UAL syntax

• Traditional Thumb syntax can still be used. Use directive to differentiate

whether it is traditional Thumb code or the new UAL syntax. For example,
a program code header with
• “CODE16” directive implies the code is in the traditional Thumb syntax, and
• “THUMB” directive implies the code is in the new UAL syntax.
• Be careful when you reuse traditional Thumb: some instructions may
change the flags in APSR, even if the S suffix is not used. However, when
the UAL syntax is used, whether the instruction changes the flag depends
on the S suffix. For example,
AND R0, R1 ; Traditional Thumb syntax
ANDS R0, R0, R1 ; Equivalent UAL syntax (S suffix is added)

IERG3060 — Part 10 8
 Suffixes for 16-bit & 32-bit
instructions
• With Thumb-2 technology, some of the operations can be handled by
either a Thumb instruction or a Thumb-2 instruction. With UAL, you can
specify which instruction you want by adding suffixes.
• For example, R0 = R0 + 1 can be implemented by
ADDS R0, #1 ; Use 16-bit Thumb instruction by default
; for smaller size
ADDS.N R0, #1 ; Use 16-bit Thumb instruction (N=Narrow)
ADDS.W R0, #1 ; Use 32-bit Thumb-2 instruction (W=wide)

• The .W (wide) suffix specifies a 32-bit instruction. If no suffix is given, the

assembler tool can choose either instruction but usually defaults to 16-bit
Thumb code to get a smaller size.
• You may also use the .N (narrow) suffix to specify a 16-bit Thumb
instruction (depending on the tool support).

IERG3060 — Part 10 9
 16-bit & 32-bit instructions
• In most cases, applications will be coded in C, and the C compilers will
use 16-bit instructions if possible for its smaller code size.
• However, when the immediate data exceed a certain range or when the
operation can be better handled with a 32-bit Thumb-2 instruction, the 32-
bit instruction will be used.
• The 32-bit Thumb-2 instructions can be half word aligned. For example,
you can have a 32-bit instruction located in a half word location.

0x1000 : LDR r0,[r1] ; a 16-bit instruction (occupy 0x1000-0x1001)

0x1002 : RBIT.W r0 ; a 32-bit Thumb-2 instruction (occupy
; 0x1002-0x1005)

• Most of the 16-bit instructions can only access registers R0–R7; 32-bit
Thumb-2 instructions do not have this limitation. However, use of PC
(R15) might not be allowed in some of the instructions. (More information
available in ARM v7-M Architecture Application Level Reference Manual
section A4.6).

IERG3060 — Part 10 10
Instruction List

IERG3060 — Part 10 11
16-Bit Data Processing Instructions

IERG3060 — Part 10 12
16-Bit Data Processing Instructions (cont’d)

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16-Bit Branch Instructions

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16-Bit Load and Store Instructions

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Other 16-Bit Instructions

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 Instruction encoding for 16-bit Thumb
instructions
• Refer to DDI 0405A for other commands.
• Example: Shift by immediate and move (register).
• imm5  shift 0~31; Rm = source register; Rd = destination register

IERG3060 — Part 10 17
From DDI 0405A-01 page-65 (A4-3)
32-Bit Data Processing
Instructions

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32-Bit Data Processing
Instructions (cont’d)

IERG3060 — Part 10 19
32-Bit Data Processing
Instructions (cont’d)

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32-Bit Load and Store Instructions

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32-Bit Load and Store Instructions
(cont’d)

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32-Bit Branch Instructions

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Other 32-Bit Instructions

IERG3060 — Part 10 24
Unsupported Thumb Instructions
for Traditional ARM Processors

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Assembler
Language:
Moving Data

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Assembler Language: Moving Data
• In the Cortex-M3, data transfers (to or from a register) can be of
one of the following types:
• Moving data between register and register
• Moving data between memory and register
• Moving data between special register and register
• Moving an immediate data value into a register
• The command to move data between registers or set a register
with an immediate data (max 16 bits) is MOV (move). For
example, moving data from register R3 to register R8 looks like
this:
MOV R8, R3
• Another instruction can generate the negative value of the
original data; it is called MVN (move negative).

IERG3060 — Part 10 27
 Load and Store
• The basic instructions for accessing memory are Load and Store.
• Load (LDR) transfers data from memory to registers; and
• Store (STR) transfers data from registers to memory.

• The transfers can be in different data sizes (byte, half word, word,
and double word), as outlined in Table 4.14.
• Multiple Load and Store operations can be combined into single
instructions called LDM (Load Multiple) and STM (Store Multiple),
as outlined in Table 4.15.
• The exclamation mark (!) in the instruction specifies whether the
register Rd should be updated after the instruction is completed.
For example, if R8 = 0x8000:
STMIA.W R8!, {R0-R3} ; R8 changed to 0x8010 after
; store (increment by 4 words)
STMIA.W R8 , {R0-R3} ; R8 unchanged after store

IERG3060 — Part 10 28
Memory Access Instructions

Note here Rd
is the source

Note here Rd
is the address
of destination
29
 Preindexing and Postindexing
• ARM processors also support memory accesses with preindexing and
postindexing. For preindexing, the register holding the memory address is
adjusted first. The memory transfer then takes place with the updated
address. For example,

LDR.W R0, [R1, #offset]! ; Read memory[R1+offset], with R1

; update to R1+offset

IERG3060 — Part 10 30
 Preindexing and Postindexing
(cont’d)
• The use of the “!” indicates the update of base register R1.
• The “!” is optional; without it, the instruction would be just a normal
memory transfer with offset from a base address.
• The preindexing memory access instructions include load and
store instructions of various transfer sizes (see Table 4.16).
• The postindexing memory access instructions carry out the
memory transfer using the base address specified by the register
and then update the address register afterward. For example,

LDR.W R0,[R1], #offset ; Read memory[R1], with R1

; updated to R1+offset

IERG3060 — Part 10 31
 Preindexing and Postindexing
(cont’d)
• When a postindexing instruction is used, there is no need to use the “!”
sign, because all postindexing instructions update the base address
register, whereas in preindexing you might choose whether to update the
base address register or not.
• Similarly to preindexing, postindexing memory access instructions are
available for different transfer sizes (Table 4.17).

IERG3060 — Part 10 32
 Push and Pop

• Two other types of memory operation: stack PUSH and stack POP.
Q: Which one is pushed/popped first?
• For example,
PUSH {R0, R4-R7, R9} ; Push R0, R4, R5, R6, R7, R9 into
; stack memory
POP {R2, R3} ; Pop R2 and R3 from stack

• Cortex-M3 has a number of special registers. They can be accessed by the

instructions MRS and MSR. For example,
MRS R0, PSR ; Read Processor status word into R0
MSR CONTROL, R1 ; Write value of R1 into control register
• Unless you are accessing the APSR, you can only use MSR or MRS to access
other special registers in privileged mode.

IERG3060 — Part 10 33
 Moving immediate data into a
register
• You might want to access a peripheral register, so you need to put the
address value into a register beforehand.
1. For small values (<= 8 bits), you can use MOVS (move). For example,
MOVS R0, #0x12 ; Set R0 to 0x12
2. For a larger value (>8 bits but <=16 bits), you might need to use a
Thumb-2 move instruction. For example,
MOVW.W R0, #0x789A ; Set R0 to 0x789A
3. If the value is 32-bit, you can use two instructions to set the upper and
lower halves:
MOVW.W R0,#0x789A ; Set R0 lower half to 0x789A
MOVT.W R0,#0x3456 ; Set R0 upper half to 0x3456. Now
; R0=0x3456789A

(Or you can use a pseudo-instruction: LDR R0, =0x3456789A )

IERG3060 — Part 10 34
 LDR and ADR Pseudo-Instructions
• Both LDR and ADR pseudo-instructions can be used to set registers to a program
address value. They have different syntaxes and behaviors.
• For LDR, if the address is a program address value, the assembler will
automatically set the LSB to 1. For example,
LDR R0, =address1 ; R0 set to ?
...
address1 ; assume address 0x4001
here is 0x4000
MOV R0, R1 ; address1 contains program code
...
• You will find that the LDR instruction will put 0x4001 into R1; the LSB is set to 1 to
indicate that it is Thumb code. If address1 is a data address, LSB will not be
changed. For example,
LDR R0, =address1 ; R0 set to ?
...
address1 ; assume address 0x4000
here is 0x4000
DCD 0x0 ; address1 contains data
...
(Define Constant Data (DCD): to define a word size constant value in your code)

IERG3060 — Part 10 35
LDR and ADR Pseudo-Instructions
(cont’d)
• For ADR, you can load the address value of a program code into a
register without setting the LSB automatically. For example,

ADR R0, address1

...
address1 ; assume address here is 0x4000
MOV R0, R1 ; address1 contains program code
...

• You will get 0x4000 in the ADR instruction.

• Note that there is no equal sign (=) in the ADR statement.

IERG3060 — Part 10 36
LDR and ADR Pseudo-Instructions
(cont’d)
• LDR obtains the immediate data by putting the data in the
program code and uses a PC relative load to get the data into the
register.
• ADR tries to generate the immediate value by adding or
subtracting instructions (for example, based on the current PC
value). As a result, it is not possible to create all immediate values
using ADR, and the target address label must be in a close range
(cons). However, using ADR can generate smaller code sizes
compared with LDR (pros).
• The 16-bit version of ADR requires that the target address must be
word aligned (address value is a multiple of 4). If the target
address is not word aligned, you can use the 32-bit version of
ADR instruction “ADR.W.”
• If the target address is more than ±4095 bytes of current PC, you
can use “ADRL” pseudo-instruction, which gives ±1 MB range.

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 Assembler
Language:
Processing Data

IERG3060 — Part 10 38
 ADD
• ADD instruction can operate between two registers or between one
register and an immediate data value:
ADD R0, R0, R1 ; R0 = R0 + R1
ADDS R0, R0, #0x12 ; R0 = R0 + 0x12
ADD.W R0, R1, R2 ; R0 = R1 + R2

• These are all ADD instructions, but they have different syntaxes and
binary coding.
• With the traditional Thumb instruction syntax, when 16-bit Thumb code is
used, an ADD instruction can change the flags in the PSR. However, 32-
bit Thumb-2 code can either change a flag or keep it unchanged. To
separate the two different operations, the S suffix should be used if the
following operation depends on the flags:
ADD.W R0, R1, R2 ; Flag unchanged
ADDS.W R0, R1, R2 ; Flag changed
• Table 4.18 shows some of the most commonly used arithmetic
instructions.

IERG3060 — Part 10 39
Examples of Arithmetic Instructions

IERG3060 — Part 10 40
 “S” Suffix and Multiply
• “S” suffix can be used to determine if the APSR should be
updated.
• In most cases, if UAL syntax is selected and if “S” suffix is not
used, the 32-bit version of the instructions would be selected as
most of the 16-bit Thumb instructions update APSR.
• The Cortex-M3 also supports 32-bit multiply instructions and
multiply accumulate instructions that give 64-bit results. These
instructions support signed or unsigned values (see Table 4.19).

IERG3060 — Part 10 41
 Logic Operation
• Another group of data processing instructions are the logical operations
instructions and logical operations such as AND, ORR (or), and shift and
rotate functions.
• “S” suffix can be used to determine if the APSR should be updated. If
UAL syntax is used and if “S” suffix is not used, the 32-bit version of the
instructions would be selected as all of the 16-bit logic operation
instructions update APSR.

IERG3060 — Part 10 42
 Shift and Rotate Instructions
• Shift and rotate instructions are shown below (Table 4.21). In some
cases, the rotate operation can be combined with other operations (for
example, in memory address offset calculation for load/store instructions).
• Again, a 32-bit version of the instruction is used if “S” suffix is not used
and if UAL syntax is used.

Q: Why is there ROTATE RIGHT but no ROTATE LEFT?

IERG3060 — Part 10 43
 Shift and Rotate Instructions
(cont’d)
• In UAL syntax, the rotate
and shift operations can
also update the carry flag
if the S suffix is used (and
always update the carry
flag if the 16-bit Thumb
code is used). See Figure
4.1.
• If the shift or rotate
operation shifts the register
position by multiple bits,
the value of the carry flag
C will be the last bit that
shifts out of the register.

IERG3060 — Part 10 44
 Sign Extend Instruction
• For conversion of signed data from byte or half word to
word, the Cortex-M3 provides the two instructions
shown in Table 4.22.
• Both 16-bit and 32-bit versions are available. The 16-
bit version can only access low registers.

IERG3060 — Part 10 45
 Reversing Data Bytes

• Another group of data processing

instructions is used for reversing
data bytes in a register (Table
4.23).
• These instructions are usually
used for conversion between little
endian and big endian data.
• Both 16-bit and 32-bit versions
are available. The 16-bit version
can only access low registers.

IERG3060 — Part 10 46
 Bit Field Processing
• The last group of data processing instructions is for bit field
processing (Table 4.24).
LDR R0, =0x1234FFFF
BFC R0, #4, #8 ; Clear R0[13:4] (8 bits)
; R0 = 0x1234F00F
LDR R0, =0x12345678
LDR R1, =0x3355AACC
BFI R1, R0, #8, #16 ; Insert R0[15:0] (16 bits)
; to R1[23:8]. R1 = 0x335678CC

IERG3060 — Part 10 47
Assembler Language:
Call and Unconditional
Branch

IERG3060 — Part 10 48
 Unconditional branch
• The most basic branch instructions are as follows:
B label ; Branch to a labeled address
BX reg ; Branch to an address specified by
; a register

• In BX instructions, the LSB of the value contained in the register

determines the next state (Thumb/ARM) of the processor.
• In the Cortex-M3, because it is always in Thumb state, this bit
should be set to 1. If it is zero, the program will cause a usage
fault exception because it is trying to switch the processor into
ARM state.

IERG3060 — Part 10 49
 Call a function
• To call a function, the branch and link instructions should be used.
BL label ; Branch to a labeled address and
; save return address in LR
BLX reg ; Branch to an address specified by
; a register and save return
; address in LR.

• With these instructions, the return address will be stored in the link
register (LR) and the function can be terminated using BX LR,
which causes program control to return to the calling process.
• However, when using BLX, make sure that the LSB of the register
is 1. Otherwise the processor will produce a fault exception
because it is an attempt to switch to the ARM state.

IERG3060 — Part 10 50
 Branch using MOV and LDR
• You can also carry out a branch operation using MOV instructions
and LDR instructions. For example,
MOV R15, R0 ; Branch to an address in R0
LDR R15, [R0] ; Branch to an address in
; memory location specified
; by R0
POP {R15} ; Do a stack pop operation,
; and change the program
; counter value to the popped
; result.

• When using these methods to carry out branches, you also need
to make sure that the LSB of the new program counter value is
0x1. Otherwise, a usage fault exception will be generated.

IERG3060 — Part 10 51
Nested Subroutine

IERG3060 — Part 10 52
Assembler Language:
Decisions and
Conditional Branches

IERG3060 — Part 10 53
 Condition branch using flag
• Use flags in the APSR register to determine whether a branch should be
carried out.
• APSR flag bits:
• four of them, N, Z, C and V, are used for branch decisions (see Table 4.25).
• another one, Q flag (bit[27]) is for saturation math operations and is not used for
conditional branches.
• With combinations of the four flags, 15 branch conditions are defined (see
Table 4.26). Using these conditions, branch instructions can be written as, for
example,
BEQ label ; Branch to address 'label' if Z flag is set
• You can also use the Thumb-2 version if your branch target is further away.
For example,
BEQ.W label ; Branch to address 'label' if Z flag is set

IERG3060 — Part 10 54
Conditions for Branches and
Conditional Operations

IERG3060 — Part 10 55
 Condition branch using IF-THEN-
ELSE
• Also IF-THEN-ELSE structures can be used for condition branch.
• For example,
CMP R0, R1 ; Compare R0 and R1
ITTEE GT ; Check if R0 > R1,
; if true, the first 2 lines
; execute (THEN)
; if false, the other 2 lines
; execute (ELSE)
MOVGT R2, R0 ; (THEN) R2 = R0
MOVGT R3, R1 ; (THEN) R3 = R1
MOVLE R2, R1 ; (ELSE) R2 = R1
MOVLE R3, R0 ; (ELSE) R3 = R0

IERG3060 — Part 10 56
 How flag bits are changed?
• APSR flags can be affected by the following:
• Most of the 16-bit ALU instructions
• 32-bit (Thumb-2) ALU instructions with the S suffix; for example,
ADDS.W
• Compare (e.g., CMP) and Test (e.g., TST, TEQ)
• Write to APSR/xPSR directly

• Most of the 16-bit Thumb arithmetic instructions affect the N, Z, C, and V

flags.
• For 32-bit Thumb-2 instructions, the ALU operation can either change
flags or not change flags. For example,
ADDS.W R0, R1, R2 ; This 32-bit Thumb instruction
; updates flag
ADD.W R0, R1, R2 ; This 32-bit Thumb instruction
; does not update flag

IERG3060 — Part 10 57
 How flag bits are changed by
CMP and CMN?
• The compare (CMP) instruction subtracts two values and updates the
flags (just like SUBS), but the result is not stored in any registers. CMP
can have the following formats:
CMP R0, R1 ; Calculate R0–R1 and update flag
CMP R0, #0x12 ; Calculate R0–0x12 and update flag

• A similar instruction is the CMN (compare negative). It compares one

value to the negative (two’s complement) of a second value; the flags are
updated, but the result is not stored in any registers:
CMN R0, R1 ; Calculate R0–(-R1) and update flag
CMN R0, #0x12 ; Calculate R0–(-0x12) and update flag

IERG3060 — Part 10 58
How flag bits are changed by TST?
• The TST (test) instruction is more like the AND
instruction.
• It ANDs two values and updates the flags. However,
the result is not stored in any register. Similarly to CMP,
it has two input formats:
TST R0, R1 ; Calculate R0 AND R1 and update flag
TST R0, #0x12 ; Calculate R0 AND 0x12 and update flag

IERG3060 — Part 10 59
 CBZ and CBNZ
• With ARM architecture v7-M, two new instructions are provided on the
Cortex-M3 to supply a simple compare with zero and conditional branch
operations: CBZ (compare and branch if zero) and CBNZ (compare and
branch if nonzero).
• The APSR value is NOT affected by the CBZ and CBNZ instructions.
• The compare and branch instructions only support forward branches. For
example,
i = 5;
while (i != 0 ){
func1(); // call a function
i−−;
}
• This can be compiled into the following:
MOV R0, #5 ; Set loop counter
loop1 CBZ R0,loop1exit ; if loop counter = 0
; then exit the loop
BL func1 ; call a function
SUB R0, #1 ; loop counter decrement
B loop1 ; next loop
loop1exit

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Assembler Language:
Conditional Execution
Using IT Instructions

IERG3060 — Part 10 61
 IF-THEN block
• The IT (IF-THEN) block is very useful for
handling small conditional code.
• It avoids branch penalties because there is no
change to program flow (so what is the
implication for instruction queue?).
• It can provide a maximum of four conditionally
executed instructions. Example: ITTE, ITTEE,
ITEEE, …

IERG3060 — Part 10 62
 IF-THEN
• The IF-THEN (IT) instructions allow up to four
succeeding instructions (called an IT block) to be
conditionally executed.

• E.g. IT, ITE, ITET, ITETT

IERG3060 — Part 10 63
 IF-THEN vs. Branch
• (IF-THEN): Just skip a few commands (that meet or do
not meet the condition)
Advantage: no need to flush the instruction pipeline.
• (Branch): In executing a branch instruction, the pipeline
will be flushed. The processor will have to fetch
instructions from the branch destination to fill up the
pipeline again.

Branch: If condition is met, implement the “do” part.

Otherwise, skip that part.
if () {
// do ...
} do (then)

IERG3060 — Part 10 64
 IT Block
• IT command is always written as ITxyz, where x, y, and z can be T
(THEN) or E (ELSE).
• The first statement after the IT command must be TRUE-THEN-
EXECUTE.
• The second to fourth statements can be either THEN (true) or ELSE
(false):

IT<x><y><z> <cond> ; IT instruction (<x>, <y>,

; <z> can be T or E)
instr1<cond> <operands> ; 1st instruction (<cond>
; must be same as IT)
instr2<cond or not cond> <operands> ; 2nd instruction (can be
; <cond> or <!cond>
instr3<cond or not cond> <operands> ; 3rd instruction (can be
; <cond> or <!cond>
instr4<cond or not cond> <operands> ; 4th instruction (can be
; <cond> or <!cond>

IERG3060 — Part 10 65
 IT Block (cont’d)
• If a statement is to be executed when <cond> is false, the suffix for the
instruction must be the opposite of the condition. For example, the
opposite of EQ is NE, the opposite of GT is LE, etc.
• Example:
if (R1<R2) then
R2=R2−R1
R2=R2/2
else
R1=R1−R2
R1=R1/2

• In assembly,
CMP R1, R2 ; If R1 < R2 (less than)
ITTEE LT ; then execute instruction 1 and 2
; (indicated by T)
; else execute instruction 3 and 4
; (indicated by E)
SUBLT.W R2, R1 ; 1st instruction
LSRLT.W R2, #1 ; 2nd instruction
SUBGE.W R1, R2 ; 3rd instruction (notice the GE is
; opposite of LT)
LSRGE.W R1, #1 ; 4th instruction

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 Exception during IT Block
• You can have fewer than four conditionally executed instructions.
The minimum is 1. Make sure the number of T and E occurrences
in the IT instruction matches the number of conditionally executed
instructions after the IT.
• Q:
• What if an exception occurs during the IT instruction block?
• A:
• The execution status of the block will be stored in the stacked PSR
(in the IT/Interrupt-Continuable Instruction [ICI] bit field). So, when
the exception handler completes and the IT block resumes, the rest
of the instructions in the block can continue the execution correctly.
• In the case of using multicycle instructions (for example, multiple load
and store) inside an IT block, if an exception takes place during the
execution, the whole instruction is abandoned, and will be restarted
after the interrupt process is completed.

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IT Block Examples

IERG3060 — Part 10 68
 Automatic IT Insertion
• IT instruction also helps porting assembly application codes from
ARM7TDMI to Cortex-M3.
• When ARM assembler (including KEIL RealView Microcontroller
Development Kit) is used, and if a conditional execution instruction is
used in assembly code without IT instruction, the assembler can insert
the required IT instruction automatically.
• An example is shown in Table 4.33. This feature allows existing assembly
code to be reused on Cortex-M3 without modifications.

• Note that 16-bit data processing instructions does not update APSR if
they are used inside an IT instruction block. If you add the S suffix in the
conditional executed instruction, the 32-bit version of the instruction would
be used by the assembler.

IERG3060 — Part 10 69
More About Some
Useful Instructions
in CORTEX-M3

IERG3060 — Part 10 70
 MSR and MRS
• Two instructions provide access to the special registers in the Cortex-M3.
Here is the syntax of these instructions:
MRS <Rn>, <SReg> ; Move from Special Register
MSR <SReg>, <Rn> ; Write to Special Register
where <SReg> could be one of the options shown in Table 4.31.

• For example, the following code can be used to set up the process stack
pointer:
LDR R0,=0x20008000 ; new value for Process Stack
; Pointer (PSP)
MSR PSP, R0
• Unless accessing the APSR, the MRS and MSR instructions can be used
in privileged mode only. Otherwise the operation will be ignored, and the
returned read data (if MRS is used) will be zero.
• After updating the value of the CONTROL register using MSR instruction,
it is recommended to add an ISB (Instruction synchronization barrier)
instruction to ensure that the effect of the update takes place immediately.
On the Cortex-M3 processor this is not strictly required, but for software
portability (if the software code is to be used on other ARM processor)
this is needed. IERG3060 — Part 10 71
 SDIV and UDIV
• The syntax for signed and unsigned divide instructions is as
follows:
SDIV.W <Rd>, <Rn>, <Rm>
UDIV.W <Rd>, <Rn>, <Rm>

• The result is Rd = Rn/Rm. For example,

LDR R0, =300 ; Decimal 300
MOV R1, #5
UDIV.W R2, R0, R1
• This will give you an R2 result of 60 (0x3C).
• You can set up the DIVBYZERO bit in the NVIC Configuration
Control Register so that when a divide by zero occurs, a fault
exception (usage fault) takes place. Otherwise, <Rd> will become
0 if a divide by zero takes place.

IERG3060 — Part 10 72
 REV, REVH, and REVSH
• REV reverses the byte order in a data word, and REVH reverses
the byte order inside a half word. For example, if R0 is
0x12345678, in executing the following:
REV R1, R0
REVH R2, R0

• R1 will become 0x78563412, and R2 will be 0x34127856. REV

and REVH are particularly useful for converting data between big
endian and little endian.
• REVSH is similar to REVH except that it only processes the lower
half word, and then it sign extends the result. For example, if R0 is
0x33448899, running:
REVSH R1, R0
• R1 will become 0xFFFF9988.

IERG3060 — Part 10 73
 Reverse Bit
• The RBIT instruction reverses the bit order in a data word. The
syntax is as follows:
RBIT.W <Rd>, <Rn>

• This instruction is very useful for processing serial bit streams in

data communications. For example, if R1 is 0xB4E10C23 (binary
value 1011_0100_1110_0001_0000_1100_0010_0011),
executing:
RBIT.W R0, R1
• R0 will become 0xC430872D (binary value
1100_0100_0011_0000_1000_0111_0010_1101).

IERG3060 — Part 10 74
 SXTB, SXTH, UXTB, and UXTH
• The four instructions SXTB, SXTH, UXTB, and UXTH are used to
extend a byte or half word data into a word. The syntax of the
instructions is as follows:
SXTB <Rd>, <Rn>
SXTH <Rd>, <Rn>
UXTB <Rd>, <Rn>
UXTH <Rd>, <Rn>

• For SXTB/SXTH, the data are sign extended using bit[7]/bit[15] of

Rn. With UXTB and UXTH, the value is zero extended to 32-bit.
• For example, if R0 is 0x55AA8765:
SXTB R1, R0 ; R1 = 0x00000065
SXTH R1, R0 ; R1 = 0xFFFF8765
UXTB R1, R0 ; R1 = 0x00000065
UXTH R1, R0 ; R1 = 0x00008765

IERG3060 — Part 10 75
 UBFX and SBFX
• UBFX and SBFX are the unsigned and signed bit field extract
instructions. The syntax of the instructions is as follows:
UBFX.W <Rd>, <Rn>, <#lsb>, <#width>
SBFX.W <Rd>, <Rn>, <#lsb>, <#width>
• UBFX extracts a bit field from a register starting from any location
(specified by #lsb) with any width (specified by #width), zero
extends it, and puts it in the destination register. For example,
LDR R0, =0x5678ABCD
UBFX.W R1, R0, #4, #8
• This will give R1 = 0x000000BC.

• Similarly, SBFX extracts a bit field, but its sign extends it before
putting it in a destination register. For example,
LDR R0,=0x5678ABCD
SBFX.W R1, R0, #4, #8
• This will give R1 = 0xFFFFFFBC.
IERG3060 — Part 10 76
 LDRD and STRD
• The two instructions LDRD and STRD transfer two words of data
from or into two registers. The syntax of the instructions is as
follows:
LDRD.W <Rxf>, <Rxf2>, [Rn, #+/−offset]{!}
; Pre-indexed
LDRD.W <Rxf>, <Rxf2>, [Rn], #+/−offset
; Post-indexed
STRD.W <Rxf>, <Rxf2>, [Rn, #+/−offset]{!}
; Pre-indexed
STRD.W <Rxf>, <Rxf2>, [Rn], #+/−offset
; Post-indexed
where <Rxf> is the first destination/source register and <Rxf2> is
the second destination/source register.

• Avoid using same register for <Rn> and <Rxf> when using
LDRD because of an erratum in Cortex-M3 revision 0 to 2.

IERG3060 — Part 10 77
 LDRD and STRD (cont’d)
• For example, the following code reads a 64-bit value located in
memory address 0x1000 into R0 and R1:
LDR R2, =0x1000 ; Base address
LDRD.W R0, R1, [R2]
; This will gives R0 = memory[0x1000],
; R1 = memory[0x1004]

• Similarly, we can use STRD to store a 64-bit value in memory. In

the following example, pre-indexed addressing mode is used:
LDR R2, =0x1000 ; Base address
STRD.W R0, R1, [R2, #0x20]
; This will gives memory[0x1020] = R0,
; memory[0x1024] = R1

IERG3060 — Part 10 78