The Simplified Instructional Computer

(SIC )
• SIC comes in two versions
– The standard model
– An XE version - “extra equipments” , “extra expensive”
• These two versions has been designed to be
upward compatible
• An object program for the standard SIC will also
execute properly on a SIC/XE system
 SIC Machine Architecture
• Memory
– 1 byte = 8-bit
– 1 word=3 consecutive bytes
– Addressed by the location of their lowest numbered byte
– Total 32,768 (2^15) bytes SIC does not have any stack.
It uses the linkage register to store the
– Memory is byte addressable return address.
It is difficult to write the recursive
program.
Registers- Five registers (24 bits in length) A programmer has to maintain memory
for return addresses when we write
Mnemonic Number Special use
more than one layer of function call.
A 0 Accumulator - used for arithmetic operations
X 1 Index Register- used for addressing
L 2 Linkage register- the Jump to Subroutine (JSUB) instruction stores the
return address in this register
PC 8 Program Counter - contains the address of the next instruction to be
fetched for execution
SW 9 Status Word - contains a variety of information, including a Condition Code (CC)
 SIC Machine Architecture
• Data Formats
 Integers: stored as 24-bit binary numbers;
2’s complement representation is used for negative values
 Characters: stored as 8-bit ASCII codes
 No floating-point hardware N ⇔ 2^n – N
Eg : if n = 4, -1 ⇔
• Instruction Formats - standard version of SIC 2^4 – 1 = (1111)2.

The flag bit x is used to indicate indexed-addressing mode

• Addressing Modes
– There are two addressing modes available
– Indicated by the setting of x bit in the instruction
Find EA corresponding to following instructions. Assume (X)= 2500
1) 3A6452 2) 92B800 3) 777777

001110100110010001010010

3 A 6 4 5 2

OP CODE 6452
X

EA=15 bit address = 6452

100100101011100000000000

9 2 B 8 0 0

OP CODE 3800
X

EA=15 bit address +(X)= 3800+2500=5D00

Find EA corresponding to following instructions. Assume (X)= 2500
1) 3A6452 2) 92B800 3) 777777

011101110111011101110111

7 7 7 7 7 7

OP CODE 7777
X

EA=15 bit address+ (X)= 6452+7777=DBC9

 ADD
SUB
Instruction set
MUL
Classified into 7 Categories LDA
DIV LDCH
1. Load and Store Instructions
LDL
Involve 2. Arithmetic Instruction LDX
AND
register A
and a word 3. Logical Instruction OR STA
in memory
4. Compare Instruction J
STCH
STL
COMP 5. Jump Instruction JEQ
STSW
involves 6. Subroutine handling Instruction JGT
STX
register A
JLT
and a word 7. I/O instruction TD
in memory tests whether the
save result WD addressed device is
in condition ready to send or receive
code (CC) of JSUB RD a byte of data
SW CC : < : ready
RSUB
CC : = : busy
 Load and Store Instructions
MNEMONIC OPERAND OPCODE EXPLANATION

LDA M 00 A=M
LDCH M 50 A[RMB] = [RMB]
LDL M 08 L=M
LDX M 04 X=M

STA M 0C M=A
STCH M 54 M[RMB] = A[RMB]
STL M 14 M=L
STSW M E8 M = SW
STX M 10 M=X

Notations used
A - Accumulator M - Memory CC - Condition Code
PC - Program Counter RMB - Right Most Byte L - Linkage Register
 Arithmetic and Logical Instruction
MNEMONIC OPERAND OPCODE EXPLANATION
ADD M 18 A=A+M
SUB M 1C A=A–M
MUL M 20 A=A*M
DIV M 24 A=A/M

Logical Instruction
AND M 40 A = A AND M
OR M 44 A = A OR M

Compare Instruction
COMP M 28 compares A and M
X=X+1;
TIX M 2C
compare X with M

Notations used
A - Accumulator M - Memory CC - Condition Code
 Jump Instructions
MNEMONIC OPERAND OPCODE EXPLANATION

J M 3C PC = M

JEQ M 30 if CC set to =, PC = M

JGT M 34 if CC set to >, PC = M

JLT M 38 if CC set to <, PC = M

Subroutine handling Instructions

JSUB M 48 L = PC ; PC = M

RSUB 4C PC = L

Notations used
A - Accumulator M - Memory CC - Condition Code
PC - Program Counter RMB - Right Most Byte L - Linkage Register
 I/O instructions
MNEMONIC OPERAND OPCODE EXPLANATION
TD M E0 test device specified by M
WD M DC device specified by M[RMB] = S[RMB]
RD M D8 A[RMB] = data specified by M[RMB]

I/O operation is performed by transferring 1 byte at a time from or to rightmost 8 bits

of accumulator.
Each device has 8 bit unique code (Device Address)
There are 3 I/O instructions:
Test Device (TD) tests whether device is ready or not. Condition code in Status Word
Register is used for this purpose. If cc is < then device is ready otherwise device is busy.
Read data(RD) reads a byte from device and stores in register A.
Write data(WD) writes a byte from register A to the device.

Notations used
A - Accumulator M - Memory CC - Condition Code
PC - Program Counter RMB - Right Most Byte L - Linkage Register
 Assembler Directives
Pseudo-Instructions
Not translated into machine instructions
Providing information to the assembler
 Syntax ADDRESS MEMORY
Label START value 0000 ---
0001 ---
Label BYTE value
: :
Label WORD value 1 BYTE
EOF 2A56 E FOR
Label RESB value 2A57 O
EACH
CHARACT
Label RESW value 2A58 F
ER

: :
Label: name of operand FIVE 3000 05
value: integer, character 3001 00 3
3002 00 BYTES
: :
Eg. EOF BYTE C’EOF’
DATA1 3100 --- 3X4=
B1 BYTE X’4156’ 12
: ---
FIVE WORD 5 310B ---
BYTES
DATA1 RESW 4 DATA1 310C ---
DATA2 RESB 5 : --- 5
BYTES
3110 ---
 Assume that to memory location named FIVE and CHARX
contains data 5 and ‘Z’ respectively. Write sequence of
statement to transfer content of location FIVE and CHARZ to
location ALPHA and C1 respectively
START 1000
1000 LDA FIVE load 5 into A
1003 STA ALPHA store in ALPHA
1006 LDCH CHARZ load ‘Z’ into A
1009 STCH C1 store in C1
100C RSUB

ALPHA 100F RESW 1 reserve one word space

FIVE 1012 WORD 5 one word holding 5
CHARZ 1015 BYTE C’Z’ one-byte constant
C1 1016 RESB 1 one-byte variable
1017 END
 Arithmetic operations: BETA = ALPH +INCR-1
PG1 START
0000 LDA ALPH
0003 ADD INCR
0006 SUB ONE
0009 STA BETA
000C RSUB
000F ONE WORD 1 one-word constant
0012 ALPH RESW 1 one-word variables
0015 BETA RESW 1
0018 INCR RESW 1
001B END
To copy a 11 byte string from one location to another

LDX ZERO Initializes X to zero.

MOVECH LDCH STR1,X X specifies indexing.
STCH STR2,X
TIX ELEVEN Increments X and compares with 11.
JLT MOVECH
RSUB
STR1 BYTE C’TEST STRING’ String constant.
STR2 RESB 11
ELEVEN WORD 11
ZERO WORD 0
 • SUBROUTINE TO READ 100-BYTE RCORD
START 1000
READ LDX ZERO INITAILIZE INDEX REGISTER TO 0
RLOOP TD INDEV TEST INPUT DEVICE
JEQ RLOOP LOOP IF DEVICE IS BUSY
RD INDEV READ ONE BYTE INTO REGISTER A
STCH RECORD,X STORE DATA BYTE INTO RECORD
TIX K100 ADD 1 TO INDEX AND COMPARE TO 100
JLT RLOOP LOOP IF INDEX IS LESS THAN 100
RSUB EXIT FROM SUBROUTINE

ZERO WORD 0
K100 WORD 100 INPUT DEVICE NUMBER
INDEV BYTE X’F1’ 100-BYTE BUFFER FOR INPUT RECORD
RECORD RESB 100 ONE-WORD CONSTANTS
END
 LDA ZERO
STA INDEX GAMMA(I)=ALPHA[I]+BETA[I]

LOOP1 LDA INDEX

LDA ALPHA,X
ADD BETA,X
STA GAMMA,X ALPHA RESW 100

LDA INDEX BETA RESW 100

GAMMA RESW 100
ADD THREE
END
STA INDEX
COMP D300
JLT LOOP1
:
:
INDEX RESW 1
ZERO WORD 0
D300 WORD 300
THREE WORD 3
 SIC/XE
Memory
• Almost the same as that previously described for SIC Byte organized
WORD
• However, 1 MB maximum memory available
Registers Registers common to SIC and
SIC/XE
•More registers are provided by SIC/XE
A 0
X 1
L 2
PC 8
SW 9

Data Formats
The same data format as the standard version
However, provide an addition 48-bit floating-point data type
• fraction: between 0 and 1
• exponent: Value between 0 to2047
• sign: 0=positive, 1=negative
• Instruction formats
- Since the memory used by SIC/XE may be 2^20 bytes, the
instruction format of SIC is not enough.
Solutions
– Use relative addressing
– Extend the address field to 20 bits
SIC/XE instruction formats
Addressing Modes
Addressing Modes: Address Computation
Addressing Modes: Address Computation
Addressing Modes: Address Computation
Addressing Modes: Address Computation
Find EA corresponding to following instructions. Assume (X)= 2500
1) 17202D 2) 92B800 3) 777777

000101110010000000101101
1 7 2 0 2 D
OPCODE n i x b p e
Displacement 02 D
Assume (PC) = 3
OPCODE=00010100=14
Format = 3
n i = 1 1 (DIRECT ADDRESS)
P=1
EA= (PC)+ Displacement
=003+02D=0030
http://cis.csuohio.edu/~jackie/cis335/sicxe_address.txt

27