Post lab [Top sheet]

Course code: EEE 205 Sec: 01

Exp. No.: 03

Exp. Name: Verilog Simulation of Combinational Logic Circuits

Md. Kaowsar Peda

St. Name:

2023-1-80-017
St. ID:

07
Group no:

Partners’ IDs (1) 2023-1-80-016

(2) 2023-1-80-072

Date of 21 August, 2024 Instructor’s Comment

performance and Signature:

Date of 30 August, 2024

submission
NAME OF THE EXPERIMENT: Verilog Simulation of Combinational Logic Circuits.

OBJECTIVE: The objective of this experiment is to learn the simulation of combinational logic
circuits.
There are 4 ways to simulate combinational logic circuits:
1. Structural Verilog simulation at primitive gate level
2. Behavioral Verilog simulation using procedural model
3. Behavioral Verilog simulation using continuous assign statement model

THEORY: Verilog is a Hardware Description Language (HDL), which is used for describing a
digital system like a network switch or a microprocessor or a memory or a flip−flop. It means, by
using an HDL we can describe any digital hardware at any level. Designs, which are described in
HDL are independent of technology, very easy for designing and debugging, and are normally
more useful than schematics, particularly for large circuits.

ABASTRACT:

This experiment investigates the simulation of combinational logic circuits through the use of
Verilog, a hardware description language widely adopted for digital design and verification.
Combinational logic circuits, characterized by their output being a function solely of the current
inputs without memory elements, serve as fundamental components in digital systems.

In this study, various combinational logic circuits, such as adders, multiplexers, and encoders, are
designed and simulated using Verilog. The experiment covers the entire design cycle, including
the creation of Verilog modules, the specification of input-output relationships, and the application
of testbenches to validate functionality.

INTRODUCTION:

Combinational logic circuits form the backbone of digital electronic systems, where their
fundamental characteristic is that the output is a direct function of the present input values, with
no dependence on past states. These circuits include essential building blocks like adders,
multiplexers, and encoders, which are pivotal in performing arithmetic operations, data selection,
and data encoding, respectively.

The design and verification of combinational logic circuits are crucial steps in developing reliable
and efficient digital systems. Verilog, a high-level hardware description language (HDL), plays a
significant role in this process by allowing designers to describe and simulate digital circuits in a
textual format. Verilog provides a structured approach to specify both the functionality and
behavior of combinational logic circuits, enabling designers to test and validate their designs
before physical implementation.
This experiment focuses on leveraging Verilog to design, simulate, and analyze combinational
logic circuits. The primary goals of the experiment are to:
1. Understand Verilog Fundamentals.
2. Design Combinational Circuits.
3. Simulate Circuit Behavior.
4. Debug and Analyze.

By engaging in this experiment, we will develop a deeper understanding of digital design

principles, gain practical experience with Verilog for combinational logic circuit design, and learn
how simulation can facilitate the verification and validation of digital systems. This foundational
knowledge is essential for advancing to more complex digital design challenges and integrating
combinational logic circuits into larger systems.

Report Questions answer:

1. The truth table and the combinational logic circuit of the Boolean expression are given
below:
The Boolean expression is A′B + AC + AB′

Truth table of this Boolean expression:

A B C A′ B′ A′B AC AB′ A′B+AC+AB′

0 0 0 1 1 0 0 0 0

0 0 1 1 1 0 0 0 0

0 1 0 1 0 1 0 0 1

0 1 1 1 0 1 0 0 1

1 0 0 0 1 0 0 1 1

1 0 1 0 1 0 1 1 1

1 1 0 0 0 0 0 0 0

1 1 1 0 0 0 1 0 1
Circuit diagram of this Boolean expression is:

2. Testbench:

module tb_boolean_expr;

// Testbench signals
reg A;
reg B;
reg C;
wire Y;

// Instantiate the module under test

boolean_expr uut (
.A(A),
.B(B),
.C(C),
.Y(Y)
);

// Initialize inputs and apply test cases

initial begin
// Monitor changes
$monitor("A=%b B=%b C=%b | Y=%b", A, B, C, Y);

// Apply test cases

A = 0; B = 0; C = 0; #10;
A = 0; B = 0; C = 1; #10;
 A = 0; B = 1; C = 0; #10;
A = 0; B = 1; C = 1; #10;
A = 1; B = 0; C = 0; #10;
A = 1; B = 0; C = 1; #10;
A = 1; B = 1; C = 0; #10;
A = 1; B = 1; C = 1; #10;

// End simulation
$finish;
end

initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule

a) Structural Verilog simulation at primitive gate level:

module boolean_expr (
input wire A,
input wire B,
input wire C,
output wire Y
);

// Intermediate signals
wire not_A;
wire not_B;
wire and1;
wire and2;
wire and3;

// NOT gates
 not (not_A, A); // not_A = A'
not (not_B, B); // not_B = B'

// AND gates
and (and1, not_A, B); // and1 = A'B
and (and2, A, C); // and2 = AC
and (and3, A, not_B); // and3 = AB'

// OR gate
or (Y, and1, and2, and3); // Y = A'B + AC + AB'

endmodule
Simulation file:
 b) Behavioral Verilog simulation using procedural model:

module boolean_expr (
input wire A,
input wire B,
input wire C,
output wire Y
);

// Behavioral description using continuous assignment

assign Y = (~A & B) | (A & C) | (A & ~B);

endmodule
Simulation file:
c) Behavioral Verilog simulation using continuous assign statement model:

module boolean_expr (
input wire A,
input wire B,
input wire C,
output wire Y
);

// Continuous assignment to directly describe the Boolean expression

assign Y = (~A & B) | (A & C) | (A & ~B);

endmodule

Simulation file:
3. Compare the results of all the aforementioned methods with your prepared truth
Table:
To compare the results of the Boolean expression A′B+AC+AB′ from various Verilog models with
the truth table, that we created post lab question 1. This table will list all possible combinations
of the inputs A, B, and C and show the corresponding output Y.
Verilog Code Verification: To verify the correctness of the behavioral and structural Verilog
implementations, we simulated each model using the provided testbench. The results from these
simulations should match the truth table values.
1. Behavioral Verilog Model:
The procedural model and continuous assign statement model assign Y = A′B + AC + AB′ in the
behavioral Verilog code should match the results in the truth table when simulated with the
testbench.
2. Structural Verilog Model:
The structural Verilog model uses gates to construct the expression. Given the truth table, we
should ensure that the results from the simulation of this model also match the truth table.
Simulated Results:
Using the testbench provided in the previous messages, we should see the following output:
For A = 0, B = 0, C = 0: Y = 0
For A = 0, B = 0, C = 1: Y = 0
For A = 0, B = 1, C = 0: Y = 1
For A = 0, B = 1, C = 1: Y = 1
For A = 1, B = 0, C = 0: Y = 1
For A = 1, B = 0, C = 1: Y = 1
For A = 1, B = 1, C = 0: Y = 1
For A = 1, B = 1, C = 1: Y = 1
Discussion: Verilog simulation of combinational logic circuits is a fundamental experiment in
digital design and verification. It involves using the Verilog hardware description language (HDL)
to model, simulate, and verify the behavior of combinational logic circuits. Here’s a detailed
discussion of the key aspects of this experiment:
Verilog and Combinational Logic:
• Verilog HDL: Verilog is a hardware description language used to model electronic
systems. It is commonly used for designing digital circuits, especially in the context of
ASIC (Application-Specific Integrated Circuit) and FPGA (Field-Programmable Gate
Array) development.
• Combinational Logic Circuits: These circuits produce outputs based solely on the current
inputs, without any memory or feedback. Examples include logic gates (AND, OR, NOT),
multiplexers, and adders. The output is a function of the input values, and there’s no
dependence on past input states.
Modeling Combinational Logic in Verilog:
Verilog allows you to model combinational logic using different approaches:
• Behavioral Model: Uses high-level constructs to describe the desired behavior. It is often
implemented with continuous assignments (assign statements) or procedural blocks
(always blocks). It is useful for quick prototyping and understanding the circuit
functionality.
• Structural Model: Uses instances of gates and other components to explicitly define the
circuit’s structure. This model is closer to the actual hardware implementation and shows
how components are interconnected.
Simulation of Combinational Logic:
• Testbench: A testbench is a Verilog module used to apply different test vectors (input
values) to the design under test (DUT) and observe the output. It helps in validating the
correctness of the design.
• Simulation Results: The output from the simulation should be compared with the truth
table of the Boolean expression to ensure correctness. If discrepancies are found, the design
or testbench may need adjustment.
Advantages of Verilog Simulation:
• Validation: Allows early validation of design before physical implementation.
• Debugging: Helps in identifying and fixing issues in the logic before hardware deployment.
• Efficiency: Speeds up the design process by allowing quick modifications and re-testing.
Conclusion: Verilog simulation of combinational logic circuits is crucial for ensuring that digital
designs meet their functional requirements. By using behavioral and structural modeling
approaches, and validating designs through comprehensive testbenches, engineers can effectively
design and verify complex digital systems. Understanding how to model and simulate these
systems helps in creating robust and reliable hardware designs.