Analog Integr Circ Sig Process (2013) 74:517–526

DOI 10.1007/s10470-012-0022-6

A wide supply voltage range and low-power all-digital clock

generator
Kuo-Hsing Cheng • Jen-Chieh Liu •

Hong-Yi Huang • Yu-Tso Chen

Received: 11 June 2012 / Revised: 6 November 2012 / Accepted: 21 December 2012 / Published online: 6 January 2013
Ó Springer Science+Business Media New York 2013

Abstract This study presents a low-power all-digital 1 Introduction

clock generator (ADCG) for a wide supply voltage range
system. The proposed ADCG limits the maximum supply For a digital water meter (DWM) application, it wants to
current to 100 lA at a supply voltage ranging from 1.6 to reduce energy consumption and increase battery longevity.
3.6 V. The ADCG also uses a digitally controlled oscillator However, an analog water meter must be converted to a
(DCO) to extend its operational frequency range. The digital meter so that the recorded data can be transmitted to
proposed DCO controls the supply current and divider a control center through wired or wireless communications
circuits for a wide supply voltage range. The output duty [1, 2]. Digitalizing a water meter allows it to operate at a
cycle of ADCG falls within 50 ± 1.9 % using a duty cycle low supply current to maintain battery energy for up to
corrector. The maximum peak-to-peak jitter is less than 10 years of operation. Accordingly, the active current of
2.7 % at 8.38 MHz for a digital water meter application the microcontroller must be less than 600 lA for a wireless
(DWM). The operational frequencies of 1.45 and 8.38 DWM system [2].
MHz at 1.8 V are 3.1 and 36.7 lA, respectively. The core Table 1 lists the specifications of clock generator for the
area of ADCG is 0.14 mm2 for a 0.35 lm CMOS process. wireless DWM and microcontroller applications. A special
The operational frequency of ADCG ranges from 4.5 to specification for this study is to supply a maximum current
9.2 MHz at a supply voltage ranging from 1.6 to 3.6 V. of 100 lA considering the process, voltage, and tempera-
This clock generator can also be applied to microcontroller ture (PVT) non-idealities. Furthermore, a wide supply
applications. voltage range and a low supply current are also necessary
as a reusable silicon intellectual property (IP) for specific
Keywords All-digital clock generator (ADCG)  applications in system on chip (SoC). The supply voltage
Digitally controlled oscillator (DCO)  Duty cycle corrector range of clock generator is from 1.8 to 3.6 V and its
(DCC)  Low power  Wide supply voltage range operational frequency is 8.38 MHz for wireless DWM
applications. Thus, the clock generator provides excellent
stability with variations in PVT.
The proposed all-digital clock generator (ADCG) offers
K.-H. Cheng  Y.-T. Chen several advantages, including a small area, fast-locking
Department of Electrical Engineering, National Central time, inherent noise immunity of digital circuits. The
University, Jhongli, Taiwan ADCG also scales easily with novel processes. Researchers
have proposed many all-digital clock generators to meet
J.-C. Liu (&)
Information and Communications Research Laboratories, specific applications. In [4–13], low jitter ADCGs were
Industrial Technology Research Institute, Hsinchu, Taiwan implemented by digital entry to achieve higher jitter per-
e-mail: [email protected] formance than analog clock generators. A ring-based dig-
itally controlled oscillator (DCO) can obtain a wide
H.-Y. Huang
Graduate Institute of Electrical Engineering, National Taipei operational frequency range for a wide supply voltage
University, New Taipei, Taiwan application [5]. An ADCG proposed a search algorithm for

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Table 1 Specifications of the clock generator diagram of the ADCG. The ADCG commences frequency
Clock generator for micro-controller
acquisition when the enabling signal Start goes high. The
counter output C\9:0[ represents the monitored DCO out-
Application Wireless DWMa 80C51 CPUb put frequency, which is comparable to the target value of 256
Supply voltage 1.8–3.6 V 2.4–3.6 V (N\9:0[). Frequency acquisition is realized when the DCO
Maximum current 100 lA – clock frequency (DCOout) is aligned with the reference clock
Temperature -40 to 85 °C -40 to 85 °C frequency (Fref). Therefore, the DCO frequency is locked as
Input frequency 32.768 kHz ± 5 % – high as the 256-times reference clock.
Output frequency 8.38 MHz ± 5 % 4–12 MHz The number of clock cycles required to complete the
RC oscillator – 7.373 MHz ± 2.5 % locking procedure can be expressed as
Frequency multiplier 256 – NTotal ¼ NIniti: þ NFA ð1Þ
a b
DWM digital water meter, PHILIPS, P89LPC932 [3]
where NTotal represents the total locking time of the pro-
posed ADCG, and NTotal depends on bit numbers and an
a wide multiplication factor. Two DCOs are required to algorithm of the ADCG, including the initialization cycles
extend the multiplication range and operational frequency (NIniti.) and the frequency acquisition cycles of (NFA). The
[6]. Figure 1 shows the block diagram of the conventional 11-bit SAR circuit in this study requires two clock cycles to
ADCG. It comprises of a phase-to-digital convertor (P2D), identify each searching operation. The initialization uses
a digital loop filter (DLF), a DCO, and a divider. The P2D one clock cycle to set the registers and counter. Therefore,
convertor uses a bang–bang phase frequency detector the total locking time of the proposed ADCG is 23(=
(PFD) or a time-to-digital convertor to sample the phase 1 ? 22) cycles.
difference of Fref and Fback signals.
The proposed design offers three benefits. First, the
supply current controller (SCC) limits the supply current to 2.1 Quantization error and frequency accuracy
be less than 100 lA. Second, the divider circuits are added
in the DCO feedback to extend its operational frequency Figure 3 presents the quantization error of the proposed
range. Thus, the SCC can control the DCO current for a ADCG. The DCO output (DCOout) can sample the refer-
wide supply voltage range. Finally, ADCG adopts two ence period (Tref) using an En signal. The quantization error
search algorithms, one is for the fast-locking time and the in Fig. 3(b) is zero and the DCO output and the reference
other is to maintain locking when temperature and voltage signal are perfectly matched. Because the divisor is 256,
variations occur. These three benefits ensure a successful the reference signal is the 256-times DCO output period. If
operation at a low supply current and wide supply voltage. the DCO output is lower, the sampled ratio can still obtain
This paper is organized as follows. Section 2 introduces 256 (Fig. 3(a)). The quantization error is the period of
the architecture of the proposed ADCG. Section 3 lower DCO output (TDCO0 ). The real frequency period is
addresses the circuitry of ADCG. Section 4 presents 255 times the period of TDCO0 . Therefore, the real DCO
experimental results. Finally, Sect. 5 gives conclusions. output period is the 256/255 times target period. The period
error is the 0.39 % TDCO. For the same reason, the higher
DCO output (TDCO00 ) has the -0.39 % TDCO (Fig. 3(c)).
2 Architecture description Thus, the quantization error affects the accuracy of DCO
frequency.
Figure 2(a) presents a block diagram of the proposed ADCG, Figure 4 shows the frequency accuracy of the DCO. The
which consists of a SCC, main controller, comparator, 11-bit counter samples the DCO output at one reference period.
successive-approximation register (SAR) [14], 11-bit DCO, The counter output (C\9:0[) must be a continuous and
level shifter, and a counter. Figure 2(b) shows the timing integer binary code. For cases (b) and (c) in Fig. 4, the
relationship between the DCO output and reference fre-
quency is

FDCO ¼ 256  Fref

00 ð2Þ
FDCO ¼ 257  Fref ¼ FDCO þ Fref

where FDCO00 is the higher DCO frequency in case (c).

Therefore, the frequency resolution of DCO output can be
defined as Eq. (2). The timing resolution of DCO is the
Fig. 1 Conventional ADCG architecture timing difference between FDCO and FDCO ? Fref. The

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Fig. 2 The proposed ADCG

a block diagram b timing
diagram

Fig. 3 Quantization error at

a lower b ideal c higher DCO
output frequency

timing resolution of DCO in this study is less than 400 ps 2.2 Proposed digitally controlled oscillator
at 8.38 MHz. The counter can obtain a continuous and
integer value within a reference period using the optimi- Figure 5 shows a block diagram of the proposed DCO. For
zation of timing resolution of the DCO output. the low supply current DCO, the minimum supply current
can limit the operational frequency of the ring-DCO. Thus,
DCO uses 1-bit and 2-bit dividers to extend the operational
frequency range when variations of supply current and
supply voltage occur. The divider outputs do not reach a
50 % duty cycle. Therefore, the duty cycle corrector
(DCC) ensures that it provides a 50 % duty cycle. The
DCO uses three methods to extend its operational fre-
quency range, as Fig. 6 shows. First, the 1-bit SCC extends
the operational frequency range. The SCC can also limit
Fig. 4 Frequency accuracy of DCO output the DCO supply current and the other circuits. The SCC

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Fig. 5 Block diagram of the proposed DCO

ensures that the supply current remains less than 100 lA at

a wide supply voltage range. Second, the DCO with a 3-bit
divider can reduce the digitally controlled varactor’s Fig. 6 The DCO operational and frequency range
(DCV) control bit numbers. The power consumption
increases when the DCV control bits extend the DCO
tuning range. Third, the 7-bit DCV produces the minimum
DCO timing resolution, which is the primary consumer of
power. Thus, the DCO has a wide operational frequency
range when the supply voltage ranges from 1.6 to 3.6 V.

2.3 Supply current controller

Figure 7 presents the block diagram of the supply current

controller. The SCC consists of a reference current (Mf, R1,
and R2) and a current mirror circuit (Ma, Mb, Mc, Md, and Fig. 7 Block diagram of the current controller
Me). The diode-connected device Mf provides a constant
gate voltage to Ma, Mb, Mc, Md, and Me. The decoupling output to produce a 50 % duty cycle by combining these
capacitors use MOSFETs to decouple the supply noises and two signals. The multiplication factor for the characteris-
maintain fewer ripples in the supply voltages of the sub- tics of this divider scheme is 2i (i is integer), Qn\n[
circuits. The supply current controller is an analog circuit already contains 50 % of the cycle. Thus, Qn\n[ can pass
controlled in a digital mode. The most significant bit (MSB) to the DCC output (DCCn) through the MCn signal, where
code, S\10[, of the SAR counter determined to compare n is n-bit divider. For a 1-bit divider, MC1 equals to S\8[ .
the frequencies Fref and 256 9 DCOout limits the maximum DCG1 can be written as
supply current. Thus, the supply current controller leads to
DCG1 ¼ D1 \0[  Q1 \0[  S\8[ ð3Þ
very low power consumption.
where DCG1 consists of D1\0[ and Q1\0[ from 1-bit
divider (Fig. 8(a)). For a 2-bit divider, the output of the
3 Circuit implementation 2-bit divider, Q2\2[, defines the input signal of PG circuit.
Equations (4) and (5) show the MC2 and DCG2,
3.1 Proposed duty cycle corrector respectively.
MC2 ¼ S\7[ þ S\8[ ð4Þ
Figure 8(a) and (b) show the block diagrams of 1-bit and 
2-bit dividers for a DCO [15]. Though the DCO extends the DCG2 ¼ D2 \1[ þ Q2 \1[ þ Q2 \0[
operational frequency range of the ADCG, the duty cycle 
þS\8[ þ S\7[
output frequency is not than 50 %. The behaviour of the 
 D2 \1[ þ Q2 \1[ þ Q2 \0[
output signal without a 50 % duty cycle degrades system  ð5Þ
performance. Therefore, the output should maintain a 50 % þS\8[ þ S\7[
duty cycle. Figure 9 shows that the proposed DCC circuit  ðD2 \1[ þ Q2 \1[ þ Q2 \0[
combines a period generator (PG), a duty cycle generator 
þS\8[ þ S\7[
(DCG), a mode controller (MC), a MUX, and a SR latch.
The DCO can produce a 50 % duty cycle signal using the The PGn signal produces the clock period and the DCGn
proposed DCC. The PGn signal defines the clock period for signal decides the duty cycle. If the Qn\n[ is already
the DCC output, and the DCGn signal decides the 50 % 50 %, this signal can be passed to the DCC output by the
duty cycle of DCC output. The SR latch allows the DCC MCn signal. Therefore, the proposed DCC can be

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Fig. 10 Circuitry of the controller

Fig. 8 Circuitry of the n-bit divider a 1-bit divider b 2-bit divider C\9:0[matches N\9:0[. In the meantime, the status of the
Stop signal will be high, and the ADCG locked [14].
Figures 11 and 12 depict the circuitry and the timing
diagram of comparator, respectively [14]. The comparator
output changes from ‘‘Fast’’ to ‘‘Slow’’ over two consec-
utive frequency comparisons and also defines the increase
as well as decrease of the code. After the ClkCoun signal
goes high, it compares the values of C\9:0[ and N\9:0[.
The counter is able to count the cycle numbers of DCO
output at one reference clock cycle. Thus, when C\i[ is
equal to N\i[, Z\i[ must be low; otherwise, Z\i[ will be
high. When Z\9:0[is zero, signal Stop goes high. A linear
Fig. 9 Block diagram of n-bit DCC algorithm is combined with the SAR algorithm to avoid
unexpected locking and provides the high resolution of
locking frequency. The signal Stop switches the searching
programmed to extend the bit number. The DCC can between SAR and linear algorithms.
improve the maximum duty cycle by 21 % under 2-bit When Stop is low, the ADCG is in SAR algorithm for
divider with and without the duty cycle corrector. fast locking, otherwise, the algorithm will be transformed
into linear algorithm to maintain synchronization of Fref
3.2 Controller and comparator and Fback. The signal Add_Sub determines up or down
counting of the 11-bit SAR counter. If C\9:0[ is less than
Figure 10 shows the circuitry of the controller determining N\9:0[, the signal Add_Sub is low. However, the signal
the functional controls of the ADCG. The signal En serves Add_Sub is high if C\9:0[ exceeds N\9:0[.
as the enable-signal for DCO circuit via Fref. After the
signal Start goes high, all registers and counters will be 3.3 SAR circuit
reset. Two clock signals, ClkCom and ClkSAR, provide the
synchronizing signals for the comparator and SAR circuit, The SAR counter is the digital loop filer of the proposed
respectively. The ResCoun resets the 10-bit counter to low ADCG as shown in Fig. 13 [14]. The binary search and
after the counter calculates the number of output frequen- linear search algorithms form the primary operating prin-
cies in one reference cycle. If the signal Stop goes low, the ciple of the 11-bit SAR. The 11-bit SAR circuit uses the
counter calculates the number of output frequencies during binary search in the frequency acquisition procedure. This
the half period of En to match the value of 256. The output improvement helps the system attain a faster locking time.
signal from ClkCoun will be low when En goes low. The The SAR circuit adopts a linear search algorithm to avoid
comparator begins to compare the values between C\9:0[ ADCG unlocking when the binary search algorithm is
and N\9:0[when the counter completes its operation. The finished. The SAR algorithm retains one bit for Fref and
signal ResCoun is high to reset the counter outputs after the 256 9 DCOout to keep Fref and 256 9 DCOout synchro-
comparator finishes its work. The output signal is aligned nized. Figure 14 shows the locking simulation of the
to the clock edge and locked to a target frequency when ADCG. The worst-case of locking time is less than 23

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Fig. 11 Circuitry of the

comparator

Fig. 12 Timing diagram of the

comparator

reference cycles considering the variations of process and

temperature.

3.4 Level shifter and counter

The level shifter is necessary as reported in [16], since the

DCO output swing is reduced because of current limit from
the supply controller circuit. Hence, the level shifter pro-
vides the voltage swing of DCO output to arrive a full
swing voltage. The counter in the feedback path detects the
frequency of DCO output. In addition, it can decide the
increase or decrease of SAR output. The Frequency Mul-
tiplier’s factor is 256 in this study. Thus, the DCO output
Fig. 14 Locking time simulations of ADCG considering PVT
frequency can approach nearly one thousand times of the
variations
reference signal Fref when its supply voltage gets too high.
Two extra bits are added to detect overflow of the DCO
output so that the 10-bit counter output can be as high as 370 lm 9 380 lm. Figure 16(a) shows the measured jitter
1023. performances of ADCG at 1.8 V. This figure also demon-
strates a 347 ps RMS jitter with a 3.2 ns peak-to-peak
jitter (P2P jitter) at 8.38 MHz and a 5.9 ns peak-to-peak
4 Experimental results jitter of the reference signal. Figure 16(b) shows the jitter
histograms at a 3.6 V supply voltage. The RMS and peak-
Figure 15 shows a die photograph of the proposed ADCG. to-peak jitters at 8.38 MHz are 317 ps and 2.5 ns, respec-
The experimental prototype was fabricated using a tively at 3.6 V supply voltage. Figure 17 shows that the
0.35 lm CMOS process, and has a core area of measured errors of the duty cycle ratio are 50 ± 1.9 % at
12 k-hits. Figure 18 shows the ADCG supply current. The
ADCG supply currents were less than 100 lA at
8.38 MHz. The supply currents of the five test chips were
smaller than 100 lA.
Figure 19(a) and (b) display the locking times measured
through a logic analyser. The locking times of ADCG were
20 and 14 clock cycles at 1.8 and 3.6 V, respectively.
Fig. 13 Block diagram of SAR circuit Figure 20 illustrates the Schmoo plot of the test chip. The

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Fig. 15 Microphotograph of
the test chip

Fig. 17 Measured supply voltage and duty cycle at 8.38 MHz

Fig. 16 Measured jitter performance at a 1.8 V and b 3.6 V supply

voltages
Fig. 18 Measured supply currents of 8.38 MHz output at various
supply voltages
proposed ADCG can operate at a frequency range of
4.5 MHz to 9.2 MHz with a supply voltage ranging from
1.6 to 3.6 V. Figure 21 shows the phase noise of the ADCG The proposed ADCG can achieve a worst-case total
at 8.38 MHz at a supply voltage of 2.6 V. The phase noise locking time of 23 reference clock cycles. The multiplication
is -108.73 dBc/Hz at an offset frequency of 1 MHz, and factor is 256. The peak-to-peak jitter was less than 2.7 % at
below -99.58 dBc/Hz at a supply voltage ranging from 1.6 8.38 MHz. The accuracies of the ADCG frequency were
to 3.6 V. 8.38 MHz ± 1.57 % at 1.8 V and 8.38 MHz ± 1.14 % at

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Fig. 19 Measured locking

times at 8.38 MHz at a 1.8 V
and b 3.6 V supply voltages

Fig. 21 Measured the phase noise of ADCG

Fig. 20 Schmoo plot of working region
3.6 V at 8.38 MHz. For a fair comparison, the power was
3.6 V. Table 2 compares the performance of the proposed normalized to the ratio between the RMS jitter and the output
all-digital clock generators with other designs. An ultralow- period. Equation (6) provides the figure-of-merit (FOM)
powered and low-jitter ADCG was operated from 1.6 to used to compare the clock generators [17].

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Table 2 Specifications of the ADCG

Reference This work [4] [8] [13] [14]

Process (nm) 350 350 180 350 180

Supply voltage (V) 1.6–3.6 3.3 1.8 3.3 1.8
Locking time (Cycles) 23 46 – 45 32
2
Chip area (mm ) 0.14 0.71 0.14 0.17 0.09
Operational 1.5–11.4 (1.8 V) 45–510 100–600 2–255 150–450
Frequency (MHz) 4.5–25.3 (3.6 V)
RMS Jitter (ps) [email protected] MHz (1.8 V) 22@450 MHz 7.28@600 MHz 20@192 MHz 44@450 MHz
[email protected] MHz (3.6 V)
Power (mW) [email protected] MHz (1.8 V) 100@500 MHz 26.7@600 MHz 33@192 MHz 16.2 @450 MHz
[email protected] MHz (3.6 V)
FOM 41.8 (1.8 V) – 30.7 26.0 18.5
37.0 (3.6 V)

! 5. Tierno, J. A., Rylyakov, A. V., & Friedman, D. J. (2008). A wide

TOSC 1 power supply range, wide tuning range, all static CMOS all
FOM ¼ 10  log 2  ð6Þ
rTOSC Pdiss digital PLL in 65 nm SOI. IEEE Journal of Solid-State Circuits,
43(1), 42–51.
6. Chen, P.-L., Chung, C.-C., Yang, J.-N., & Lee, C.-Y. (2006). A
clock generator with cascaded dynamic frequency counting loops
5 Conclusion for wide multiplication range applications. IEEE Journal of
Solid-State Circuits, 41(6), 1275–1285.
7. Lin, S.-Y., & Liu, S.-I. (2009). A 15 Ghz all-digital spread-
This study presents a wide supply voltage and low supply spectrum clock generator. IEEE Journal of Solid-State Circuits,
current all-digital clock generator (ADCG). The proposed 44(11), 3111–3119.
ADCG has a supply current smaller than 100 lA at a 8. Hsu, H.-J., & Huang, S.-Y. (2011). A low-jitter ADPLL via a
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The fast-locking time and 50 % duty cycle are also System, 19(1), 165–170.
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proposed current controller that minimizes the supply S., et al. (2004). A PVT tolerant 0.18 MHz to 600 MHz self-
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Acknowledgments The authors would like to thank the Chip Ainspan, H. A., & Friedman, D. (2008). A modular all-digital
Implementation Center (CIC), Taiwan, for fabricating the test chip. PLL architecture enabling both 1-to-2 GHz and 24-to-32 GHz
This study was supported by the Fortune Semiconductor Corporation. operation in 65 nm CMOS. IEEE international solid-state cir-
cuits conference digest of technical papers, pp. 516–632.
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period jitter TDC-less fractional-N digital PLL with digitally
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programmable dividers in standard 0.35-um CMOS technology. Hong-Yi Huang was born in
IEEE Journal of Solid-State Circuits, 35(7), 1039–1045. Taiwan in 1965. He received the
16. Matsumoto, A., Sakiyama, S., Tokunaga, Y., Morie, T., & Dosho, B.S. degree in Nuclear Engineer-
S. (2008). A design method and developments of a low-power ing from the National Tsing-Hua
and high-resolution multiphase generation system. IEEE Journal University, Hsinchu, Taiwan in
of Solid-State Circuits, 43(4), 831–843. 1987 and the M.S. and Ph.D.
17. Gierkink, S. L. J., & Ed (A. J. M.) van Tuijl (2002) A coupled degrees from the Institute of
sawtooth oscillator combining low jitter with high control line- Electronics, National Chiao-Tung
arity. IEEE Journal of Solid-State Circuits, 37(6):702–710. University, Hsinchu, Taiwan in
1989 and 1994, respectively. He
was with Industrial Technology
Kuo-Hsing Cheng was born in Research Institute (ITRI), Taiwan
Taipei, Taiwan, Republic of from 1994 to 1999, engaged in
China, in 1962. He received the mixed-signal integrated circuits
B.S. degree from the Department design. He was with the Depart-
of Electrical Engineering, ment of Electronic Engineering, Fu-Jen Catholic University, Taiwan since
National Central University in 1999. He is an associate professor in Graduate Institute of Electrical
1985, and the M.S. and Ph.D. Engineering, National Taipei University, Taiwan since 2006. His research
degrees from the Institute of interests are in bio-circuits and systems, high-speed and low-power low-
Electronics, National Chiao- voltage integrated circuits and systems, embedded memory, analog and
Tung University, Taiwan, communication integrated circuits. He has authored and coauthored over
Republic of China, in 1987 and 60 research papers and 30 patents.
1992, respectively. During the
years 1987–1992, he studied in Yu-Tso Chen was born in
the development of high perfor- Tainan, Taiwan, Republic of
mance digital integrated circuits China, in 1984. He received the
and systems. During 1992–1993 he was an associate researcher in the B.S. degree from the Depart-
Chip Implementation Center, National Science Council, Taiwan. From ment of Electrical Engineering,
1993 to 2003, he was an associate professor in the Department of National Taipei University of
Electrical Engineering, Tamkang University, Taiwan. In 2003, he Technology, Taipei, Taiwan, in
joined the faculty of the National Central University at Jung-Li, Taiwan. 2007. And, he received the M.S.
He is currently a professor in the Department of Electrical Engineering. degree from National Central
His research interests include LV/LP high-speed mixed-signal inte- University, Taiwan, in 2009.
grated circuits and systems, clock synchronization circuits and ultra- His research interests include all
high-frequency mixed-signal circuits for wire communications. digital PLL and wide supply
voltage range circuit.
Jen-Chieh Liu was born in
I-Lan, Taiwan, Republic of
China, in 1981. He received the
B.S. and M.S. degree from the
department of electrical engi-
neering, Fu-Jen catholic univer-
sity, Taiwan, in 2004, and 2006,
respectively. He received the
Ph.D. degree from the depart-
ment of electrical engineering,
National Central University,
Taiwan, in 2012. Since 2010, he
has been with the Industrial
Technology Research Institute
(ITRI), Taiwan, where he has
been working as an IC design engineer. His research interests include all
digital PLL, built-in jitter measurement circuits, and low power/low
supply voltage for clock synchronization circuits and systems.

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