EXPERIMENT NO.

: - 1

AIM: To study the basic logic gates which are used in digital circuits.

THEORY:

Any Gate is a logic circuit with one output and one or more inputs. The output signal of any gate occurs
only for certain combination of input signals. Different types of gates are used in the digital circuit like
AND gate, OR gate, NOR gate, NAND gate, NOT gate are the basic logic gates. Some gates are the
combination of above basic gates. Such gates can be prepared by using discrete components like diodes,
transistors, and resisters but nowadays, different ICs are used to have different gates. A power supply of +5
V is used to give input. This supply is also used to drive ICs. When power supply to the input is 'ON' we can
say that logic level is at '1' and when power supply to the input is 'OFF' the logic level is said to be at '0'
level.

AND GATE:
AND gate is a gate which gives output (output at '1' level) only when all inputs are present (i.e. all inputs are
at '1' level). Here IC 7408 is used which has 2-inputs AND gate which are four in numbers. Here only one
gate is used. The truth table of AND gate is given in the table.

A B OUTPUT
0 0 0
0 1 0
1 0 0
1 1 1

OR GATE:
OR gate is a gate which gives output (output at '1' level) when any ONE of the input is present (any ONE
out of all input must be at '1' level). Here IC 7432 is used which has two input OR gates which are four in
numbers. The truth table of OR gate is given in the table.

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PAGE : 1 Digital Electronics
 A B OUTPUT
0 0 0
0 1 1
1 0 1
1 1 1

NOT GATE:
This is also known as INVERTER gate. This gate has one input and one output. All it does is invert the
input signal i.e. if the input is at high level, the output will be at low level and vice versa. ICs 7404 or 7406
can be used to get NOT gates, which are six in numbers. The truth table of NOT gate is given in the table.

A OUTPUT
0 1
1 0

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PAGE : 2 Digital Electronics
Ex-OR GATE:-
XOR gate is a gate which gives output (output at 1 level) when both of the input is different (any ONE input
at 1 level and other at 0 level). When both of the input is same output is at 0 levels. This gate is used in the
comparison. Here 1C 74LS86 is used which has two input XOR gates. There are four XOR gate in this 1C.
Here only one gate is used. The truth table and logical symbol of XOR gate is given below.

A B OUTPUT
0 0 0
0 1 1
1 0 1
1 1 0

EQUIPMENTS REQUIRED:

Trainer kit or Bread Board, Power Supply and LEDs.

COMPONENTS REQUIRED:

-ICs 7408, 7432, 7404.

-Hook up wires.

PROCEDURE:

1. Pull all switches at „0‟ position.

2. Switch ON the power supply.
3. Test the truth table of different gates by changing the position of inputs (i.e. „1‟ level means switch is
ON & „0‟ level means switch is OFF) and check the level of output (if LED glows it is at level „1‟
and if LED doesn‟t glow output is at level „0‟).

OBSERVATIONS:
Verify truth table of all gates in trainer kit.

CONCLUSION:
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PAGE : 3 Digital Electronics
 EXPERIMENT NO.: - 2

AIM: To study NAND and NOR gates as Universal Gates.

THEORY:
In addition to AND, OR, and NOT gates, other logic gates like NAND and NOR are also used in the design
of digital circuits.

NAND GATE:
It is a sequence of series combination of AND gate and NOT gate, known as NAND gate. The output of
NAND gate is at „0‟ level only when all the inputs are „1‟ level. In rest of all the conditions of inputs the
output will be at level „1‟. IC 7400 can be used to get NAND gate. This IC has two input NAND gates,
which are four in numbers. The truth table of NAND gate is given in the table.

A B OUTPUT(Y)
A Y 0 0 1
0 1 1
1 0 1
B
1 1 0

NAND Gate is a Universal Gate:

NAND gate is called a universal gate because any gate can be implemented using NAND gate to prove that
any Gate can be implemented using only NAND gates, we will show that the AND, OR, and NOT
operations can be performed using only these gates.

Implementing an Inverter Using only NAND Gate

The figure shows ways in which a NAND gate can be used as an inverter (NOT gate).

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PAGE : 4 Digital Electronics
Implementing AND Using only NAND Gates

An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced by a NAND
gate with its output complemented by a NAND gate inverter).

Implementing OR Using only NAND Gates

An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced by a NAND
gate with all its inputs complemented by NAND gate inverters). Thus, the NAND gate is a universal gate
since it can implement the AND, OR and NOT functions.

NOR GATE:
It is a sequence of series combination of OR gate and NOT gate. The output of NOR gate is at level „1‟
when all the inputs are at „0‟ level. In rest of all the conditions of inputs the output is at „0‟ level. IC 7402
can be used to neither get NOR gate. This IC neither has two input NOR gates, which are four in numbers.
The truth table of NOR gate is given in table.

A B OUTPUT
0 0 1
Y 0 1 0
1 0 0
1 1 0

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PAGE : 5 Digital Electronics
NOR Gate is a Universal Gate:
To prove that any Gate can be implemented using only NOR gates, we will show that the AND, OR, and
NOT operations can be performed using only these gates.

Implementing an Inverter Using only NOR Gate

The figure shows two ways in which a NOR gate can be used as an inverter (NOT gate).

Implementing OR Using only NOR Gates

An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by a NOR gate with
its output complemented by a NOR gate inverter)

Implementing AND Using only NOR Gates

An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is replaced by a NOR
gate with all its inputs complemented by NOR gate inverters)

EQUIPMENTS REQUIRED:

Trainer kit or Bread Board, Power Supply and LED‟s.

COMPONENTS REQUIRED:
-ICs 7400, 7402
-Hook up wires

PROCEDURE:

1. Pull all switches at „0‟ position.

2. Switch ON the power supply.

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PAGE : 6 Digital Electronics
 3. Test the truth table of different gates by changing the position of inputs (i.e. „1‟ level means switch is
ON & „0‟ level means switch is OFF) and check the level of output (if LED glows it is at level „1‟
and if LED doesn‟t glow output is at level „0‟).

OBSERVATIONS:

CONCLUSION:

Questions:

1) Convert Following Binary Numbers to Decimal.

a) 11011 b) 0.1101 c) 1101.1101
Ans : a) 27 b) 0.8125 c) 13.8125

2) Convert Following Decimal Numbers to Binary.

a) 27 b) 0.75 c) 21.625
Ans: a) 11011 b) 0.11 c) 10101.101

3) Convert Following Octal Numbers to Decimal.

a) 753 b) 0.235 c) 265.731
Ans: a) 491 b) 0.30664 c) 181.92375

4) Convert Following Decimal Numbers to Octal.

a) 266 b) 0.256 c) 125.201
Ans : a) 412 b) 0.20304 c) 175.14672

5) Convert Following Octal Numbers to Binary.

a) 452 b) 0.275 c) 746.421
Ans: a) 100101010 b) 0.010111101 c) 111100110.100010001

6) Convert Following Binary Numbers to Octal.

a) 100011110 b) 0.010111101 c) 100101111.0110101
Ans : a) 436 b) 0.275 c) 27.324
7) Convert Following Hexa-Decimal Numbers to Decimal.
a) A23 b) 0.351 c) A23.351
Ans : a) 2595 b) 0.20727 c) 2595.20727

8) Convert Following Decimal Numbers to Hexa-Decimal.

a) 293 b) 0.210 c) 125.201
Ans : a) 125 b) 0.35C28F c)7D.3374B

9) Convert Following Hexa-Decimal Numbers to Binary.

a) 47A b) 0.264 c) F23.
Ans : a) 010001111010 b) 0.001001100101 c) 111100100011.011010100001

10) Convert Following Binary Numbers to Hexa-Decimal.

a) 100011110101 b) 0.010111101 c) 1010010111.0110101

Ans : a) 8F5 b) 0.5E8 c) 297.6A

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PAGE : 7 Digital Electronics
 EXPERIMENT NO.: - 3

AIM: To study the arithmetic function of addition by building Half Adder circuit using logic gates.

THEORY:
This experiment gives how computer does the function of addition. The addition of two numbers in binary
which does not have “carry” is done by half adder circuit and the addition of two numbers in binary which
have “carry” is done by full adder circuit.

The half adder adds two-binary digit at a time. Fig. given below shows how to make half adder by using two
logic gates namely AND gate and EX-OR gate. The truth table of EX-OR gate is as below:

EX-OR Gate:

A B OUTPUT
0 0 0
0 1 1
1 0 1
1 1 0

As shown in the following figure the output of AND gate is used as “carry” bit and the output of EX-OR
gate is used as “sum” bit. There will be four distinct cases which are shown in following truth table.

A B Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

EQUIPMENT REQUIRED:

-Trainer kit

COMPONENTS REQUIRED:

-ICs 7486, 7408.

-Hook up wires.

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PAGE : 8 Digital Electronics
PROCEDURE:
1. Connect 5V DC power supply to input terminals.
2. Change the state of A & B (0 & 1) to get four states at output by changing the position of micro
switch. Check the truth table of half adder. ( If LED glows it is High state and if it does not glow
then it is Low state)

OBSERVATIONS:

CONCLUSION:

Questions :

1) Convert the Foollowing Numbers to Decimal.

a) 12121 (base3)
b) 1032.2(base4)
c) 4310 (base5)
d) 0.342(base6)
e) 50(base7)
f) 8.3(base9)

2) Convert the Decimal numbers 250.5 to base3,base4,base7

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PAGE : 9 Digital Electronics
 EXPERIMENT NO.: - 4

AIM: To study the arithmetic function of addition by building Full Adder circuit using logic gates.

THEORY:

This experiment gives how computer does the function of addition. The addition of two numbers in binary
which does no have “carry” is done by half adder circuit and the addition of two numbers in binary which
have “carry” is done by full adder circuit. Sometimes in addition of two binary numbers you may have a
carry from one column to the next. So in the next column we have to add three digits. This is not possible by
half adder circuit. This is carried by a circuit as shown in fig.1 which consists of two half adder circuits and
an OR-gate. This is known as full adder circuit.

Figure: 1

As shown in figure.1 the output of AND gate is used at “carry” bit and the output of EX-OR gate is used as
“sum” bit. There will be four distinct cases which are shown in following truth table.

A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

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PAGE : 10 Digital Electronics
EQUIPMENT REQUIRED:

-Trainer kit

COMPONENTS REQUIRED:

-ICs 7408, 7432, 7486.

-Hook up wires.

PROCEDURE:
1. Connect 5V DC power supply to input terminals.
2. Change the state of A & B (0 & 1) to get four states at output by changing the position of micro
switch. Check the truth table of half adder. ( If LED glows it is High state and if it does not glow
then it is Low state)

OBSERVATIONS:

CONCLUSION:

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PAGE : 11 Digital Electronics
Question :

1) Find the 1’s & 2’s Complement of Following Numbers

a) 00001000 b) 10101011 c) 10011001

Ans : a) 11110111, 11111000 b) 01010100, 01010101 c) 01100110, 01100111

b) Find the 9’s &10’s Complement of Following Numbers

a) 52520 b) 25.639 c) 90090 Ans : a) 47479,47480 b) 74.360,74.361 c) 09909,09910

b) Using 2’s Complement Perform M-N of Following Numbers.

a) M=1010100 b) M=11010 Ans:
N=1000100 N=1101

b) Using 1’s Complement Perform M-N of Following Numbers.

a) M=10010 b) M=11010 Ans:
N=10011 N=10000

a) Using 10’s Complement Perform M-N of Following Numbers.

a) M=5250 b) M=753 Ans:
N=321 N=864

a) Using 9’s Complement Perform M-N of Following Numbers.

a) M=3570 b) M=20 Ans:
N=2100 N=1000

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PAGE : 12 Digital Electronics
 EXPERIMENT NO.: - 5

AIM: To Design Half-subtractor.

THEORY:

A combination circuit that performs the arithmetic subtraction of two bits is called half subtractor. In figure
we assigns two symbols X and Y are two input variables and D (difference) and B (borrow) are two output
variables. The truth table for half subtractor is shown in figure.
D = x‟y + xy‟
=xy
B = x y‟
The half subtractor consists of an X-OR gate and AND gate.

EQUIPMENTS REQUIRED:

-Trainer kit

COMPONENTS REQUIRED:

 Connecting wires
 IC 7408 (AND gate)
 IC 7486 (X-OR gate)
 IC 7404(NOT gate)

PROCEDURE

1. Join the circuit as per circuit diagram.

2. Verify the truth-table.

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PAGE : 13 Digital Electronics
OBSERVATIONS:

CONCLUSION:

Question :

1) Find the Minterms for the following functions.

a) Y(A,B,C) = AB‟ + C‟ b) AB + AC‟ + BC c) AB + ABC‟ + B‟

Ans : a) ∑m (0,2,4,5,6) b) ∑m (2,4,6,7) c) ∑m (0,1,4,5,6,7)

2) Find the Maxterms for the following functions.

a) Y(A,B,C) = (A+B)(B+C‟)(A+C) b) (A+B‟)(A+B+C‟) c) (A+B)(B‟+C)(A+B‟C)

Ans : a) ∑M (0,1,2,5) b) ∑M (1,2,3) c) ∑M (0,1,2,6)

3) Minimize the Following Expression using K-map.

a)Y(A,B,C) = ∑m (1,3,5,7) b) Y(A,B,C) = ∑m (0,1,4,5) c) ∑m (0,2,4,6)

Ans : a) Y(A,B,C) = C b) Y(A,B,C) = B‟ c) Y(A,B,C) = B‟

4) Minimize the Following Expression using K-map.

a) Y(A,B,C) = AB + CB‟ + C b) Y(A,B,C,D) = ABC‟ + BCD + BCD‟
c) Y(A,B,C,D) = ABC‟ + BCD + B

Ans : a) Y(A,B,C) = AB + C b) Y(A,B,C,D) = AB + BC c) Y(A,B,C,D) = CB + AB + BD‟

5) Minimize the Following Expression using K-map.

a) Y(A,B,C) = (A+B‟+C)(A‟+B‟+C)(A+B‟+C‟)(A‟+B‟+C‟) b) Y(A,B,C,D) = (C+D)(C‟+D‟)
c) Y(A,B,C) = Πm(0,2,4,6) d)Y(A,B,C) = Πm(0,1,2,3,4,5,6,7)

Ans : a) Y(A,B,C) = B‟ b) Y(A,B,C,D) = D‟ c) Y(A,B,C) = C

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PAGE : 14 Digital Electronics
 EXPERIMENT NO.: - 6

AIM: To design Full-subtractor.

THEORY:

A combination circuit that performs the arithmetic subtraction of three bits is called full subtractor. In figure
we assigns three symbols X, Y and Z are three input variables and D (difference) and B(borrow) are two
output variables. The truth table for full subtractor is shown in figure.

D=xyz
B = x‟y + x‟z + yz

The full subtractor consists of two half-subtractor and one OR gate.

EQUIPMENTS REQUIRED:

-Trainer kit

COMPONENTS REQUIRED:

 Connecting wires
 IC 7408 (AND gate)
 IC 7486 (X-OR gate)
 IC 7432 (OR gate)

PROCEDURE:
1.Join the circuit as per circuit diagram.
2.Verify the truth table for full-subtractor.
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PAGE : 15 Digital Electronics
OBSERVATION:

CONCLUSION:

Question :
1) Minimize the Following Boolean functions:
a) Y(A,B,C,D) = ∑m (1,3,7,11,15) + d(0,2,5)
b) Y(A,B,C,D) = πM (4,5,6,7,8,12) . d(1,2,3,9,11,14)
c) Y(A,B,C,D) = ∑m (1,3,5,8,9,11,15) + d(2,13)
d) Y(A,B,C,D) = πM (1,2,3,8,9,10,11,14) . d(7,15)

Ans : a) Y(A,B,C,D) = CD + A‟B‟ b) Y(A,B,C,D) = (A+B‟)(A‟+C+D)

c) Y(A,B,C,D) = B‟D+C‟D+AB‟C‟+AD
d) Y(A,B,C,D) = (A‟+B)(A‟+C‟)(B+C‟)(B+D‟)

2) Minimize the following Boolean functions using Tabulation method

a) Y(A,B,C,D) = ∑m (2,4,5,9,12,13)
b) Y(A,B,C,D) = ∑m (1,4,8,12,13)

Ans : a) A‟B‟CD‟+AC‟D+BC‟ b) A‟B‟C‟D+BC‟D‟+AC‟D‟+ABC‟

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PAGE : 16 Digital Electronics
 EXPERIMENT NO.: - 7

AIM: To study the operation of multiplexer circuit.

THEORY:

A multiplexer is a MSI logic circuit capable of selecting single input bit from a number of different inputs
and routing the selected bit to a single output. The bit selected is determined by the appropriate input
address lines. For instant a multiplexer having three data select lines A, B, C is capable of selecting one of
the eight possible input bits (i.e. D0 to D7). Here IC 74151 is used which is eight bit multiplexer. The
connection diagram and truth table are shown in respective figures.

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PAGE : 17 Digital Electronics
 A B C

Vcc
9 10 11 16
I7
Strobe 12
7 13 I6
I5
GND 14
8
I4
Y 74LS151 15
I3
5 1
I2
Y' 2
I1
6 3
I0
4

INPUTS OUTPUTS
SELECT STROBE
C B A S Y
X X X H L
L L L L D0
L L H L D1
L H L L D2
L H H L D3
H L L L D4
H L H L D5
H H L L D6
H H H L D7

EQUIPMENT REQUIRED:
-Trainer kit

COMPONENTS REQUIRED:

-ICs 74151.
-Hook up wires.

PROCEDURE:

1. Switch ON the power supply.

3. Set inputs (D0 to D7) at high level or at low level as desired.
4. Set STR to low level.
5. Set three data select lines A, B, C at any value as per truth table ( say A = Low, B= High , C= Low
i.e. 010 i.e. decimal 2 as per column no. 4)
6. Multiplexer will select D2 input at Y output terminal.
7. Check the truth table for different value of data select lines A, B, C mentioned in the truth table and
checks the selected input Y appears at output.
8. If the level of strobe is changed to high level at any point, Y output will be only at low level
irrespective of any position of A, B, C.

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PAGE : 18 Digital Electronics
OBSERVATIONS:

CONCLUSION:

Questions:
1. Give the difference between Sequential and Combinational logic circuit
2. Write short note on the following
A) R-S Flip flop
B) J-K Flip flop
C) D- Flip flop
D) T- Flip flop
E) Master Slave J-K Flip flop

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PAGE : 19 Digital Electronics
 EXPERIMENT NO.: - 8

AIM: To study the operation of de-multiplexer circuit.

THEORY:

A demultiplexer is a MSI logic circuit capable of routing data from a single source to one of a number of
possible destinations the data bits are applied at the enable inputs and they appear at an output specified by
the address inputs A, B, C.

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PAGE : 20 Digital Electronics
Here IC 74138 is used which decodes one of eight lines based upon the conditions at the three binary select
inputs and the three enable inputs. The connection diagram and function table are shown below.
A B C

Vcc
3 2 1 16
G2A 15 Y0
4 14 Y1
G2B 13 Y2
5
74LS138 12 Y3
G1 Y4
6 11
Y5
10
8 Y6
9
7 Y7

INPUTS OUTPUTS
ENABLE SELECT
G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X H H H H H H H H
L X X X X H H H H H H H H
H L L L L L H H H H H H H
H L L L H H L H H H H H H
H L L H L H H L H H H H H
H L L H H H H H L H H H H
H L H L L H H H H L H H H
H L H L H H H H H H L H H
H L H H L H H H H H H L H
H L H H H H H H H H H H L

EQUIPMENT REQUIRED:

-Trainer kit

COMPONENTS REQUIRED:

-ICs 74138.
-Hook up wires.

PROCEDURE:

1. Switch ON the power supply.

2. Set G1, G2A and G2B at low level.
3. Set inputs C, B, A at low level.
4. All output must be at high level ( i.e. all LED should glow - condition no.2)
5. Set G1, G2A and G2B at high level & inputs C, B, A as it is i.e. at low level.
6. All output must be at high level (i.e. all LED should glow – condition no.1)
7. Set G1 at high level and G2A and G2B at low level.

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PAGE : 21 Digital Electronics
 8. Set C, B, A at any different levels and check the outputs as per truth table, for example, if you adjust
C, B, A to 0 1 0 , the output Y2 only will be low, others will be at high level – condition no.5.

OBSERVATION:

CONCLUSION:

Questions:
a) Explain Half adder and Full adder in details.
b) Explain Half Substractor and Full Substractor in details.
c) List out the Design Procedure for Combinational logic Circuit.
d) Design a Combinational Circuit For BCD to Excess-3 Code Converter.
e) Write a Short note on universal gates.
f) Design a combinational logic circuit for even & odd Parity generator and Parity Checker

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PAGE : 22 Digital Electronics
 EXPERIMENT NO.: - 9

AIM: To study R-S Flip flop circuit.

THEORY:

A multivibrator is a regenerative circuit with two active devices, designed so that one device conducts while
the cuts off. Multivibrator can store binary numbers. So, it can perform essential functions like counting of
pulsed, synchronizing arithmetic operations etc. Such type of circuit is known as Flip-Flop circuits.

R R
Q Q

Q' Q'
S S

The R-S Flip-Flop is another name of bi-stable multivibrator, one whose output is low or high, 0 or 1. This
output can be changed to other state only with the help of an external input called „TRIGGER‟. Until the
external input is applied, the original state of output remains unchanged indefinitely fig. no. 1 shows the
circuit diagram of R-S flip-flop, which of two NOT gates and two NAND gates. This flip-flop has two
inputs namely R and S (R=reset & S=set) and has outputs namely Q and Q‟, where Q‟ is always the
complement of Q. The truth-table of this R-S flip-flop is as under.

R R
Q Q
Clock Clock
Q' Q'
S S

R S Q
0 0 Last state
0 1 1(Set)
1 0 0(Reset)
1 1 1 Forbidden

The first input condition in the truth-table is R=0 & S=0. Since 0 input has no effect on its output, the flip-
flop simply remains on its previous state i.e. Q remains unchanged.

The second input condition of the truth-table is R=0 & S=1 forces the output to switch over to 1 i.e. at high
level. Thus input at 1 level is said that the flip-flop has SET i.e. Q=1(naturally Q‟=0).

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PAGE : 23 Digital Electronics
The third input condition of the truth-table is R=1 & S=0 forces the output to switch over to 0 i.e. at low
level. Thus input at 0 level is said that the flip-flop has RESET i.e. Q=0(naturally Q‟=1).

The fourth input condition of the truth-table is R=1 & S=1 forces the output of both NAND gates to switch
over to 0 i.e. at low level. In other words Q=Q‟+0 at the same time. This is nothing but violation of the basic
definition of flip-flop that Q must complement of Q‟. This state is known as forbidden state. Generally it is
agreed upon never to impose this input condition.

EQUIPMENT REQUIRED:
-Trainer kit

COMPONENTS REQUIRED:
-IC 7432
-Hook up wires.

PROCEDURE:
1. Connect circuit as per the ckt. Diagram and give 5V DC power supply to input terminals.
2. Switch ON the power supply.
3. Change the state of R & S as per truth-table and note down the status of output at every stage as per
truth-table.
4. Closely watch the output when R=S=1.

OBSERVATIONS:

CONCLUSION:

Questions:
a) Write a short note on Binary parallel adder.
b) Write a short note on 4-bit full adder with look ahead carry generator
c) Write a short note on BCD adder
d) Design a combinational logic circuit for 2-bit magnitude Comparator

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PAGE : 24 Digital Electronics
 EXPERIMENT NO.: - 10

AIM: To study D Flip-Flop circuit.

THEORY:

A multivibrator is a regenerative circuit with two active devices, designed so that one device conducts while
the cuts off. Multivibrator can store binary numbers. So, it can perform essential functions like counting of
pulsed, synchronizing arithmetic operations etc. Such type of circuit is known as Flip-Flop circuits

D R
Q
Clock
Q'
S

The R-S Flip-Flop has two data input R & S. To store a high bit you need a high S. To store a low bit you
need a high R. Generation of two signals to drive a Flip-Flop is a disadvantage in many applications. Further
more the forbidden condition of both R=S=1 may occur inadvertently. This had led to change R-S Flip-Flop
i.e. a Flip-Flop that needs only a single data input. This Flip-Flop is shown in figure. The truth-table of D
Flip-Flop is as under:

CLK D Qn+1
0 X On(Last state)
1 0 0(Reset)
1 1 1(Set)

This kind of Flip-Flop prevents the value of D from reaching the Q output until a clock occurs.

In general D Flip-Flop is a bi-stable circuit whose D input is transferred to the output only after clock pulse
is received.

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PAGE : 25 Digital Electronics
EQUIPMENT REQUIRED:
-Trainer kit

COMPONENTS REQUIRED:
-ICs 7400, 7432, 7408
-Hook up wires.
PROCEDURE:
1. Connect circuit as per the circuit diagram.
2. Switch ON the power supplies for any condition of D and analyze the condition of output Q as per
truth-table.
3. Set D=0 and apply clock pulse. Analyze the condition of output Q and verify with truth-table.
4. Set D=1 and apply clock pulse. Analyze the condition of output Q and verify with truth-table.

OBSERVATIONS:

CONCLUSION:

QUESTIONS:
a) Write a short note on following.
1) Multiplexer
2) Demultiplexer
3) Encoder
4) Decoder
b) Implement Full adder using 3 to 8 Line decoder.
c) Implement Following expression using multiplexer.
1) F(A,B,C,D) = ∑m(0,2,3,6,8,9,12,14)
2) F(A,B,C) = ∑m(0,1,4,6,7)
3) F(A,B,C,D) = ∑m(0,1,3,4,8,9,15)
4) F(A,B,C) = ∑m(1,3,5,6)

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PAGE : 26 Digital Electronics
 EXPERIMENT NO.: - 11
AIM: To study JK Flip flop circuit.

THEORY:

A multivibrator is a regenerative circuit with two active devices, designed so that one device conducts while
the cuts off. Multivibrator can store binary numbers. So, it can perform essential functions like counting of
pulsed, synchronizing arithmetic operations etc. Such type of circuit is known as Flip-Flop circuits.

JK flip-flop can be used to build a counter that counts the number of positive or negative clock edges
driving its clock input. For the purpose of counting, the JK flip-flop is the ideal element to use. The fig.
shows circuit diagram of JK flip-flop. The truth table is as under.

CLK J K Q n+1
X 0 0 On (Last state)
↑ 0 1 0 (Reset)
↑ 1 0 1(Set)
↑ 1 1 On‟(toggle)

When J & K both are at low state, both AND gate are disabled and so clock pulse has no effect i.e. Q
retains its last value. When J=0 & K=1 upper gate is disable so there is no way to set the flip-flop. The only
possibility is RESET. When Q is high, the power gate passes a RESET triggers as soon as the next positive
clock edge arrives. This forces Q to become low. When J=1 & K=0, lower gate is disable so it is impossible
to RESET the flip-flop. We can SET the flip-flop. When Q is low Q bar is high. Therefore the upper gate
passes a SET trigger on the next positive clock edge. This drives Q into high state i.e. Q=1.When J=1 &
K=1 then there is a forbidden state with RS flip flop i.e. it is impossible to SET or RESET the flip flop. If Q
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PAGE : 27 Digital Electronics
is high, the lower gate passes a RESET trigger on the next positive clock edge. On the other hand when Q is
low the upper gate passes a SET trigger on the next positive clock edge. Either way Q changes to the
complement of the last state. Therefore J=1 & K=1 means the flip flop will toggle on the next positive clock
edge. The toggle means to switch to the opposite state. Thus by addition of clock and getting propagation
delay, racing problem can be eliminated in JK flip flop.
EQUIPMENT REQUIRED:
-Trainer kit

COMPONENTS REQUIRED:
 IC 7400 (for clock)
 IC 7432 (for RS flip flop)
 IC 7486 (3- input AND gate)
 Hook up wires.
PROCEDURE:
1. Connect circuit as per the circuit diagram and give 5V DC power supply to input terminals.
2. Switch ON the power supply.
3. Change the state of J & K as per truth-table and note down the status of output at every stage as per
truth-table.
4. Closely watch the output.

OBSERVATIONS:

CONCLUSION:

Question:
a) What is registers? Explain SISO,SIPO,PISO,PIPO Shift register in Detail.
b) Explain Binary Ripple Counter in Detail.
c) Explain 4-bit UP/DOWN Binary counter.
d) Explain 4-bit Binary Counter with Parallel Load.
e) Explain BCD Ripple Counter.
f) Explain Bi-directional Shift Register with Parallel Load

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PAGE : 28 Digital Electronics
 EXPERIMENT NO.: - 12
AIM: To study Master-Slave JK Flip flop circuit.

THEORY:

One way to solve racing problem in JK flip flop is to use Master/slave JK flip flop circuit. This type of flip-
flop circuit is used mostly in counting devices. As shown in the figure there are two JK flip-flop one is
Master and other is slave. Master is positively edge triggered and the slave is negatively edge triggered.
Therefore the master responds to its J & K inputs before the slave.

For example if J=1 & K=0 the master flip-flop SETS on positive edge of the applied clock pulse. The high
output of master (y=1) drives the J input of slave. As slave is negative triggered flip-flop, on the negative
edge of the clock pulse the slave flip-flop sets i.e. it follows master. Thus by any state of master will
be copied by slave on negative edge of clock pulse. The change in output of master will be according to the
level of J, K and positive edge of clock pulse applied.

In short, if master Sets, the slave Sets and if Master Resets, the slave Resets. The 54LS74 and 74LS76 is a
dual JK master/slave flip-flops widely used.

EQUIPMENT REQUIRED:
-Trainer kit

COMPONENTS REQUIRED:
 IC 7473 (JK flip flop)
 IC 7400 (for clock)
 Hook up wires.

PROCEDURE:
1. Connect circuit as per the circuit diagram and give 5V DC power supply to input terminals.
2. Switch ON the power supply.
3. Set J=1 & K=0 of master and press clock micro switch (keep on pressing so that only positive edge
is applied). Observe the output of master Y=1 and Y bar =0.
4. Now release the micro switch so that negative edge of the clock is applied to slave. Observe that
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PAGE : 29 Digital Electronics
 outputs of slave, they will be as per the outputs of master.
5. With different value of J & K of master repeat the above procedure and see that slave always follows
master.

OBSERVATIONS:

CONCLUSION:

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PAGE : 30 Digital Electronics