Scribd
Upload
35 views10 pages

Eepc-301 L4

Uploaded by

sugardad0728
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
35 views10 pages

Eepc-301 L4

Uploaded by

sugardad0728
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 10

EEPC-301: MICROPROCESSORS AND

INTERFACING

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23


INTEL 8085A PIN Cofiguration
 The 8085A is a 8- bit
microprocessor suitable for a
wide range of application. It is
a:
 40-pin DIP (Dual in package)
chip
 based on NMOS technology
 contains approximately 6200
transistors on164 x 222 mil
chip.

 Microprocessor requires a
single +5V supply between Vcc
at pin no. 40 and Vss at pin no.
20.
Fig. Pin Configuration of Intel 8085A Microprocessor

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 2


INTEL 8085A PIN Cofiguration
A15 – A8 at pin no. 28 to pin no. 21:
 The microprocessor can address directly 216 memory locations or 65536 memory locations or 64k
memory locations using 16-address lines (A15-A0).
 Pin no. 28 to pin no. 21 give us the higher order 8-bits of the address (A15-A8). These address lines
are unidirectional, tri-state address lines.

AD7–AD0 at pin no. 19 to pin no. 12:


 Pin no. 19 to pin no.12 marked AD7–AD0 are used for dual purpose.

 It is time multiplexed lower 8-bit address bus (A7-A0) and 8-bit data bus (D7-D0).

ALE at Pin No 30:


 The 8085A uses a time multiplexed address-data bus.
 ALE stands for address latch enable. It is used to distinguish whether the AD7 – AD0 bus contains
address bits A7 – A0 or data bits D7- D0.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 3


INTEL 8085A PIN Cofiguration

 The BDB at pin no 19 to 12 are used for bi-directional data transfer operation.

 When the BDB is inputting the information from the external world into the microprocessor, we say
that 𝜇𝑝 is in READ mode and operation is READ operation.
 When the 𝜇𝑝 is outputting 8-bit of information to the external world through BDB we say 𝜇𝑝 is in
WRITE mode and operation is WRITE operation.
 To tell the external world the microprocessor is in input mode for READ operation, it issues a control
signal which is normally HIGH and active LOW (when 𝜇𝑝 is in READ mode) .
 To tell the external world that 𝜇𝑝 is in WRITE mode, 𝜇𝑝 issues a control signal output at pin no.
31. It is normally HIGH & active LOW.
 Both and are never made LOW at the same time. Both the signals are tri-stated during
HOLD, HALT and RESET states.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 4


INTEL 8085A PIN Cofiguration

 Whenever the address issued by the 𝜇𝑝 on the address lines refers to the memory then the 𝜇𝑝
makes LOW to indicate the external world that the address so sent belongs to the memory
and data on the BDB refers to the memory.
 Whenever the address on the address lines refers to an I/O device the 𝜇𝑝 makes control
signal output HIGH to tell the external world that the address on the address bus refers to an I/O
device and the data on the BDB refers to an I/O device.

READY at PIN NO 35:


 This is a control signal input. There are many peripheral devices which are slow in operation
compared to the microprocessor speed.
 There is a need for telling the 𝜇𝑝 that the device so addressed by the 𝜇𝑝 is not ready for data
transfer operation. The device, selected should have the ability to generate a control signal output
READY which shall be LOW if the device is not ready for data transfer operation and goes HIGH
when the device is READY for data transfer operation.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 5


INTEL 8085A PIN Cofiguration

 It is an input control signal normally HIGH and active LOW. It is used to RESET the microprocessor
to its initial state.

RESET OUT at Pin no.3:


 It is normally low signal output. It indicates 8085A is being RESET.
 When control signal at pin no. 36 is LOW, RESET OUT at pin no.3 goes HIGH. It remains
HIGH as long as is active and LOW.
 RESET OUT control signal is provided for the user to use it to RESET all the peripheral devices to
their initial states.

X1, X2 terminal at pin nos.1 & 2 and CLK(OUT) at pin no.37:


 The 8085A μ𝑝 has an on-chip oscillator with all the required circuitry except for the crystal (or RC,
LC network) that controls the operating frequency. A crystal is connected across X1 and X2 to
provide a crystal frequency of fcrystal MHz.
 The frequency is internally divided by two: therefore to operate a system at 3 MHz, the crystal
should have a frequency of 6 MHz.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 6


INTEL 8085A PIN Cofiguration
CLK(OUT) at pin no.37:
 Clock output can be used as the system clock for other devices.

 CLK(OUT) signal is used for synchronizing the peripheral devices with the μ𝑝 operation.

SID & SOD at PIN NO 5 & 4:


 SID stands for SERIAL INPUT DATA and SOD stands for SERIAL OUTPUT DATA. These two pins
are specially provided in 8085 𝜇𝑝 for communicating with serial devices, like CRT, TTY, and Printers
etc.
 Microprocessor as and when needed uses SID and SOD lines for transfer of data bit by bit along
the same lines.

Status Signals S1 (33) and S0 (29):


 These two status signals along with signal output identify the type of the machine cycle being
executed by the 8085A.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 7


INTEL 8085A PIN Cofiguration
INTERRUPT CONTROL SIGNALS:
 TRAP at pin no. 6, RST7.5 at pin no. 7, RST6.5 at pin no. 8, RST 5.5 at pin no. 9, and INTR at pin
no. 10 are interrupt control signals input provided for interrupting the 𝜇𝑝 while it is executing the
program.
 RST stands for RESTART. These interrupt control signal input can be broadly divided in to two
categories:
(a) Non – maskable interrupts
(b) Maskable interrupts
 Non–maskable control signal inputs are those control signal inputs which can interrupt the 𝜇𝑝
programming execution once the power is ON. The maskable interrupts are those control signal
inputs which can be individually disabled or enabled as and when necessary.

 TRAP at pin no.6:

 TRAP control signal input of Intel 8085A processors is a non-maskable (NMI) RESTART vectored
interrupt. When the power is ON, it is enabled and no enable interrupt command is required. TRAP
has the highest priority of any interrupt.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 8


INTEL 8085A PIN Cofiguration
 INTR at pin no.10:

 This is the lowest priority interrupt request in the 8085A processor and is used as a general
purpose interrupt. An input of INTR=1 implies some external device has put up an interrupt and
wants the CPU to execute an appropriate service routine.

 RST5.5, RST6.5 & RST 7.5:

 These are 8085A’s maskable vectored interrupt inputs. Among these three, RST 7.5 has the
highest priority and RST 5.5 has the lowest priority.

 at pin no.11:
 is an Interrupt acknowledge control signal output. This is an active LOW control signal output.
 When the μ𝑝 acknowledges any interrupt than instead of signal it issues signal to tell the
external world that processor is now processing an interrupt acknowledge machine cycle.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 9


INTEL 8085A PIN Cofiguration
HOLD at pin no 39 and HLDA at pin no 38:
 HOLD (Hold) is a control signal input and HLDA (Hold acknowledge) is a control signal output.
These two signals are used for hand-shaked control during DMA operation (Direct Memory
Access).
 These two signals are used where there is more than one CPU like devices sharing the same
system bus. The device asking for DMA makes the HOLD signal input HIGH. while entering the
HOLD state the μ𝑝 issues the HOLD acknowledge signal HLDA high at pin no. 38.

Dr. Asha Sharma (Ph.D., IIT Kanpur) Aug-23 10

You might also like