VLSI REPORT

Pratish Kumar (22BEC034)

Zubair Khan (22BEC027)
Rakesh Patidar (22BEC039)

1. Introduction
In digital design, especially when working with FPGA systems, it is
often useful to display computed results in real-time. This project
demonstrates the design and implementation of a 4-bit binary adder on
an FPGA, with the result shown on a 7-segment display embedded in
the FPGA board. This setup provides an efficient way to visually verify
the outcome of the addition operation directly from the hardware.

2. Objectives
The primary objectives of this project are:
• To design and implement a 4-bit binary adder circuit on an FPGA.
• To convert the binary output of the adder to a format suitable for
driving a 7-segment display.
• To use the embedded 7-segment display on the FPGA board for
real-time visualization of the addition result.

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3. FPGA-Embedded 7-Segment Display
The FPGA board’s 7-segment display provides an immediate visual
interface to observe the output of the 4-bit adder. This display consists
of seven LEDs arranged in a pattern to represent decimal numbers (0-
9) and hexadecimal characters (A-F).
Each LED segment (labeled A to G) is controlled by a specific signal
to illuminate the segments that form each character. The display on
the FPGA board is commonly configured for active-low control signals,
where a ‘0’ lights up the segment, and a ‘1’ turns it off.

4. Design and Implementation

4.1 4-Bit Adder Circuit
The adder circuit was designed using a ripple-carry adder configura-
tion, consisting of four full adders that compute the sum of two 4-bit
binary inputs. Each full adder computes a single bit of the result while
propagating the carry to the next adder in the sequence. The sum is
represented as a 4-bit binary value, which is then fed into a 7-segment
display decoder for visualization.

4.2 7-Segment Decoder for FPGA Display

The 7-segment decoder module translates the 4-bit binary sum output
into control signals for the FPGA’s embedded 7-segment display. Each
4-bit binary output corresponds to a unique 7-segment configuration,
allowing the display to accurately represent results in hexadecimal for-
mat, from 0 (0000) to F (1111). The decoder converts each binary
input into the appropriate set of signals that control which segments
(labeled A to G) are illuminated.

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4.3 Implementation on FPGA
The design was coded in Verilog and verified through simulation to
ensure accurate addition and display. After successful simulation,
the code was synthesized and implemented on the FPGA. Once pro-
grammed, the addition results were displayed in real-time on the FPGA
board’s embedded 7-segment display, enabling a straightforward ver-
ification of the adder’s functionality by observing each possible sum
directly on the hardware.

5. Code:
module top_module(
input [3:0] a,
input [3:0] b,
input cin,
input enable,
output [6:0] seg,
output [15:0] led
);

wire [3:0] sum;

wire cout;

four_bitadder u4 (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);

seven_segment_decoder u6 (
.sum(sum),
.enable(enable),
.seg(seg)
);

assign led[0] = a[0];

assign led[1] = a[1];
assign led[2] = a[2];
assign led[3] = a[3];

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 assign led[4] = b[0];
assign led[5] = b[1];
assign led[6] = b[2];
assign led[7] = b[3];
assign led[8] = cin;
assign led[9] = cout;
assign led[10] = enable;
assign led[11] = 0;
assign led[12] = 0;
assign led[13] = 0;
assign led[14] = 0;
assign led[15] = 0;

endmodule
‘timescale 1ns / 1ps

module one_bit_fulladder(
input a,
input b,
input cin,
output sum,
output cout
);
assign sum = (a ^ b) ^ cin;
assign cout = b & cin | a & cin | a & b;
endmodule
module four_bitadder(
input [3:0] a,
input [3:0] b,
input cin,
output [3:0] sum,
output cout
);

wire [3:0] carry;

one_bit_fulladder u0(a[0], b[0], cin, sum[0], carry[0]);

one_bit_fulladder u1(a[1], b[1], carry[0], sum[1], carry[1]);
one_bit_fulladder u2(a[2], b[2], carry[1], sum[2], carry[2]);
one_bit_fulladder u3(a[3], b[3], carry[2], sum[3], carry[3]);

assign cout = carry[3];

endmodule
module seven_segment_decoder (

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 input [3:0] sum,
input enable,
output reg [6:0] seg
);

always @(*) begin

if (enable) begin
case (sum)
4’b0000: seg = 7’b0000001;
4’b0001: seg = 7’b1001111;
4’b0010: seg = 7’b0010010;
4’b0011: seg = 7’b0000110;
4’b0100: seg = 7’b1001100;
4’b0101: seg = 7’b0100100;
4’b0110: seg = 7’b0100000;
4’b0111: seg = 7’b0001111;
4’b1000: seg = 7’b0000000;
4’b1001: seg = 7’b0000100;
4’b1010: seg = 7’b0001000;
4’b1011: seg = 7’b1100000;
4’b1100: seg = 7’b0110001;
4’b1101: seg = 7’b1000010;
4’b1110: seg = 7’b0110000;
4’b1111: seg = 7’b0111000;
default: seg = 7’b0000001;
endcase
end else begin
seg = 7’b1111111;
end
end
endmodule

Constraints for Top Module (LEDs and 7-segment Display)

# Assign switches a[0] to a[3] (for inputs a[3:0])
set_property PACKAGE_PIN V17 [get_ports {a[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {a[0]}]

set_property PACKAGE_PIN V16 [get_ports {a[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {a[1]}]

set_property PACKAGE_PIN W16 [get_ports {a[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {a[2]}]

set_property PACKAGE_PIN W17 [get_ports {a[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {a[3]}]

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# Assign switches b[0] to b[3] (for inputs b[3:0])
set_property PACKAGE_PIN W15 [get_ports {b[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {b[0]}]

set_property PACKAGE_PIN V15 [get_ports {b[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {b[1]}]

set_property PACKAGE_PIN W14 [get_ports {b[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {b[2]}]

set_property PACKAGE_PIN W13 [get_ports {b[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {b[3]}]

# Assign push button cin (Carry-in)

set_property PACKAGE_PIN R2 [get_ports {cin}]
set_property IOSTANDARD LVCMOS33 [get_ports {cin}]

# Assign switch for enable signal

set_property PACKAGE_PIN T1 [get_ports {enable}]
set_property IOSTANDARD LVCMOS33 [get_ports {enable}]

# Assign LEDs led[0] to led[7] for input bits a and b

set_property PACKAGE_PIN U16 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]

set_property PACKAGE_PIN E19 [get_ports {led[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]

set_property PACKAGE_PIN U19 [get_ports {led[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]

set_property PACKAGE_PIN V19 [get_ports {led[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]

set_property PACKAGE_PIN W18 [get_ports {led[4]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]

set_property PACKAGE_PIN U15 [get_ports {led[5]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]

set_property PACKAGE_PIN U14 [get_ports {led[6]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]

set_property PACKAGE_PIN V14 [get_ports {led[7]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]

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# Assign LEDs led[8] to led[10] for cin, cout, and enable
set_property PACKAGE_PIN V13 [get_ports {led[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]

set_property PACKAGE_PIN W3 [get_ports {led[15]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]

set_property PACKAGE_PIN V3 [get_ports {led[14]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]

# Assign remaining LEDs to 0 (or other values as needed)

set_property PACKAGE_PIN N3 [get_ports {led[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]

set_property PACKAGE_PIN P3 [get_ports {led[12]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]

set_property PACKAGE_PIN U3 [get_ports {led[13]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]

set_property PACKAGE_PIN L1 [get_ports {led[8]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]

set_property PACKAGE_PIN P1 [get_ports {led[10]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]

# Assign 7-segment display pins (seg[6:0]) to the corresponding FPGA pins

set_property PACKAGE_PIN U7 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]

set_property PACKAGE_PIN V5 [get_ports {seg[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]

set_property PACKAGE_PIN U5 [get_ports {seg[2]}]

set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]

set_property PACKAGE_PIN V8 [get_ports {seg[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]

set_property PACKAGE_PIN U8 [get_ports {seg[4]}]

set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]

set_property PACKAGE_PIN W6 [get_ports {seg[5]}]

set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]

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set_property PACKAGE_PIN W7 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]

Block Diagram of 4-Bit Adder and 7-Segment Dis-

play

Figure 1: Diagram of the 4-bit Adder and 7-Segment Display on FPGA

5. Results
The 4-bit adder and decoder performed accurately, correctly comput-
ing the sum of two 4-bit binary numbers and displaying the result on
the embedded 7-segment display of the FPGA. This integration allowed
for real-time monitoring of the adder’s performance, with all possible
sums (from 0 to 15) correctly represented in hexadecimal format. The
FPGA board, which hosted both the adder logic and the display, served
as an effective platform for computation and output display, ensuring

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that the entire process from calculation to visualization was seamless.
This functionality was verified through simulation and FPGA pro-
gramming, with results observed directly on the hardware. The ability
to see the sum in real-time on the 7-segment display made it easier
to troubleshoot and confirm that the adder was working as expected.
Additionally, the display’s active-low configuration was validated, en-
suring that each segment of the display was correctly illuminated based
on the binary sum.
Overall, the project demonstrated the FPGA’s capabilities in per-
forming both computational tasks and displaying results, making it a
valuable platform for real-time embedded systems.

6. Conclusion
The project successfully demonstrated the design, implementation, and
testing of a 4-bit binary adder circuit, with the results displayed on an
FPGA’s embedded 7-segment display. This integration allowed for
efficient and accurate real-time monitoring of the computation, show-
casing the ability of FPGA systems to handle both arithmetic compu-
tations and output visualization simultaneously.
The use of a ripple-carry adder, combined with the 7-segment dis-
play decoder, provided a simple yet effective solution to the problem of
visualizing computation results on hardware. Furthermore, the flexibil-
ity and reconfigurability of the FPGA were key factors in the project’s
success, offering the potential for further enhancements, such as the
addition of more complex arithmetic operations or user interfaces.
This project highlights the versatility of FPGA technology for em-
bedded system design, especially for applications requiring real-time
computation and feedback. It serves as a solid foundation for more ad-
vanced embedded system projects, providing insight into the potential
of FPGA-based solutions for computational tasks, data visualization,

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and hardware interfacing.

7. References
• Brown, S., & Vranesic, Z. (2009). Fundamentals
of Digital Logic with Verilog Design. McGraw-
Hill Education.
This textbook provides a solid foundation in digital logic design principles and offers detailed
tutorials on FPGA-based design using Verilog. It includes explanations of arithmetic circuits,
such as adders, and how to interface with display modules like 7-segment displays, making it
a crucial reference for FPGA design projects.

• Wakerly, J. F. (2017). Digital Design: Princi-

ples and Practices (5th Edition). Pearson.
This book is a comprehensive resource on digital design, covering topics such as adders,
arithmetic circuits, and FPGA applications. It also includes practical examples of 7-segment
display interfacing in digital systems, offering readers a thorough understanding of digital
design principles and practices applicable to FPGA implementations.

• Xilinx (or Altera) FPGA User Guide.

The FPGA board manufacturers, such as Xilinx and Intel Altera, provide detailed user guides
and reference manuals for using the board’s embedded peripherals, including 7-segment dis-
plays. These guides are essential for understanding how to program and interface with FPGAs
using Verilog or VHDL, and they provide the necessary tools for integrating peripherals and
programming the FPGA.

• FPGA-Based 4-Bit Adder Project Tutorials.

Several online resources, including FPGA4Student, Digi-Key, and other FPGA project web-
sites, offer tutorials and project documentation for designing and implementing a 4-bit adder.
These tutorials often include step-by-step guides for simulating the design in FPGA software,
programming the FPGA board, and displaying results on an embedded 7-segment display.
These resources are practical and highly valuable for both beginners and advanced FPGA
developers.

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