Memory Organisation
Memory Organisation
Memory Organization
• The address bus lines are listed in the third column. Although there
are 16 lines in the address bus, the table shows only 10 lines
because the other 6 are not used in this example and are assumed to
be zero.
• The small x's under the address bus lines designate those lines that
must be connected to the address inputs in each chip.
• The RAM chips have 128 bytes and need seven address lines.
• The ROM chip has 512 bytes and needs 9 address lines.
• The x's are always assigned to the low-order bus lines: lines 1
through 7 for the RAM and lines 1 through 9 for the ROM.
• It is now necessary to distinguish between four RAM chips by
assigning to each a different address.
• For this particular example we choose bus lines 8 and 9 to represent
four distinct binary combinations.
• The table clearly shows that the nine low-order bus lines constitute
a memory space for RAM equal to 29 = 512 bytes.
• The distinction between a RAM and ROM address is done with
another bus line.
• When line 10 is 0, the CPU selects a RAM, and when this line is
equal to 1, it selects the ROM.
Memory Address Map
TABLE 4-1 Memory Address Map for Microprocomputer
Figure 4-4: Memory
connection to the CPU.
Auxiliary Memory
• The average time required to reach a storage location in memory
and obtain its contents is called the access time.
• In electromechanical devices with moving parts such as disks and
tapes, the access time consists of a seek time required to position
the read-write head to a location and a transfer time required
to transfer data to or from the device.
• Because the seek time is usually much longer than the transfer time,
auxiliary storage is organized in records or blocks.
• A record is a specified number of characters or words.
• Reading or writing is always done on entire records.
• The transfer rate is the number of characters or words that the
device can transfer per second, after it has been positioned at the
beginning of the record.
Associative Memory
• The time required to find an item stored in memory can be reduced
considerably if stored data can be identified for access by the
content of the data itself rather than by an address.
• A memory unit accessed by content is called an associative
memory or content addressable memory (CAM).
• This type of memory is accessed simultaneously and in parallel on
the basis of data content rather than by specific address or location.
• When a word is written in an associative memory, no address is
given. The memory is capable of finding an empty unused location
to store the word.
• When a word is to be read from an associative memory, the content
of the word, or part of the word, is specified.
• The memory locates all words which match the specified content
and marks them for reading.
Associative Memory
• The block diagram of an associative memory is shown in Fig. 4.6.
• It consists of a memory array and logic for m words with n bits per
word.
• The argument register A and key register K each have n bits, one
for each bit of a word.
• The match register M has m bits, one for each memory word.
• Each word in memory is compared in parallel with the content of
the argument register.
• The words that match the bits of the argument register set a
corresponding bit in the match register.
• After the matching process, those bits in the match register that
have been set indicate the fact that their corresponding words have
been matched.
• Reading is accomplished by a sequential access to memory for
those words whose corresponding bits in the match register have
Associative Memory
• The cache memory access time is less than the access time of main
memory by a factor of 5 to 10.