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2-Channel Audio Processor IC PT2315

DESCRIPTION
PT2315 is a two-channel digital audio processor utilizing CMOS Technology. Volume, Bass, Treble
and Balance Controls are incorporated into a single chip. Loudness Function is also provided to build a
highly effective electronic audio processor having the highest performance and reliability with the least
external components. All functions are programmable using the I2C Bus. The pin assignments and
application circuit are optimized for easy PCB layout and cost saving advantage for audio application.
Housed in a 20-pin DIP/SOP, PT2315 is pin-to-pin compatible with TDA7315 and is very similar in
performance with the later.

FEATURES
z CMOS technology
z Least external components
z Treble and Bass control
z Loudness function
z Input/output for external noise reduction system/equalizer
z 2 independent speaker controls for Balance function
z Independent mute function
z Volume control in 1.25dB/step
z Low distortion
z Low noise and DC stepping
z Controlled by I2C bus micro-processor interface
z Pin-to-pin compatible with TDA7315

APPLICATIONS
z Car stereo (Audio)
z Hi-Fi audio system
z Can be used in all I2C system applications

Note:
Purchase of I2C Component of Princeton Technology Corporation (PTC) conveys a license under
Philips I2C Patent Right to use these components in any I2C System, provided that the system
conforms to the I2C Standard Specification defined by Philips

PT2315 V1.2 -1- March, 2006

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2-Channel Audio Processor IC PT2315

BLOCK DIAGRAM
L OU D_ L B O UT_ L B IN_L TRE B _L
9 13 12 4

RB

Vo lu me S pe ake r
& ATT
L IN 11 B ass Tre ble
L ou d ne ss
17 L OU T

Mu te

20 CL K
S er ial B u s D eco de r & La tch e s 19 DATA
18 DG ND

S pe ake r
ATT
Vo lu me
B ass Tre ble
RIN 6 &
L ou d ne ss 16 RO UT

Mu te

RB

S up pl y

2 3 1 7 15 14 5

V DD A GN D RE F L OU D_R B OU T_R B IN _R TRE B _R

PT2315 V1.2 -2- March, 2006

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2-Channel Audio Processor IC PT2315

PIN CONFIGURATION

RE F 1 20 CLK

VD D 2 19 D ATA

AG N D 3 18 DGND

TR EB _ L 4 17 LOUT

TR EB_ R 5 16 ROUT
PT23 15
RIN 6 15 BO U T_ R

LOUD_ R 7 14 BI N _ R

NC 8 13 BO U T_ L

LOUD _L 9 12 BI N _ L
N C 10 11 L IN

PT2315 V1.2 -3- March, 2006

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2-Channel Audio Processor IC PT2315

PIN DESCRIPTION
Pin Name I/O Description Pin No.
REF - Analog Reference Voltage (1/2 VDD) 1
VDD - Supply Input Voltage 2
AGND - Analog Ground 3
TREB_L I Left Channel Input for Treble Controller 4
TREB_R I Right Channel Input for Treble Controller 5
RIN I Audio Processor Right Channel Input 6
LOUD_R I Right Channel Loudness Input 7
LOUD_L I Left Channel Loudness Input 9
LIN I Audio Processor Left Channel Input 11
BIN_L I Left Bass Controller Input Channel 12
BOUT_L O Left Bass Controller Output Channel 13
BIN_R I Right Bass Controller Input Channel 14
BOUT_R O Right Bass Controller Output Channel 15
ROUT O Right Speaker Output 16
LOUT O Left Speaker Output 17
DGND - Digital Ground 18
DATA I Control Data Input 19
CLK I Clock Input for Serial Data Transmission 20
NC - No Connection 8, 10

PT2315 V1.2 -4- March, 2006

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2-Channel Audio Processor IC PT2315

FUNCTION DESCRIPTION
I2C BUS INTERFACE
Data are transmitted to and from the microprocessor to the PT2315 via the DATA and CLK. The DATA
and CLK make up the BUS Interface.

DATA VALIDITY
A data on the DATA Line is considered valid and stable only when the CLK Signal is in HIGH State. The
HIGH and LOW State of the DATA Line can only change when the CLK signal is LOW. Please refer to
the figure below.

DATA

CLK
DATA LINE DATA
STABLE, CHANGE
DATA VALID ALLOWED

START AND STOP CONDITIONS

A Start Condition is activated when
1. CLK is set to HIGH and
2. DATA shifts from HIGH to LOW State.

The Stop Condition is activated when

1. CLK is set to HIGH and
2. DATA shifts from LOW to HIGH State

Please refer to the timing diagram below.

CLK

DATA

START ST OP

PT2315 V1.2 -5- March, 2006

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2-Channel Audio Processor IC PT2315

BYTE FORMAT
Every byte transmitted to the DATA Line consist of 8 bits. Each byte must be followed by an
Acknowledge Bit. The MSB is transmitted first.

ACKNOWLEDGE
During the Acknowledge Clock Pulse, the master (µP) puts a resistive HIGH level on the DATA Line.
The peripheral (audio processor) that acknowledges has to pull-down (LOW) the DATA line during the
Acknowledge Clock Pulse so that the DATA Line is in a Stable Low State during this Clock Pulse.
Please refer to the diagram below.

CLK 1 2 3 4 7 8 9

DATA MSB

AC KNOWLED GE MENT
START F ROM RECE IV ER

The audio processor that has been addressed has to generate an acknowledge after receiving each
byte, otherwise, the DATA Line will remain at the High Level during the ninth (9th) Clock Pulse. In this
case, the master transmitter can generate the STOP Information in order to abort the transfer.

TRANSMISSION WITHOUT ACKNOWLEDGE

If you want to avoid the acknowledge detection of the audio processor, a simpler µP transmission may
be used. Wait one clock and do not check the slave acknowledge of this same clock then send the new
data. If you use this approach, there are greater chances of faulty operation as well as decrease in
noise immunity.

PT2315 V1.2 -6- March, 2006

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2-Channel Audio Processor IC PT2315

INTERFACE PROTOCOL
The interface protocol consists of the following:
• A Start Condition
• A Chip Address Byte including the PT2315 address. The 8th Bit of the Byte must be “0”. PT2315
must always acknowledge the end of each transmitted byte.
• A Data Sequence (N-Bytes + Acknowledge)
• A Stop Condition

Please refer to the diagram below:

P T2315 A DD RE SS

MS B FIRS T B YTE LS B MS B LS B MS B LS B
S TA RT 1 0 0 0 1 0 0 0 A CK DATA A CK DATA A CK S TOP
DATA TRA NS MITTE D (N-BY TES + A CK NOW LE DGE )

Notes:
1. ACK=Acknowledge
2. Max. Clock Speed=100Bits/s

PT2315 V1.2 -7- March, 2006

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2-Channel Audio Processor IC PT2315

SOFTWARE SPECIFICATION
PT2315 ADDRESS
PT2315 Address is shown below.

1 0
0 0 0 0 0 0
MSB LSB

DATA BYTES
MSB LSB Function
0 0 B2 B1 B0 A2 A1 A0 Volume Control
1 0 0 B1 B0 A2 A1 A0 Speaker ATT L
1 0 1 B1 B0 A2 A1 A0 Speaker ATT R
0 1 0 * * L * * Loudness Control
0 1 1 0 C3 C2 C1 C0 Bass Control
0 1 1 1 C3 C2 C1 C0 Treble Control
where Ax=1.25 dB steps; Bx=10 dB steps; Cx=2 dB steps; * =no effect

I2C BUS INTERFACE START TIME

After Power is turned ON, PT2315 needs to wait for a short time in order to insure stability. This waiting
period is relative to the value of Cref. As the Cref value is 10µf, the waiting time period for PT2315 to
send I2C Bus Signal is at least 300ms. If the waiting time period is less than 300ms, I2C Control may fail.
Please refer to the diagram below.

V POWER ON

90% VDD

VDD
at least 300ms

SDA/SCL

PT2315 V1.2 -8- March, 2006

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2-Channel Audio Processor IC PT2315

VOLUME
The table below gives a detailed description of the Volume Data Bytes. For example, a volume of -37.5
dB is given by 0 0 0 1 1 1 1 0.
MSB LSB Function
0 0 B2 B1 B0 A2 A1 A0 Volume 1.25dB steps
0 0 0 0
0 0 1 -1.25
0 1 0 -2.5
0 1 1 -3.75
1 0 0 -5
1 0 1 -6.25
1 1 0 -7.5
1 1 1 -8.75
0 0 B2 B1 B0 A2 A1 A0 Volume 10dB steps
0 0 0 0
0 0 1 -10
0 1 0 -20
0 1 1 -30
1 0 0 -40
1 0 1 -50
1 1 0 -60
1 1 1 -70

SPEAKER ATTENUATORS
The table below gives a detailed description of the speaker attenuators data bytes. For example, an
attenuation of 30dB on the Speaker L (Left) is given by 1 0 0 1 1 0 0 0.
MSB LSB Function
1 0 0 B1 B0 A2 A1 A0 Speaker L
1 0 1 B1 B0 A2 A1 A0 Speaker R
0 0 0 0
0 0 1 -1.25
0 1 0 -2.5
0 1 1 -3.75
1 0 0 -5
1 0 1 -6.25
1 1 0 -7.5
1 1 1 -8.75
0 0 0
0 1 -10
1 0 -20
1 1 -30
1 1 1 1 1 Mute

PT2315 V1.2 -9- March, 2006

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2-Channel Audio Processor IC PT2315

LOUDNESS FUNCTION
The following table shows the detailed description of the Loudness Function. For example, when the
Loudness Function is turned ON, the code format is 0 1 0 0 0 0 0 0.
MSB LSB Function
0 1 0 * * L * * Loudness Control
0 Loudness ON
1 Loudness OFF
Note: *=No Effect

BASS AND TREBLE DATA BYTES

The following table shows a detailed description of the Bass and Treble Data Byte. For example a
Treble at -12dB is given by 0 1 1 1 0 0 0 1.
MSB LSB Function
0 1 1 0 C3 C2 C1 C0 Bass
0 1 1 1 C3 C2 C1 C0 Treble
0 0 0 0 -14
0 0 0 1 -12
0 0 1 0 -10
0 0 1 1 -8
0 1 0 0 -6
0 1 0 1 -4
0 1 1 0 -2
0 1 1 1 0

1 1 1 1 0
1 1 1 0 2
1 1 0 1 4
1 1 0 0 6
1 0 1 1 8
1 0 1 0 10
1 0 0 1 12
1 0 0 0 14

PT2315 V1.2 - 10 - March, 2006

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2-Channel Audio Processor IC PT2315

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min. Max. Unit
Operating supply voltage Vs 10.5 V
Input current, any pin except supplies Iin -10 10 mA
Input voltage (see Note) Vin -0.3 VS+0.3 V
Operating temperature Topr -40 85 ℃
Storage temperature Tstg -65 150 ℃

QUICK REFERENCE DATA

Parameter Symbol Min. Typ. Max. Unit
Supply voltage VS 6 9 10 V
Max. input signal handling VCL 2 2.5 - Vrms
Total harmonic distortion
THD - 0.07 0.15 %
(V=1Vrms, f=1KHz)
Signal to noise ratio S/N - 95 - dB
Channel separation
Sc - 85 - dB
(f=1KHz)
Volume control 1.25dB step - -75 - 0 dB
Bass & Treble control 2dB step - -14 - +14 dB
Balance control 1.25dB step - -37.5 - 0 dB
Mute attenuation - - 75 - dB

PT2315 V1.2 - 11 - March, 2006

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2-Channel Audio Processor IC PT2315

ELECTRICAL CHARACTERISTICS
(Unless specified: Ta=25℃, VDD=9V, RL=100KΩ, Rg=600Ω, all controls flat<G=0>, f=1KHz)
Parameter Symbol Test Condition Min. Typ. Max. Unit
Supply
Supply voltage VDD 6 9 10 V
Supply current IS - 30 40 mA
Volume Control
Input resistance RIV 20 30 40 KΩ
Control range CRANGE 65 70 75 dB
Min. attenuation AVMIN -1 0 1 dB
Max. attenuation AVMAX 65 70 75 dB
Step resolution ASTEP 0.5 1.25 1.75 dB
AV=0 to -20dB -1.25 1.25 dB
Attenuation set error EA 0
AV=-20 to -60dB -3.0 2 dB
Speaker Attenuators
Control range CRANGE 35 37.5 40 dB
Step resolution SSTEP 0.5 1.25 1.75 dB
Attenuation set error EA - - 1.5 dB
Output mute attenuation AMUTE 70 75 - dB
Bass Control (see Note)
Control range Gb Max. Boost/Cut ±12 ±14 ±16 dB
Step resolution BSTEP 1 2 3 dB
Internal feedback resistance RB 34 44 58 KΩ
Treble Control (see Note)
Control range Gt Max. Boost/Cut ±13 ±14 ±15 dB
Step resolution TSTEP 1 2 3 dB
Audio Outputs
Clipping level VOCL AV=-8.75dB, d=0.3% 2 2.5 - Vrms
Output resistance ROUT - 40 45 Ω
DC voltage level VOUT 4.2 4.5 4.8 V

PT2315 V1.2 - 12 - March, 2006

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2-Channel Audio Processor IC PT2315

Parameter Symbol Test Condition Min. Typ. Max. Unit

General
BW=20~20KHz,
-97 dB
Flat output muted - -
-92 dB
Output noise NO All gains=0dB
A Curve
- -100 - dB
All Gains=0dB
All Gains=0dB
Signal to noise ratio S/N - 95 - dB
VO=1Vrms
AV=0, VIN=1Vrms
AV=-8.75dB, 0.1 0.3 %
Distortion d VIN=1Vrms - 0.07 0.15 %
AV=-8.75dB, 0.03 0.1 %
VIN=0.3Vrms
Channel separation left/right Sc 80 90 - dB
Bus Inputs
Input low voltage VIL - - 1 V
Input high voltage VIH 3 - - V
Input current IIN -5 - +5 µA
Output voltage SDA acknowledge VO IO=1.6mA - - 0.4 V

Note:
For the Bass and Treble Response, please refer to the diagram below. The center frequency and
quality of the resonance behavior can be selected by the external circuitry. A standard first order bass
response can realized by a standard feedback network.

PT2315 V1.2 - 13 - March, 2006

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2-Channel Audio Processor IC PT2315

RESPONSE
(dB)

FREQUENCY

Typical Tone Response (with the ext. Components indicated in the test circuit)

dB

Hz

Loudness vs Volume Attenuation Frequency Response (C10=C11=100nF)

PT2315 V1.2 - 14 - March, 2006

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2-Channel Audio Processor IC PT2315

OPEN

10n
100n
dB
56n
220n 33n

Shorted to VREF

Hz

C10, C11 vs Loudness Frequency Response (Volume=-40dB, All other controls are flat)

PT2315 V1.2 - 15 - March, 2006

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2-Channel Audio Processor IC PT2315

APPLICATION CIRCUIT
R2
5.6K

MCU C4 C6 C7 C10
100n 100n 100n 2.7n

18 19 20 9 13 12 4
DGND DATA CLK LOUD_L BOUT_L BIN_L TREB_L
C2 C12
2.2µ R 10µ
+

11 RIN +
AM/FM LOUT 17
Tuner
6 LIN
+

C1 R
2.2µ

PT2315

+
ROUT 16
C13
10µ

VDD AGND REF LOUD_R BOUT_R BIN_R TREB_R

2 3 1 7 15 14 5

C3 + C5 C8 C9 C11
VDD 22µ 100n 100n 100n 2.7n

R1
5.6K

Notes:
1. The Resistor (R) range=2.0KΩ ~ 3.6KΩ.
2. Resistor (R) Recommended Value=2.4KΩ.

PT2315 V1.2 - 16 - March, 2006

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2-Channel Audio Processor IC PT2315

ORDER INFORMATION
Valid Part Number Package Type Top Code
PT2315 20 Pins, SOP, 300mil PT2315
PT1215-D 20 Pins, DIP, 300mil PT2315-D
PT2315 (L) 20 Pins, SOP, 300mil PT2315
PT2315-D (L) 20 Pins, DIP, 300mil PT2315-D

Notes:
1. (L), (C) or (S) = Lead Free.
2. The Lead Free mark is put in front of the data code.

PT2315 V1.2 - 17 - March, 2006

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2-Channel Audio Processor IC PT2315

PACKAGE INFORMATION
20 PINS, DIP, 300 MIL

PT2315 V1.2 - 18 - March, 2006

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2-Channel Audio Processor IC PT2315

Dimensions In Inches
Symbol
Min. Nom. Max.
A 0.210
A1 0.015
A2 0.115 0.130 0.195
b 0.014 0.018 0.022
b1 0.014 0.018 0.020
b2 0.045 0.060 0.070
b3 0.030 0.039 0.045
c 0.008 0.010 0.014
c1 0.008 0.010 0.011
D 0.980 1.030 1.060
D1 0.005
E 0.300 0.310 0.325
E1 0.240 0.250 0.280
e 0.100 bsc.
eA 0.300 bsc.
eB 0.430
eC 0.000 0.060
L 0.115 0.130 0.150
Notes:
1. All dimensions are in INCHES.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension”A”，”A1” and ”L”are measured with the package seated in JEDEC Seating Plane Gauge
GS-3
4. “D”，”D1” and “E1” dimensions do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.010 inch.
5. “E” and “eA” measured with the leads constrained to be perpendicular to datum -c- .
6. “eB” and “eC” are measured at the lead tips with the leads unconstrained.
7. N is the number of the terminal positions (N=20)
8. Pointed or rounded lead tips are preferred to ease insertion.
9. “b2” and “b3” maximum dimensions are not include dambar protrusions. Dambar protrusions shall
not exceed 0.010 inch (0.25mm)
10. Distance between leads including Dambar protrusions to be 0.005 inch minimum.
11. Datum plane -H- coincident with the bottom of lead, where lead exits body.
12. Refer to JEDEC MS-001, Variation AD.
JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.

PT2315 V1.2 - 19 - March, 2006

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2-Channel Audio Processor IC PT2315

20 PINS, SOP, 300MIL

Dimensions In Millimeter
Symbol
Min. Nom. Max.
A 2.35 2.65
A1 0.10 0.30
B 0.33 0.51
C 0.23 0.32
D 12.60 13.00
E 7.40 7.60
e 1.27 bsc.
H 10.00 10.65
h 0.25 0.75
L 0.40 1.27
α 0° 8°

PT2315 V1.2 - 20 - March, 2006

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2-Channel Audio Processor IC PT2315

Notes:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold Flash, protrusion or gate
burrs shall not exceed 0.15mm (0.006 in) per side.
3. Dimension “E” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25mm (0.010 in) per side.
4. The chamfer on the body is optional. It is not present, a visual index feature must be located within
the crosshatched area.
5. “L” is the length of the terminal for soldering to a substrate.
6. N is the number of the terminal positions (N=20)
7. The lead width “B” as measured 0.36mm (0.014 in) or greater above the seating plane, shall not
exceed a maximum value of 0.61mm (0.24 in).
8. Controlling dimension: MILLIMETER.
9. Refer to JEDEC MS-013, Variation AC.
JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.

PT2315 V1.2 - 21 - March, 2006