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QUESTION BANK For 2nd Internals

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22 views2 pages

QUESTION BANK For 2nd Internals

Uploaded by

Shrayanka s
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CAMBRIDGE INSTITUTE OF TECHNOLOGY

K.R. PURAM, BANGALORE – 560 036, Ph: 080-2561 8798 / 2561 8799
Fax: 080-2561 8789, email: [email protected]
Affiliated to VTU, Belagavi| Approved by AICTE, New Delhi| NAAC& NBA Accredited|
UGC 2(f) Certified| Recognized by Govt. of Karnataka

Department of Electronics and Communication Engineering

QUESTION BANK for 2nd Internals-2022

Course: VLSI DESIGN Semester: VII


Course Code: 18EC72 Section: A, B & C

S.No QUESTIONS CO’s RBT Mark


LEVEL s
S
1 What is scaling. Compute drain current, power, current density and power CO2 L2 10
density for constant field and constant voltage scaling
2 Draw the layout of 𝑌 = (A+B+C)D CO2 L2 8
3 Mention different types of MOSFET capacitances and explain with CO2 L2 6
necessary diagrams and equations.
4 With neat diagram, explain lambda based design rules for wires and CO2 L2 8
contacts.
5 CO2 L2 8
Draw the stick diagram and layout for .
6 What do you mean by  based design rules? List the design rules for CO2 L2 10
CMOS technology.
7 Explain following fabrication process a) Wafer Formation CO2 L2 10
b) Photolithography c) Well and Channel Formation d)Silicon Dioxide
(SiO2) layer formation.
8 Explain different types of MOSFET capacitances and derive the CO2 L2 10
expressions for the same.
9 Draw circuit diagram, stick diagram and layout diagram for CMOS CO2 L2 10
Inverter.
10 Draw circuit diagram, stick diagram and layout diagram for CMOS nor2 CO2 L2 10
gate.
11 What are the different techniques for silicon dioxide layer formation? CO2 L2 6
12 With neat diagram, explain czochralski process for wafer formation. CO2 L2 10
13 Explain Constant voltage scaling and obtain scaling factor for IDS in linear CO2 L2 10
and saturation.
14 With neat diagram, explain triple well process. CO2 L2 10
15 Explain Constant field scaling and obtain scaling factor for IDS in linear CO2 L2 10
and saturation
16 Explain Cgb, Cgs,Cgd of nMOS transistor in cutoff, linear and saturation. CO2 L2 10
17 Define Isolation and channel formation. CO2 L2 5
18 With neat diagram, explain photolithography process. CO2 L2 10

email: [email protected]: www.cambridge.edu.in Page 1


CAMBRIDGE INSTITUTE OF TECHNOLOGY
K.R. PURAM, BANGALORE – 560 036, Ph: 080-2561 8798 / 2561 8799
Fax: 080-2561 8789, email: [email protected]
Affiliated to VTU, Belagavi| Approved by AICTE, New Delhi| NAAC& NBA Accredited|
UGC 2(f) Certified| Recognized by Govt. of Karnataka

Department of Electronics and Communication Engineering

19 With neat diagram, explain the VLSI Design Flow. CO2 L2 10


20 Draw the Static CMOS circuit and obtain the Logical effort and parasitic CO2 L2 10
delay for Y = 𝐴̅ Y = ̅̅̅̅̅̅̅̅̅̅̅
𝐴. 𝐵 + 𝐶 Y = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴. 𝐵 + 𝐶. 𝐷

21 Explain Elmore delay model and also estimate tpd for unit inverter CO2 L2 10
driving m identical unit inverter with driver is w times unit size.
22 Define logical effort , Electrical effort and Parasitic delay. CO2 L2 6

23 Explain RC delay model and calculate propagation delay for inverter. CO2 L2 10
24 Derive an expression for delay in multistage path network with N CO2 L2 10
stage path effort F and parasitic delay P.
25 Estimate delay of NAND3 gate using linear delay model. CO2 L2 10
26 Derive minimum possible path delay of N-stage path with path effort CO2 L2 10
F and parasitic delay P.
27 Explain RC equivalent circuit for pMOS and nMOS and calculate load CO2 L2 10
Capacitance for two unit inverter.
28 Define Linear delay model. CO2 L2 5
29 Define the following terms CO2 L2 10
a)Propagation delay b) Contamination delay c) Rise time d) Fall time
30 Explain how to choose the best number of stages in the circuit. CO2 L2 10
31 Define Elmore delay model. CO2 L2 5

32 Explain following fabrication process a) Isolation b) Gate and CO2 L2 10


Source/Drain Formations c) Contacts and Metallization d) Passivation
e) Metrology.
33 Draw circuit diagram, stick diagram and layout diagram for CMOS nand2 CO2 L2 10
gate.
34 What is scaling. Compute drain current, power, current density and power CO2 L2 10
density for constant voltage scaling.
35 Explain short channel effects with neat diagram and related equations. CO2 L2 10
36 Explain narrow channel effects with neat a diagram and related equations. CO2 L2 8
37 Describe junction capacitance with all related equations. CO2 L2 10

Course Coordinators
Dr. Girish.H
Prof. Ravi Kumar M

email: [email protected]: www.cambridge.edu.in Page 2

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