/*

///////////////// bcd to seven segment display ///////////////////////////////////

module bcd_to_seven_segment(
input [3:0] bcd, // 4-bit BCD input
output reg [6:0] seg // 7-segment display output (a-g)
);

// Always block to determine the 7-segment display output based on the BCD
input
always @(bcd) begin
case (bcd)
4'b0000: seg = 7'b1111110; // 0
4'b0001: seg = 7'b0110000; // 1
4'b0010: seg = 7'b1101101; // 2
4'b0011: seg = 7'b1111001; // 3
4'b0100: seg = 7'b0110011; // 4
4'b0101: seg = 7'b1011011; // 5
4'b0110: seg = 7'b1011111; // 6
4'b0111: seg = 7'b1110000; // 7
4'b1000: seg = 7'b1111111; // 8
4'b1001: seg = 7'b1111011; // 9
default: seg = 7'b0000000; // Blank display for invalid inputs
endcase
end
endmodule

*/
/*

//////////////// sum of two two digit decimal number to 7 segment

display /////////////////////////

module add_and_display(
input [6:0] num1, // First 2-digit number (0-99)
input [6:0] num2, // Second 2-digit number (0-99)
output reg [6:0] seg_hundreds, // 7-segment output for hundreds place
output reg [6:0] seg_tens, // 7-segment output for tens place
output reg [6:0] seg_units // 7-segment output for units place
);
// Internal signals
reg [8:0] sum; // Sum can be up to 198 (fits in 8 bits)
reg [3:0] hundreds, tens, units;

// 7-Segment display lookup table (direct assignment without function)

always @(*) begin
// Add the two input numbers
sum = num1 + num2;

// Convert the binary sum to BCD format (hundreds, tens, and units)
hundreds = (sum / 100) % 10;
tens = (sum / 10) % 10;
units = sum % 10;
 // Convert each BCD digit to 7-segment output directly
case (hundreds)
4'b0000: seg_hundreds = 7'b1111110; // 0
4'b0001: seg_hundreds = 7'b0110000; // 1
4'b0010: seg_hundreds = 7'b1101101; // 2
4'b0011: seg_hundreds = 7'b1111001; // 3
4'b0100: seg_hundreds = 7'b0110011; // 4
4'b0101: seg_hundreds = 7'b1011011; // 5
4'b0110: seg_hundreds = 7'b1011111; // 6
4'b0111: seg_hundreds = 7'b1110000; // 7
4'b1000: seg_hundreds = 7'b1111111; // 8
4'b1001: seg_hundreds = 7'b1111011; // 9
default: seg_hundreds = 7'b0000000; // Blank for invalid input
endcase

case (tens)
4'b0000: seg_tens = 7'b1111110; // 0
4'b0001: seg_tens = 7'b0110000; // 1
4'b0010: seg_tens = 7'b1101101; // 2
4'b0011: seg_tens = 7'b1111001; // 3
4'b0100: seg_tens = 7'b0110011; // 4
4'b0101: seg_tens = 7'b1011011; // 5
4'b0110: seg_tens = 7'b1011111; // 6
4'b0111: seg_tens = 7'b1110000; // 7
4'b1000: seg_tens = 7'b1111111; // 8
4'b1001: seg_tens = 7'b1111011; // 9
default: seg_tens = 7'b0000000; // Blank for invalid input
endcase

case (units)
4'b0000: seg_units = 7'b1111110; // 0
4'b0001: seg_units = 7'b0110000; // 1
4'b0010: seg_units = 7'b1101101; // 2
4'b0011: seg_units = 7'b1111001; // 3
4'b0100: seg_units = 7'b0110011; // 4
4'b0101: seg_units = 7'b1011011; // 5
4'b0110: seg_units = 7'b1011111; // 6
4'b0111: seg_units = 7'b1110000; // 7
4'b1000: seg_units = 7'b1111111; // 8
4'b1001: seg_units = 7'b1111011; // 9
default: seg_units = 7'b0000000; // Blank for invalid input
endcase
end
endmodule
*/
/*

////////////////////D and TFlip Flop///////////////////////////////////////

module d_flip_flop (
input D, // Data input
input clk, // Clock input
input reset, // Asynchronous reset (active high)
output reg Q // Output
);

// Always block triggered by the rising edge of clock or reset

 always @(posedge clk or posedge reset) begin
if (reset) // If reset is high, reset output to 0
Q <= 0;
else
Q <= D; // On rising edge of clock, Q takes the value of D
end
endmodule

module t_flip_flop (
input T, // Toggle input
input clk, // Clock input
input reset, // Asynchronous reset (active high)
output reg Q // Output
);

// Always block triggered by the rising edge of clock or reset

always @(posedge clk or posedge reset) begin
if (reset) // If reset is high, reset output to 0
Q <= 0;
else if (T) // If T is high, toggle the output Q
Q <= ~Q;
end
endmodule

*/
/*

////////////////////////JK and SR Flipflop///////////////////////////////////////

module jk_flip_flop (
input J, // J input (Set)
input K, // K input (Reset)
input clk, // Clock input
input reset, // Asynchronous reset (active high)
output reg Q, // Output Q
output reg Q_bar // Output Q-bar (inverted output)
);

// Always block triggered by the rising edge of the clock or reset signal
always @(posedge clk or posedge reset) begin
if (reset) begin // Asynchronous reset: reset Q and Q_bar to 0
Q <= 0;
Q_bar <= 1;
end
else begin
case ({J, K})
2'b00: begin // No change state
Q <= Q;
Q_bar <= Q_bar;
end
2'b01: begin // Reset state
Q <= 0;
Q_bar <= 1;
end
2'b10: begin // Set state
Q <= 1;
Q_bar <= 0;
 end
2'b11: begin // Toggle state
Q <= ~Q; // Toggle the Q output
Q_bar <= ~Q_bar; // Toggle Q-bar as well
end
endcase
end
end
endmodule

module sr_flip_flop (
input S, // Set input
input R, // Reset input
input clk, // Clock input
input reset, // Asynchronous reset (active high)
output reg Q, // Output Q
output reg Q_bar // Output Q-bar (inverted output)
);

// Always block triggered by the rising edge of the clock or reset signal
always @(posedge clk or posedge reset) begin
if (reset) begin // Asynchronous reset: reset Q and Q_bar to 0
Q <= 0;
Q_bar <= 1;
end
else begin
case ({S, R})
2'b00: begin // No change state
Q <= Q;
Q_bar <= Q_bar;
end
2'b01: begin // Reset state
Q <= 0;
Q_bar <= 1;
end
2'b10: begin // Set state
Q <= 1;
Q_bar <= 0;
end
2'b11: begin // Invalid state: both set and reset high
// This is an invalid state and should not occur in practice
Q <= 1'bx; // Indeterminate value (X represents unknown state)
Q_bar <= 1'bx;
end
endcase
end
end
endmodule

*/
/*

////////////////////////COUNTER//////////////////////////////
module down_counter (
input clk, // Clock signal
 input reset, // Asynchronous reset (active high)
output [3:0] count // 4-bit counter output
);
reg [3:0] count_reg; // Register to store the counter value

// Always block for the down counter

always @(posedge clk or posedge reset) begin
if (reset)
count_reg <= 4'b1111; // Reset the counter to 15 (1111)
else
count_reg <= count_reg - 1; // Decrement the counter by 1
end

// Assign the counter register value to the output

assign count = count_reg;

endmodule

*/
/*

////////////////////////PIPO SIPO////////////////////

module pipo_shift_register (
input clk, // Clock input
input reset, // Reset input
input [7:0] parallel_in, // 8-bit parallel data input
output reg [7:0] parallel_out // 8-bit parallel data output
);

always @(posedge clk or posedge reset) begin

if (reset)
parallel_out <= 8'b00000000; // Reset the shift register
else
parallel_out <= parallel_in; // Load the data in parallel
end

endmodule

module sipo_shift_register (
input clk, // Clock input
input reset, // Reset input
input serial_in, // Serial data input
output reg [7:0] parallel_out // 8-bit parallel data output
);

reg [7:0] shift_reg; // 8-bit shift register to hold serial data

always @(posedge clk or posedge reset) begin

if (reset)
shift_reg <= 8'b00000000; // Reset the shift register
else
shift_reg <= {shift_reg[6:0], serial_in}; // Shift left and load the
new bit
end

always @(posedge clk) begin

 parallel_out <= shift_reg; // Output parallel data on each clock cycle
end

endmodule

*/
/*

//////////////////////////////RAM Implementation////////////////////

module ram #(
parameter ADDR_WIDTH = 4, // Address width (4 bits -> 16 addresses)
parameter DATA_WIDTH = 8, // Data width (8 bits per word)
parameter DEPTH = (1 << ADDR_WIDTH) // Depth of memory (16 locations)
)(
input wire clk, // Clock signal
input wire we, // Write enable signal
input wire [ADDR_WIDTH-1:0] addr, // Address input
input wire [DATA_WIDTH-1:0] data_in,// Data input
output reg [DATA_WIDTH-1:0] data_out// Data output
);

// Memory declaration with specified depth and data width

reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];

// Read and write operations

always @(posedge clk) begin
if (we) begin
// Write operation when write enable is high
mem[addr] <= data_in;
end
// Continuous read from the specified address
data_out <= mem[addr];
end
endmodule

*/
/*

////////////////////////////ROM implementation///////////////////////////
module rom(
input [2:0] address, // 3-bit address input
output reg [7:0] data // 8-bit data output
);
// Define the ROM contents
reg [7:0] rom_memory [7:0]; // 8 locations, each 8 bits wide

// Initialize the ROM with predefined values

initial begin
rom_memory[0] = 8'b00000001;
rom_memory[1] = 8'b00000010;
rom_memory[2] = 8'b00000100;
rom_memory[3] = 8'b00001000;
rom_memory[4] = 8'b00010000;
rom_memory[5] = 8'b00100000;
rom_memory[6] = 8'b01000000;
rom_memory[7] = 8'b10000000;
 end

// Read data based on address input

always @(*) begin
data = rom_memory[address];
end
endmodule
*/
/*

///////////////////////////FIFO////////////////////////

module fifo #(parameter DATA_WIDTH = 8, parameter DEPTH = 16) (

input clk, // Clock signal
input reset, // Reset signal
input write_en, // Write enable signal
input read_en, // Read enable signal
input [DATA_WIDTH-1:0] data_in, // Data to be written into FIFO
output reg [DATA_WIDTH-1:0] data_out, // Data read from FIFO
output reg full, // FIFO full flag
output reg empty // FIFO empty flag
);

// Memory array to store data

reg [DATA_WIDTH-1:0] fifo_mem [DEPTH-1:0];
reg [4:0] write_ptr = 0; // Write pointer
reg [4:0] read_ptr = 0; // Read pointer
reg [5:0] count = 0; // Data count in the FIFO

// Full and empty flags

always @(*) begin
full = (count == DEPTH);
empty = (count == 0);
end

// Write data to FIFO

always @(posedge clk or posedge reset) begin
if (reset) begin
write_ptr <= 0;
count <= 0;
end else if (write_en && !full) begin
fifo_mem[write_ptr] <= data_in;
write_ptr <= (write_ptr + 1) % DEPTH;
count <= count + 1;
end
end

// Read data from FIFO

always @(posedge clk or posedge reset) begin
if (reset) begin
read_ptr <= 0;
count <= 0;
data_out <= 0;
end else if (read_en && !empty) begin
data_out <= fifo_mem[read_ptr];
read_ptr <= (read_ptr + 1) % DEPTH;
count <= count - 1;
end
end
endmodule

*/
/*

////////////////////////Serial Adder///////////////////

module serial_adder_fsm(
input clk,
input rst,
input start,
input a, // Serial input for A
input b, // Serial input for B
output reg sum, // Serial output for sum
output reg done // Indicates completion of addition
);
// State encoding using parameters
parameter IDLE = 2'b00;
parameter ADD = 2'b01;
parameter DONE = 2'b10;

// Internal state registers

reg [1:0] current_state, next_state;

// Internal registers for addition

reg carry;
reg [3:0] bit_count; // Counter for the number of bits processed

// State transition logic (sequential block)

always @(posedge clk or posedge rst) begin
if (rst)
current_state <= IDLE;
else
current_state <= next_state;
end

// Next state logic (combinational block)

always @(*) begin
case (current_state)
IDLE: begin
if (start)
next_state = ADD;
else
next_state = IDLE;
end
ADD: begin
if (bit_count == 4)
next_state = DONE;
else
next_state = ADD;
end
DONE: begin
next_state = IDLE;
end
default: next_state = IDLE;
endcase
 end

// Serial addition and output logic

always @(posedge clk or posedge rst) begin
if (rst) begin
sum <= 0;
carry <= 0;
bit_count <= 0;
done <= 0;
end else begin
case (current_state)
IDLE: begin
sum <= 0;
carry <= 0;
bit_count <= 0;
done <= 0;
end

ADD: begin
// Perform the serial addition
sum <= a ^ b ^ carry;
carry <= (a & b) | (carry & (a ^ b));

// Increment bit counter

bit_count <= bit_count + 1;
end

DONE: begin
done <= 1; // Indicate completion
end
endcase
end
end
endmodule

*/
/*

//////////////////////Signed multiplier////////////////////////////

module signed_multiplier_8x8 (
input signed [7:0] a, // 8-bit signed input A
input signed [7:0] b, // 8-bit signed input B
output reg signed [15:0] product // 16-bit signed output Product
);

// Perform signed multiplication

always @(*) begin
product = a * b;
end

endmodule

*/