Memory test

Introduction
• Memory blocks - very important part of digital circuits
This necessitates different fault models and test
techniques for memory blocks
• No logic gates and FFs
• Need different fault models and test techniques
• Compressed, symmetrical structure with only
reading and writing operations
• Memory technology - capacity quadruples roughly
every 3 years, which leads to decrease in memory price
per bit
 Introduction
• High storage capacity is obtained by raise in density –
decreased size – new dielectric materials (high k)
• New methods for faster access of the memory
• Faulty memory chips not discarded
• During manufacturing test for memory chips, faults are
not only be detected but also their locations are
diagnosed
• Almost all memory chips will have faults in some cells
 Introduction
• Redundant (extra) cells in the memory
• New fault free cell is connected in the appropriate
position – in place of faulty cell
• Blow fuses (using laser) to recreate defective cells to
normal spare cells
• The sole functionality of a cell is to store a bit of
information which is implemented using a capacitor;
when the capacitance is charged, it represents 1 and
when there is no charge, it represents a 0. No logic
gates are involved in memory
 Introduction
• Use of logic gates (in FFs) instead of capacitors to
store a bit of information would lead to a very large
area
• Memory test different from logic test
• New fault models and test procedures required for
testing memories
 Memory architecture
Address bus
Column decoder

Driver
Row decoder Memory cells
(write to cells)

Data in
Sense amplifiers
(read from cells)
Read/write
Data out
 Memory architecture
• Memory read
- row and column decoders determine the location of
cell from the address
-cell of the appropriate row and column gets
connected to the sense amplifier, which sends the
data out
• Memory write: Determine location of the cell from
address
• Special driver circuitry writes the values in the data
bus into the selected cell
 Memory fault models
• Required to check
• Required value (0/1) can be written into a cell
• The stored value can be read from a cell
• The proper cell can be accessed, i.e., the row and
column decoder are fault free
 Memory fault models
• The row and column decoders - digital circuits
implemented using logic gates
• The sense amplifier and driver - analog circuits
• Decoders and sense amplifiers - neither considered as
gate level digital circuits nor as analog circuits
• Functionality of decoders - whether desired cells
accessed based on the address in the address bus
• Amplifiers and drivers - whether they can pass the
values to and from the cells correctly
• Sequentially enter the data and retrieve it – Testing the
blocks indirectly
 Memory fault models
• Stuck-at faults
• Transition faults
• Coupling faults
• Neighborhood patterns sensitive faults
• Address decoder faults
 Stuck at fault
w0
s0 s1 w1

w0
State diagram for a good memory cell
w0 w0
s0 w1 s1 w1
sa0
sa1
State diagram for a sa0 memory cell and a sa1 memory cell
• Logic value of a cell (or line in the sense amplifier or
driver) is always 0 or always 1
• s0 - cell contains 0; s1 – cell contains 1; w1(w0)
indicates the value of 1(0) being written
 Transition fault
w0
w1 s1 w1
s0
w0

State diagram for up transition fault in a memory cell

• Cell fails to make a (0 to 1) or a (1 to 0) transition when

it is written
• Up transition fault - (↑|0) – similar to sa0 fault - can take
and retain value 1 if a 0 has not yet been written
• Down transition fault - (↓|1)
 Coupling fault
• Deviation from normal behavior of a cell because of
coupling with others
• Any two cells can couple and normal behavior
changes in these 2 cells - 2- coupling fault model
• n cells in a memory, then there can be nC2 number of 2-
coupling faults
• Assume that only neighboring cells (decided based on
threshold distance) can be involved in the fault
• Proximity window concept (shifting window)
• Types : (i) inversion coupling faults, (ii) idempotent
coupling faults
 Inversion coupling faults
• Consider two cells – i and j
• Memory cell i is the coupled cell (where fault occurs)
and memory cell j is the coupling cell
• 2-inversion coupling fault - a transition from 0 to 1 or 1
to 0 in memory cell j causes an unwanted change in
memory cell i
• Rising(↑|↨) – implying 0 to 1 change in cell j
complements the content of cell i
• Falling (↓|↨) -- implying 1 to 0 change in cell j
complements the content of cell i
 Inversion coupling faults
w1j
w0j w0i
w0j s01 w1j
w0i s00

w0i w1i w0i w1i

w1j
s10 s11 w1i
w1i
w0j
w0j w1j

The state diagram for 2 cells i and j under normal condition

 Inversion coupling faults
w0j w0i
w0j s01 w1j
w0i s00

w0i
w0i w1i w1j
w1j
w1i

s10 s11
w1i w1i
w0j
w0j w1j
The state diagram for 2 cells i and j under inversion
coupling fault
• Under rising fault condition, if 1 is to be written to cell j,
state changes from s00 to s11
• When 1 is to be written in j when in s00, it makes a 0 to
1 transition. As j is the coupling cell, it complements
the value of the coupled cell i
 Idempotent coupling fault
• In a 2-idempotent coupling fault involving cells i and j,
a transition (0 to 1 and 1 to 0) in memory cell j sets the
value in memory cell i to be 0 or 1
• The four possible 2-idempotent coupling faults
involving cells i, j are
• Rising – 0 (↑/0) – 0 to 1 change in cell j sets the content
of cell i to be 0
• Rising – 1 (↑/1) – 0 to 1 change in cell j sets the content
of cell i to be 1
 Idempotent coupling fault
• Falling – 0 (↓/0) – 1 to 0 change in cell j sets the content
of cell i to be 0
• Falling – 1 (↓/1) – 1 to 0 change in cell j sets the content
of cell I to be 1
 Idempotent coupling fault
w0j w0i
w0j s01 w1j
w0i s00
w1j
w0i
w0i w1i w1i

s10 w1j s11

w1i w1i
w0j
w0j w1j

The state machine for 2 cells i and j under rising – 1

idempotent coupling fault
• Under rising – 1 fault, change in cell j from 0 to 1 sets i
to be 1. This situation is similar to rising inversion
coupling fault
• Unlike rising inversion coupling fault , in rising -1
idempotent fault, there is no transition from s10 to s01
 Bridging fault
• A bridging fault - short circuit between 2 or more cells
• To keep the number of faults within a practical number,
it is assumed that only 2 cells are involved in a
bridging fault
• Two types
• AND bridging fault – result of logic and value stored
in cells - (0,0|0,0), (0,1|0,0), (1,0|0,0) and (1,1|1,1)
• OR bridging fault – result of logic or value stored in
cells (0,0|0,0), (0,1|1,1), (1,0|1,1) and (1,1|1,1)
 Neighbourhood pattern
sensitive coupling faults
• Most important and different kind of fault in memory
• Cells in neighbourhood influence value stored in a
memory cell
• Type-1 and type-2

0 0 1 2
1 3 3 4 5
4 6 7 8
Cell
Under
Test(cut)
Type-1 Type-2
 Neighbourhood pattern
sensitive coupling faults (NPSF)
• Active NPSF (ANPSF)
• Data in base cell changes due to a change in the
pattern of the neighbourhood cells. One
neighbourhood cell has a transition, while the rest of
the neighbourhood (including the base cell) has a given
pattern
• Each base cell must be read in state 0 and state 1, for
all possible deleted neighbourhood pattern changes
• Cij<d0,d1,d3,d4|b> (type1)
• C2(0, ↓ ,0,0|0)
 NPSF
• Passive NPSF (PNPSF)
• Certain neighbourhood pattern prevents the base cell
from changing
• Each base cell must be written and read in state 0 and
in state 1, for all deleted neighbourhood pattern
permutations
• Cij<d0,d1,d3,d4;↓|1>
 PNPSF
• ↑|0 : cell under test can’t be changed from 0 to 1 (initial
value of the cell under test is 0)
• ↓|1 : cell under test can’t be changed from 1 to 0 (initial
value of the cell under test is 1)
• ↨|x : cell under test can’t be changed regardless of its
content
 Address decoder fault
• 4 types of faults (for both reading and writing)
• No cell is accessed for certain address
• No address can access a certain cell
• With a particular address, multiple cells are
simultaneously accessed
• A particular cell can be accessed with multiple
addresses
Testing of memory faults - March test
• Widely used for memory testing
• Steps:
• In increasing order of address of memory cells, write
0s to the cells
• In decreasing order of address of the memory cells,
read the cells (expected value 0) and write 1 to the cells
• In increasing order of address of the memory cells,
read the cells (expected value 1) and write 0 to the cells
• In decreasing order of address of the memory cells,
read the cells (expected value 0)
 March test
Read each
Read each
Address Cell(should get 0) Address Cell(should
9-0 and write 1
9-0 get 0)

9 x 9 0 9 1 9 0 9 0
8 x 8 0 8 1 8 0 8 0
7 x 7 0 7 1 7 0 7 0
6 x 6 0 6 1 6 0 6 0
5 x 5 0 5 1 5 0 5 0
4 x 4 0 4 1 4 0 4 0
3 x 3 0 3 1 3 0 3 0
2 x 2 0 2 1 2 0 2 0
1 x 1 0 1 1 1 0 1 0
0 x 0 0 0 1 0 0 0 0

Address
Address Initial Address Write each 0-9
0-9 content 0-9 Cell with 0 Read each
Cell(should get 1)
and write 0
 March test
• March test : stuck-at fault
• March test tests sa0 and sa1 faults in the cells
because 0 and 1 in each cell is written and read
back
• March test : Transition fault
• Write 0 – read 0 – write 1 - read 1 – can detect (↑|0)
fault
• Write 1 – read 1 – write 0 - read 0 – can detect (↓|1)
fault
 March test
• March test : Coupling fault
• Cannot detect all coupling fault due to sequential
trace – fault masking
Cell traversal Write each
order Cell with 1

k 0 k 1
j 0 j 1
i 0 i 0 1 0

Cell traversalWrite each

order Cell with 0
 March test - Coupling faults
• Inversion rising coupling fault between cell i and j
• Cell j is to be written with 0 and read back
• Value at cell i is to be read and remembered
• Cell j is to be written with 1 and read back
• Value of cell i is to be read and checked that it is
same as the one remembered (i.e., no inversion has
happened)
 March test - Coupling faults
• Inversion falling coupling fault between cell i and j
• Cell j is to be written with 1 and read back
• Value at cell i is to be read and remembered
• Cell j is to be written with 0 and read back
• Value of cell i is to be read and checked that it is
same as the one remembered (i.e., no inversion has
happened)
 March test - Coupling faults
• Idempotent rising - 0 coupling fault (↑|0) between cell i
and j
• Cell j is to be written with 0 and read back
• Cell i is to be written with 1 and read back
• Cell j is to be written with 1 and read back
• Value of cell i is to be read and checked to be 1
 March test - Bridging faults
• Like coupling faults March test can not detect all
bridging faults
• (0,0|0,0), (0,1|0,0), (1,0|0,0) and (1,1|1,1) are the 4 types
of AND bridging faults
• This implies that cells i, j which are involved in bridging
faults must have the four combinations of inputs
00,01,10,11
 March test - Bridging faults
• Following test patterns are required
• write 0 in cells i and j and read back the values
• write 0 in cell i and 1 in cell j and read back the
values
• write 1 in cell i and 0 in cell j and read back the
values
• write 1 in cells i and j and read back the values
• When the cells are read back, contents must remain
the same
 March test: Neighborhood pattern
sensitive faults
• Write 0s into cells 0,1, 2, 3 and 4 (Type 1) and read them
back
• Write a 1 into cell under test (cell 2) and read it
• Can not read 1 if the fault exists
• Similarly March test can be applied to other faults
(NPSF)
• Must be able to access, read and write those cells as
they may not be sequential
 Basics of memory BIST
• For March test an address generator (increasing and
decreasing order) and a data reader/writer is required
• BIST for March test will be simply an LFSR and a data
reader/writer
• As in the case of logic BIST, the LFSR should have
primitive polynomial so that it generates all numbers
from 1 to 2n-1
 Basics of memory BIST
• In addition to this, it must also have following features
• be able to generate all 0 pattern to access the 0th
memory location
• be able to generate forward and reverse order
patterns i.e., if 1-0-2-3 is the sequence of the LFSR
(when initialized with 1), then there should be a
mode to generate the sequence 1-3-2-0
• Area overhead is large for a predetermined pattern
 Basics of memory BIST
• March test requires cell traversal from 0 to n and then
from n to 0
• Contents of cells must be remembered and area
overhead
• March test can be modified by replacing “sequential
read/write” with “arbitrary order read/write”, but
covering all cells without loss in test capability
 Basics of memory BIST

• Test capability will not change if sequence of cell

traversal is any other sequence, for ex. 1-0-2-5-7-3-4-6-
9-8 while moving in ascending order and 1-8-9-6-4-3-7-
2-0 while moving in reverse order
• Sequence depends on LFSR and the seed used
• Standard LFSR can be modified to satisfy the
additional features of memory BIST
 Basics of memory BIST
• In the modified LFSR, the positions of FFs are in
reverse order i.e., X0 (LFSR of BIST) is marked as X2
and X2 (LFSR of BIST) is marked as X0
• Circuitry for feedback from last FF to first FF now
involves NOR gates in addition to XOR gates so that all
0 pattern can also be generated
 Basics of memory BIST
• LFSR generates all the patterns in the range 0 to 23-1
including the all 0 pattern
• The standard seed of the LFSR is 001
• Pattern sequence in decimal is 1-0-4-6-7-3-5-2
• While traversing back, strict reverse order is followed

.
X0 0 0 1 1 1 0 1 0 0

D Q . D Q . D Q
X1
X2
= 0 0 0 1 1 1 0 1 0
1 0 0 0 1 1 1 0 1

X0 X1 X1 X2
X0 X2 (LSB)
 Basics of memory BIST
• For March test, the LFSR should also have a
counterpart that can generate a reverse pattern, i,e., the
reverse LFSR should generate reverse of “1-0-4-6-7-3-
5-2”, which is 1-2-5-3-7-6-4-0 (seed is assumed to be
same for both the LFSR and its reverse counterpart)
• To achieve this reverse shift of data, the D and Q
terminals are to be swapped, in the (forward) LFSR and
numbering of the FFs is to be made in reverse order
The feedback from last FF to the first one will also
have the XOR-NOR gate circuitry (as in the case of
 Basics of memory BIST
• Reverse LFSR with pattern sequence 1-2-5-3-7-6-4-0.
• The standard seed of the LFSR is 001
• All the patterns are required to access the memory
locations
• While traversing back, strict reverse order is followed

.
X0 1 0 1 1 1 0 0 0 1

Q D . Q D . Q D
X1
X2
= 0 1 0 1 1 1 0 0 0
0 0 1 0 1 1 1 0 0

X2 X1 X0
X2 X1
X0 (LSB)